JPH01235495A - Pulsing signal reception circuit - Google Patents

Abstract

PURPOSE:To lighten the burden of a central control circuit, and to prevent erroneous detection due to a sound signal by excluding an input signal to a push-button signal receiver to output button information and a detection signal which respectively varies and disappears within signal supervision time. CONSTITUTION:When the push-button signal receiver 101 detects a push-button signal, it outputs the detection signal and the button information that the push- button signal is encoded, A latch circuit 102 stores this button information temporarily, and a comparison circuit 103 compares and collates the output signal of this latch circuit with the button information. Besides, when the output signal of the comparison circuit 103 and the detection signal of the push-button signal receiver 101 are effective, a counter circuit 104 counts until the prescribed time of the effective duration of these two signals elapses, and when they are invalid, it is reset. Then, the input signal to the push button signal receiver 101 to output the button information and the detection signal to vary and disappear respectively within the prescribed signal supervision time is excluded. Thus, the burden of the central control circuit can be lightened, and the erroneous detection due to the sound signal can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a selection signal receiving circuit for a storage/exchange machine, and more particularly to a selection signal receiving circuit for receiving a push button signal as a selection signal for a storage/exchange machine.

[Conventional technology]

Conventionally, this type of selection signal receiving circuit, as shown in FIG. , thereby causing the central control circuit 302 to connect the terminal DA of the push button signal receiver 301.
The button information output from the TA is read via the gate circuit 303. Alternatively, as shown in FIG. 4, the central control circuit 402 operates the push button signal receiver 401 in synchronization with the clock interrupt signal output from the interrupt control circuit 404 using the clock signal output from the clock generation circuit 405.
The detection signal output from the terminal STB of the gate circuit 403
, thereby scanning the push button signal receiver 40
Read button information output from terminal DATA 1.

[Problem to be solved by the invention]

However, in the conventional selection signal receiving circuit described above, in order to improve reception accuracy, the central control circuit increases the number of times the button information is read, and each time the read button information is compared with the previously read button information. This has the drawback of significantly reducing processing efficiency. In addition, especially in a storage/exchange device that outputs an operation guide message using an audio signal and is capable of receiving a push button signal, the operation guide message using an audio signal may be leaked and mistakenly detected as a push button signal. This has the disadvantage that more thorough scanning is required to eliminate this false detection.

The present invention has been made in view of the above circumstances, and the selection signal receiving circuit of the present invention is capable of reducing the burden on programming during selection signal scanning and eliminating false detections caused by audio signals. It is an object of the present invention to provide a selection signal receiving circuit for

[Means to solve the problem]

In order to achieve the above object, the selection signal receiving circuit according to the present invention is characterized in that the selection signal receiving circuit of a storage exchanger receives a push button signal consisting of a combination signal train of two frequencies within the audio frequency band. a push-button signal receiver that outputs a detection signal indicating that the push-button signal has been detected when a button signal is detected and button information in which the detected push-button signal is encoded; A latch circuit that temporarily stores button information when a detection signal is output, a comparison circuit that compares the output signal of this latch circuit with this button information, and receives the output signal of this comparison circuit and this push button signal. and a counter circuit that counts the valid duration of these two signals until a predetermined time elapses when the detection signal of the device is valid, and is reset when the detection signal is invalid, and is reset within the predetermined signal monitoring time. The aim is to eliminate input signals to push button signal receivers that output changing button information and disappearing detection signals.

〔Example〕

Next, specific embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, 101 is a push button signal receiver;
02 is a latch circuit, 103 is a comparison circuit, 104 is a counter circuit, 105 is an AND circuit, 106 is a delay circuit, 10
7 is a clock generation circuit, 108 is a central control circuit, 109
110 is a gate circuit, and 110 is an interrupt control circuit. Here, when a signal having the frequency spectrum of a push button signal (a signal equivalent to a two-frequency signal within the audio frequency band output from a push button dial telephone) is not input to the terminal SIN of the push button signal receiver 101. , the detection signal output from the terminal STB of the push button signal receiver 101 is in an inactive state of "I" or "II" level,
Further, the output signal of the comparison circuit 103 that compares and collates the button information output from the terminal DATA of the push button signal receiver 101 and the output signal of the latch circuit 102 is transmitted to the comparison circuit 1.
If the output signal of the latch circuit 102 input to the terminal A of the 03 does not match the button information input to the terminal B of the comparison circuit 103, it is in an inactive state at the "L" level. Terminal ST of push button signal receiver 101
The detection signal output from B is a non-inverting logic type delay circuit 10.
6 becomes a latch signal that is input to the input terminal CK of the latch circuit 1020, and the AND circuit 105 converts the AND signal of this latch signal and the output signal of the comparison circuit 103 into a clear signal that is input to the terminal CR of the counter circuit 104. It becomes a signal. The counter circuit 104 is in a clear state when the detection signal outputted from the terminal STB of the push button signal receiver 101 is in an inactive state at "L" level. Here, when a signal having the frequency spectrum of the push button signal is input to the terminal SIN of the push button signal receiver 101, the push button signal receiver 101 outputs a detection signal from the terminal STB after a predetermined card time has elapsed. is changed from the "L" level in the inactive state to the "H" level in the active state. The button information decoded by the push button signal receiver 101 and output from the terminal DATA is "H" when this detection signal is in the active state.
After reaching the level, it is determined, so by giving this detection signal a delay longer than this determination time in the delay circuit 106, the detection signal changes from the inactive state L" level to the active state "°H" level. On the rising edge of , this button information is latched into latch circuit 102 .

This latched button information is held until one detection signal reaches the inactive state of "LI+" level, and during that time, the terminal DA of the push button signal receiver 101
The comparison circuit 103 compares and collates the button information that is continuously output from the TA. When one detection signal is active “
While the level is high, if there is no change in the button information, the output signal of the comparison circuit 103 is in the active state of "HI".
+ level is maintained, and therefore, the counter circuit 104 enters a cleared state and performs a counting operation using clock pulses. When the count value of this clock pulse in the counter circuit 104 reaches a predetermined value set in advance,
The interrupt control circuit 110 inputs the signal output from the terminal Qx of the counter circuit 104 and sends an interrupt request signal to the central control circuit 108, and the central control circuit 108, which has received this interrupt request signal, 109
The detection signal and button information are received for the first time through the . If there is a change in button information while one detection signal is in the active state at the "H" level, the output signal of the comparison circuit 103 immediately changes to the inactive state at the "L+" level. , AND circuit 105
The counter circuit 104 is cleared via the OFF line to stop the monitoring operation. In addition, the detection signal is in the active state °°H''
If the level changes even instantaneously to the inactive "L" level, the AND circuit 105
The counter circuit 104 is cleared and the monitoring operation is temporarily stopped.

FIG. 2 is a timing waveform diagram of an embodiment of the present invention, and is a diagram illustrating a series of operations of the embodiment of the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the processing related to scanning, comparison, and verification of selection signals in the central control circuit, and it is also possible to eliminate erroneous reception due to audio signals. This has the effect of making it possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing waveform diagram of an embodiment of the present invention, and FIGS. 3 and 4 are block diagrams of a conventional selection signal receiving circuit. . 101.301,401...Push button signal receiver, 102...Latch circuit, 103...
... Comparison circuit, 104 ... Counter circuit, 10
5...AND circuit, 106...Delay circuit, 107,405...Clock generation circuit, 1
08,302,402...Central control circuit, 10
9,303,403...gate circuit, 110,
304, 404... Interrupt control circuit.

Claims (1)

[Claims] In a selection signal receiving circuit of a storage/exchange device that receives a push button signal consisting of a combination signal string of two frequencies within the audio frequency band, when a push button signal is detected, the push button outputs the detection signal and encoded button information. a button signal receiver, a latch circuit that temporarily stores the button information when the detection signal is output from the push button signal receiver, and a comparison circuit that compares and matches the output signal of the latch circuit with the button information. and a counter circuit that counts the valid duration of the two signals until a predetermined time elapses when the output signal of the comparison circuit and the detection signal are valid, and is reset when the output signal of the comparison circuit and the detection signal are invalid. . A selection signal receiving circuit, characterized in that an input signal to the push button signal receiver that outputs the button information that changes and the detection signal that disappears within a signal monitoring time is excluded.