JPH01211399A - Dynamic shift register with scanning function - Google Patents

Abstract

PURPOSE:To enable the functional test of a whole LSI to be easily executed by respectively and serially connecting a first memory circuit part and a second memory circuit part or a third memory circuit part and a fourth memory circuit part, connecting the second memory part to the third memory circuit part to share a first capacitor. CONSTITUTION:Switches 21 and 35 which open and close, capacitors 29 and 39 which store an electric signal by accumulating charge and a shift register which is constituted by connecting the memory circuits 1 and 3 consisting of inverters 33 and 37 which output the input shares the capacitor 39. They are connected and controlled by a clock signal. Thus, the capacitor can be controlled from plural paths and the input/output of the electric signal accumulated in the capacitor can be facilitated. As the result of that, the functional test of the whole LSI can be easily executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to LSI, and particularly to custom LSI.

(Prior Art) As a dynamic shift register in an LSI, the one shown in FIG. 7(a) is generally known. This dynamic shift register includes the first and second storage circuit sections 1.3 and 1.3.
are connected in series, and the first
A data input signal is input to the input terminal 5, the second input terminal 9 of the second memory circuit section 3 is connected to the first output terminal 7, and the second output terminal 11 of the second memory circuit section 3 is connected to the first output terminal 7. is connected as an output signal Q to the internal combinational circuit of the LSI. Said first
The first clock signal input terminal 13 of the memory circuit section 1 has a first
A clock signal φ is inputted, a first clock signal i having an inverted potential of the first clock signal φ is inputted to the 1b clock signal input terminal 15, and the first clock signal φ
is the first level (L-0), the first output terminal 7 outputs a signal corresponding to the data input signal. The first clock signal 1 is input to the 2b clock signal input terminal 17 of the second storage circuit section 3, and the inverted 7d of the first clock signal 2 is present at the 2a clock signal Δ terminal 19. When the first clock signal φ is manually input and the first clock signal 1 is a level (L-0), it is inputted from the second output terminal 11 to the second input terminal 9 of the second memory circuit section 3. A signal corresponding to the signal is output.

The first memory circuit section 1 has an input side connected to the first input terminal 5, and a first switch 21 consisting of a transfer gate including an N-channel transistor and a P-channel transistor, and an output terminal 23 of this switch 21. 25 is connected to the first capacitor 29, and the other end 27 is connected to the reference potential (grounded);
The input terminal 31 is connected to the negative terminal 25 of 29 of this first capacitor.
is connected to the inverter circuit 33, and an inverter circuit 33 is connected to the first output terminal 7, and an output side from which an inversion of the input potential is outputted is connected to the first output terminal 7. The second memory circuit section 3 has the same configuration as the first memory circuit section 1.

The operation of this dynamic shift register is as described above. The 1st a+bs 2nd a, b 07 signal input terminal 13 in the second storage circuit section 1.3. i5, 17゜19 No. Rubel (
The first clock signal φ of the level (L-0) and the second level (H-1
), when the first clock signal A of ff
1l The first switch 21 in the storage circuit section 1 is turned on, and a signal corresponding to the data input signal is stored in the first capacitor 29, and the second storage circuit section 3 is stored in the first capacitor 29.
The M2 switch 35 inside is turned off and the output signal stored in the first capacitor 29 is output. or,
Said 1st. Said 1a, b in the second storage circuit section 1.3,
2nd a, b clock signal input terminal 13.15.17.19
When the first clock signal φ of the second level (H-1) and the first clock signal 7 of the first level potential (L-0) are input to the first clock signal φ in the first storage circuit section 1, The switch 21 is turned off, the second switch 35 in the second storage circuit section 3 is turned on, and the potential of the electric signal accumulated in the first capacitor 27 is inverted by the first inverter circuit. , an electric signal corresponding to the input terminal of the second switch 35 is output from the output side, the potential is inverted by the second inverter circuit 37, and the data input signal is input from the second output terminal 11. A data output signal Q corresponding to the signal is output.

In this way, the conventional dynamic shift register is
The first and second switches 21.35 are opened and closed by changing the potential of the input clock signal at a cycle that does not cause the charges stored in S1 and the second capacitor 29.39 to disappear due to leakage or the like. The operation is performed.

FIG. 7(b) shows a dynamic shift register using a clocked inverter that performs the same operation as FIG. 7(a). A clocked inverter 49 in which the clocked inverters 12' and 12' are connected in series and whose input end is connected to the input end 5 of the first storage circuit section 1; The first capacitor 29 is grounded, and the one end 25 of the first capacitor 29 is connected to the first output end 7 of the first memory circuit section 1. The second memory circuit section 3 has the same configuration as the first memory circuit section 1. The clocked inverter 49 has a source connected to a positive power supply potential, a first P channel transistor 41 whose gate is connected to the input terminal 5 of the clocked inverter 49, and a source connected to the drain of the first P channel transistor 41. , the clock signal φ is input to the gate, and the source is connected to the output side of the clocked inverter 49.

a second P-channel transistor 43; a first N-channel transistor 45 whose source is connected to a reference potential (grounded) and whose gate is connected to the input terminal 5 of the clocked inverter 49;
A source is connected to the drain of the clocked inverter 49, a drain is connected to the output side of this clocked inverter 49, and a clock is connected to the gate.

and a second N-channel transistor 47 to which the signal 7 is input. The clocked inverter 49 in the second memory circuit section 3 receives a clock signal φ inputted to the clocked inverter in the first memory circuit section 1 and the gates of the second P channel and N channel transistors 43 and 47.
, 7 are different in that their positions are switched.

The test of the dynamic shift register shown in FIG. 7(a) shows that the first and second switches 21.35, the first and second capacitors 29.39, and the first and second inverters 33.37 are normal. This is a test to see if the dynamic shift register operates as shown in FIG. 7(b).
This is a test to see if the first and second clocked inverters 49 and the first and second capacitors 29 and 39 operate normally.

In the test of the dynamic shift register shown in FIGS. 7(a) and 7(b), data is input to the first input terminal 5 at a specified clock cycle, and a normal result is output from the second output terminal 11. This is done by checking whether the To test an LSI that uses a large number of registers in this way, it is difficult to design a program to set the data input from outside the LSI, and it is difficult to output the test results. This is extremely difficult because it cannot be easily output to the outside of the LSI.

Furthermore, when the clock signal is stopped, a through current flows and the current consumption increases. It was not possible to measure current. Note that an increase in current consumption places a burden not only on the transistors in the CMOS but also on the LSI package, so in highly integrated LSIs that use a large number of dynamic shift registers, it is difficult to stop the clock signal and use the LSI. situation.

(Problem to be solved by the invention) As mentioned above, in the conventional dynamic register, the LS
It was very difficult to create a test input signal from outside.

An object of the present invention is to facilitate testing of dynamic shift registers in order to solve the above problems.

[Structure of the Invention] (Means for Solving the Problems) A dynamic shift register according to the present invention includes a switch that opens and closes, a capacitor that stores an electric signal by storing electric charge, and an inverter that inverts the input and outputs it. A shift register is configured by connecting two memory circuits, each of which shares the capacitor with the other. This dynamic shift register allows electrical signals to be controlled from multiple paths.

(Function) In the device configured as described above, since the capacitor can be controlled from a plurality of paths, it is easy to input and output electrical signals stored in the capacitor.

(Embodiments) The present invention will be described in detail below based on embodiments shown in the drawings.

FIG. 1(a) shows a dynamic shift register existing in an LSI showing an embodiment of the present invention.

This dynamic shift register is the first. The second memory circuit section 1.3 is connected in series, and the third and fourth memory circuit sections 51.53 are further connected in series, and the second memory circuit section 3 is connected in series.
is connected to the third storage circuit section 51 and shares a portion thereof. A data input signal is input to the first input terminal 5 of the first memory circuit section 1, and the second input terminal 9 of the second memory circuit section 3 is connected to the first output terminal 7. The second output terminal 11 of the memory circuit section 3 is connected as an output signal Q to a combinational circuit (not shown) inside the LSI. The data input signal SD is input to the third input terminal 55 of the third memory circuit section 51, and the fourth input terminal 59 of the fourth memory circuit section 53 is connected to the T43 output terminal 57. The fourth output terminal 61 of the memory port 53 is led to an input terminal of another dynamic shift register or an external connection terminal. Said Section 1 t
The first clock signal φ is input to the first clock signal input terminal 13 of the a port 1, and the first clock signal φ is input to the first clock signal input terminal 15 of the a port 1.
1b has an inverted potential of the first clock signal φ.
When the lock signal 7 is input and the first clock signal φ is at the level (L-0), the first output terminal 7 outputs a signal corresponding to the data input signal. Said second
The second clock signal input terminal 17 of the memory circuit section 3 has a first
A clock signal T is input, a first clock signal φ having an inverted potential of the first clock signal 7 is input to the second b clock signal input terminal 19, and the first clock signal ¥
is the second level (L-0), the second output terminal 11 outputs a signal corresponding to the signal input to the second input terminal 11 of the second storage circuit section 3. Since a part of the third memory circuit section 51 is shared with the second memory circuit section 3, the second output terminal 1 of the second memory circuit section 3
1, a signal corresponding to the signal input to the second input terminal 9 is output from the third output terminal 57. Further, the second clock signal A is input to the third clock signal input terminal 63 of the third storage circuit section 51, and the second clock signal A having an inverted potential of the second clock signal A is input to the third b clock signal input terminal 65. When the clock fg No. A signal corresponding to is output. Further, the third clock signal B is input to the fourth a clock signal input terminal 67 of the fourth memory circuit section 53, and the M4
The third clock signal B is input to the b clock signal input terminal 69.
When the third clock signal 1 having an inverted potential of
A signal corresponding to the signal input to the fourth input terminal 59 is outputted from the fourth output terminal 61 .

The first storage circuit section 1 has an input side connected to the first input terminal 5, and a first switch 21 comprising a transfer gate having the first a and b clock signal input terminals, and an output side of the first switch 21. a first capacitor 29 whose one end is connected to the terminal 25 and whose other end is grounded; and a first inverter 33 connected to the output terminal 7. The second, third, and fourth memory circuit sections 3, 51, and 53 have the same configuration as the first memory circuit section 1.

The operation of this dynamic shift register is as described above. Said 1a, b in the second storage circuit section 1.3.

2nd b, ao link signal input terminal 13.15.17°19
The first clock signal φ of the first level potential (L-0) and the first clock signal ■ of the second level potential (H-1) are input to the third memory circuit section 51, and The second level (H-1) is connected to the clock signal input terminal 63°65.
When the clock signal A and the second clock signal A of the second level (L-0) are input, the first switch 21 in the first storage circuit section 1 becomes conductive, and the first switch 21 corresponds to the data input signal. A signal is output from the first output terminal 7, and the potential of this output signal is stored in the first capacitor 29. A second switch 35 in the second memory circuit section 3 and a third switch 7 in the third memory circuit section 51
1 is turned off, and the second. An output signal corresponding to the potential stored in the second capacitor 39 in the second storage circuit section 3 is output from the third output terminal 11.57. Further, when the third clock signal B of the second level and the third clock signal B of the fourth level are input to the fourth a and b clock signal input terminals in the fourth storage circuit section 53, the fourth switch 35 is turned off, and the fourth output terminal 61 outputs an output signal SQ corresponding to the potential stored in the fourth memory circuit section 53. 13, 15. 2nd level (H-1) on 17.19
When the first clock signal φ of the first level and the first clock signal ■ of the second level (L-0) are input, the is turned off, and the second switch 35 in the second storage circuit section 3 is turned on. The electric signal stored in the first capacitor 29 is inverted in potential by the first inverter 33 and input to the input side of the second switch 35, and the electric signal corresponding to this input signal is output to the output side. The potential is inverted at the second impark 37, and an output signal Q corresponding to the data input signal is output from the second output terminal 11. An electrical signal corresponding to the human input signal is stored in the capacitor 39.

Next, the first. Said 1a in the second storage circuit section 1.3
, b, second b, a clock signal input terminal 13.15', 1
7.191: T41 clock signal φ of the first level (L-'o), first clock signal 7 of the second level potential (H-1)
is input, the first switch 21 in the first memory circuit vW section 1 is turned on, the second switch 35 in the second memory circuit section 3 is turned off, and the A potential corresponding to the data input signal is stored in the first capacitor 29 in the first storage circuit section 1.

Next, the fourth a in the fourth memory circuit section 53.

b The clock signal input terminal 67.69 has the th level (L-0)
When the ff13 clock signal B and the third clock signal 1 at the second level (H-1) are input, the fourth switch 73 in the fourth storage circuit section 53 becomes conductive, and the second The output signal SQ corresponding to the electrical signal stored in the capacitor 39 is outputted from the fourth output terminal 61 and stored in the second capacitor 39 in the fourth capacitor 79 in the fourth storage circuit section 53. The inverted potential of the electrical signal that was previously stored is stored.

Next, a third clock signal B of a second level (H-1) and a third clock signal B of a second level (H-1) and a third clock signal B of a second level (L-
0), the fourth switch 73 in the fourth storage circuit section 53 becomes non-conductive, and the fourth capacitor 7 is output from the fourth output terminal 61.
An inverted potential of the potential stored in 9 is output. Next, the second clock signal A of the second level (L-0) and the second clock signal of the second level (H-1) are input to the third a and b clock signal input terminals 63.65 in the third storage circuit section 51. When the signal X is input, the third switch 71 becomes conductive, and the third input terminal 5
An output signal Q corresponding to the data input signal SD input to the input terminal 5 is output, and a potential is accumulated in the second capacitor 39.

Next, the second clock signal A of the second level (H-1) and the second clock signal I of the second level (L-0) are input to the third a, b clock signal input terminals 63.65 of the third switch 71. input, and the fourth switch 73
a, b The clock signal input terminals 67 and 69 are connected to the th level (L-
When the third clock signal B of 0) and the third clock signal 1 of the second level (H-4) are input, the third switch 71 becomes non-conductive, and the fourth switch 73 becomes conductive. state, and the potential corresponding to the data input signal SQ stored in the second capacitor 39 is output from the fourth output terminal 61.

In this way, in the function test of the dynamic shift register, when the first or second level data input signal is input to the first input terminal 5, the state of the first clock signal φ is set, so that the state of the first clock signal φ is set. By transmitting the data of the human input signal [D] as the output signal Q to the second output terminal 11, and further setting the state of the third black signal B, the fourth output terminal 6
1, the data corresponding to the data input signal R2 is transmitted as the output signal SQ, and the data input signal S at the first or second level potential is transmitted to the third terminal 55.
When I is input, by setting the state of the second clock signal A, the output signal Q is output to the second output terminal 11.
It is tested that the data of the data input signal SI is transmitted to the ν terminal 61 as the output signal SQ corresponding to the data input signal SI.

Δ Therefore, the output terminal of the output signal SQ and the input terminal of the input signal SI of another dynamic shift register are connected to the third input terminal 55 and the fourth output terminal 61 of the dynamic shift register of this embodiment, And the second. The third clock signals A and B alternately
), the electrical signal corresponding to the data stored in the second capacitor 39 based on the data input signal SI is shifted to another storage circuit section, and at the same time,
A new next data input signal SI is input from the storage circuit section.

In other words, by repeating this test cycle,
A path from the first input end 5 to the second output end 11 and the fourth output end 61, and a path from the third input end 55 to the second output end 11 and the fourth output end 61. Can be inspected.

In addition, the above-mentioned No. 1. Second. Third. Fourth switch 21; 35.
No. 71 and 73 use a transfer gate, but a P-channel transistor or an N-channel transistor may also be used.

In another embodiment of the invention, shown in FIG. 1(b), the first
．． Second. Third. and a fourth clocked inverter (an inverter that performs a switching operation based on a clock signal and outputs an inverted potential level of an input signal) 49 is a CMO
It is used in LSIs that have an S structure. Each memory circuit section 1. , 3.51.53, each of the clocked inverters 49 has two P-channel transistors 41.43 and two N-channel transistors 45.47 connected in series. The first clocked inverter 49 includes a first P channel transistor 41 whose source is connected to a positive power supply potential and whose gate is connected to the input terminal 5 of the first clocked inverter 49, and a drain of the first P channel transistor 41. A second P-channel transistor 43 has a source connected to the gate, a clock signal φ is input to the gate, and a source connected to the output side of the first clocked inverter 49, and a source connected to the reference power supply (grounded).
, a first N-channel transistor 45 whose gate is connected to the input terminal 5 of the first clocked inverter 49, a source connected to the drain of the first N-channel transistor 45, and a drain connected to the output side of the clocked inverter 49. A second N-channel transistor 47 is connected to the second N-channel transistor 47 and has a gate to which the clock signal (2) is input.

The clocked inverter 49 in the second storage circuit section 3 is connected to the first clocked inverter 49 and the second clocked inverter 49.
The structure differs in that the positions of the clock signals φ and 2, which are manually input to the gates of the P-channel and N-channel transistors 43 and 47, are reversed.

In the third clocked inverter 49 in the third storage circuit section 5, the clock signal A is input to the gate of the second P-channel transistor 43, and the clock signal X is input to the gate of the second N-channel transistor 47. The clocked inverter 49 is configured to be different from the first clocked inverter 49 in the first memory circuit section 1 in this point.

The N4 clocked inverter 49 in the fourth storage circuit section 53 has the clock signal B input to the gate of the second P channel transistor 43 and the clock signal 1 input to the gate of the second N channel transistor 47. , is configured differently from the first clocked inverter 49 in the first memory circuit section 1.

Said 1st. Second. Third. Fourth memory circuit section 1.3°51.
53 capacitors 27, 39.79 are connected to the output side of each clocked inverter 49, and the first .
m2. Third. The connection structure of the fourth memory circuit section 1.3, 51.53 is the same as that shown in FIG. 1(a). Further, the operation of this embodiment is similar to that of the embodiment shown in FIG. 1(a).

Incidentally, in the embodiment using a clocked inverter shown in FIG. 1(b), the circuit area can be reduced by combining a switch and an inverter.

Furthermore, especially in the embodiment shown in FIGS. 1(a) and 1(b), output signals corresponding to two input signals can be outputted from two output terminals under control using a clock signal, making it possible to accurately perform LSI functional tests. Do this, the second and fourth output terminals 11.6
1 is located outside the dynamic shift register, the load is reduced, and there is an advantage that the LSI function test can be performed even with the use of an inverter with a small driving capacity.

FIG. 1(e) is a logic symbol of the embodiment shown in FIGS. 1(a) and (b). Next, as shown in FIG. 2, the connection relationships of this embodiment in the LSI will be explained using these logic symbols. When the circuit according to the embodiment of the present invention shown in FIG. 1 is applied to the LSI 81 as shown in FIG. 2, the input signal S!
A dynamic shift register 83.85.87 is constructed using the output signal SQ as a path. The input signal and the output signal Q are connected via the output of the combinational circuit 89 in the LSI 81 or an input buffer 91. Further, clock signals φ, A, B and data input signal SI are inputted to the input end connected to the outside of the LSI 81, and further transmitted to the dynamic shift registers 83, 85, 87, etc. via an input buffer 92. is input. The data output signal SQ of the dynamic shift register 87 is sent to the LSI 81 via an output buffer 94.
is output to the external output terminal.

The timing chart shown in FIG. 3 is based on the LS shown in FIG.
This is to explain the test I. First, with the first clock signal φ set to the first level, the electric signal accumulated in the first capacitor 29 in the first memory circuit section is By temporarily setting the clock signal φ to the second level, the data output signal Q is outputted from the second output terminal 11. Next, when the first clock signal φ is set to the first level again and the third clock signal B is set to the second level, the electric signal held in the second capacitor 39 in the second storage circuit section 3 is The signal is transferred to the fourth capacitor 79 in the fourth storage circuit section 61.

Next, the second clock signal A is set to the first level, and the third clock signal B is set to the second level, so that the data output signal Q corresponding to the external data input signal SI is output, and the electric power is output. The signal is held in the second capacitor 39 in the second storage circuit section 3.

then the second clock signal A is set to a second level;
Further, by setting the third clock signal B to the third level, the electric signal held in the memory circuit section 3 is outputted from the fourth output terminal.

In this way, the second. By repeating the cycle of alternately setting the third clock signals A and B to the third level, the second capacitor 39 in the second storage circuit section 3 temporarily holds the data as an electric signal, and then It is output from the fourth output terminal 61 as a data output signal SQ.

When the clock signal φ is set to the second level after data input signals corresponding to the number of existing dynamic shift registers are transmitted, the result of the combinational circuit 89 is changed from the input signals of all the dynamic shift registers to the second level.
The signal is transferred to the second capacitor 39 in the memory circuit section 3.

For static current consumption measurement, the above-mentioned 1. 2nd degree: By setting all of the third clock signals φ, A, and B to the first value, the input state of the second inverter 37 becomes unstable, which is stabilized by the constant charges of the first and second capacitors 29 and 39. This circuit is stable and static current consumption can be measured because no through current occurs. Measuring static current consumption is an effective method for discovering physical abnormalities in transistors. Especially in 0MO3, static current consumption is usually extremely small, so if a large static current consumption is measured, the internal transistor Short circuits, etc. are predicted, and defective products can be easily eliminated.

The second embodiment of the present invention shown in FIG. 4(a) is similar to that shown in FIG.
In the first embodiment shown in a), the third switch 71 in the third memory circuit section 51 is connected to the connection line between the first switch 21 in the first memory circuit section l and the first capacitor 29. and the third inverter circuit section 93 are connected to each other. Second. The third and fourth storage circuit units 1, 3, 51, 53 are connected. The operation of this embodiment is such that the 1a and 2b clock signal input terminals 13.19 of the first and second switches 21.35 of the first and second storage circuit sections 1.3 are connected to a level (L-0). The first clock signal φ of the second level (H-1) is inputted to the 1b and 28th clock signal input terminals 15.17, and the third switch of the third storage circuit section 51 is input. 71
A second level (H-
The second clock signal A of 1) is inputted, the second clock signal λ of the first level (L-0) is inputted to the third b clock signal input terminal 65, and the second clock signal λ of the first level (L-0) is inputted to the third b clock signal input terminal 65.
When a data input signal is input to the first storage circuit section 1, an electrical signal corresponding to the data input signal is stored in the first storage circuit section 1. Subsequently, when the first clock signal .phi. continue,
The clock signal B of the 4th level is input to the m4a clock signal input terminal 67, and the 4b clock signal input terminal 6
When the third clock signal stone of the second level is input to 9,
A data output signal SQ corresponding to the data input signal is outputted from the fourth output terminal 61 of the fourth storage circuit section 53. Subsequently, the third clock signal B of the second level is input to the fourth a clock signal input terminal 67, and the third clock signal B of the fourth
Clock signal input terminal 69t: The third clock signal 100 of the third level is input, and the fourth switch 73 becomes unequal 9, and the 3a clock signal input terminal 63 of the third switch 71 The second clock signal A of the second level is inputted, and the second clock signal X of the second level is inputted to the third b clock signal input terminal 65, and the third switch 71 becomes conductive, and the third input terminal 55 becomes conductive. An output signal Q corresponding to the input data input signal SI is outputted from the second output terminal 11, and the electrical signal is stored in the first capacitor 29 of the first storage circuit section 1. Furthermore, the above-mentioned 3. When the potential level of the clock signal input to the fourth switch 71.73 is inverted and input, the third switch 71.
1 becomes non-conductive, the fourth switch 73 becomes conductive, and a data output signal SQ corresponding to the data input signal input to the third input terminal 55 is output from the fourth output terminal 61. In this way, different data input signals are input from the two input terminals, and depending on the five states of the clock signal,
By outputting a data output signal corresponding to the data input signal from the two output terminals, the same effect as that of the embodiment shown in FIG. 1(a) can be obtained.

An embodiment using the clocked inverter shown in FIG. 4(b) and performing the same operation as in FIG. 4(a) is also available.
) has the same effect as the embodiment shown in ().

In addition, especially the above-mentioned No. 2. Since the fourth output terminal 11.61 is located outside the dynamic shift register, the load is small and the function test can be carried out even if an inverter with a small driving capacity is used.

The configuration of the embodiment shown in FIG. 5(a) is as follows:
and the second memory circuit section 3 are connected in series, and '! J3
The memory circuit unit 51 and the fourth memory circuit unit 53 are connected in series, and each of these memory circuit units 1゜3.51.53 has an input end and an output end, and the second memory circuit The section 3 and the fourth memory circuit section 53 are connected. Said 1st. Second. 3rd degree.

and the fourth storage circuit section 1, 3, 51, 53 are respectively the first
The third storage circuit section 51 has a switch, a capacitor, and an inverter having almost the same configuration as the embodiment shown in the figure.
has a third capacitor 79 that is not shared with other memory circuit sections; The second inverter 3.7 and the second capacitor 39 of the fourth storage circuit section 3.53 are shared, and the second output terminal 11 and the fourth output terminal 61 are common.

The operation of this embodiment is as follows: the first and second storage ports 1.
3 first and second switches 21.35 18th and second
The first clock signal φ at the 19th level (L-0) is input to the b clock signal input terminal 13.19, and the first clock signal φ at the second level (H-1) is input to the 1b and 2a clock signal input terminals 15°17. φ is input, and the first
A data input signal is input to the input terminal 5, the first switch 21 is turned on, and the second switch 35 stores an electric signal corresponding to the data input signal in the first storage circuit section 1. Subsequently, when the potentials of the first clock signals φ and ¥ are inverted, data output signals Q and SQ corresponding to the data input signals are outputted to the second and fourth output terminals 11 . 61, and an electrical signal corresponding to the data input signal is stored in the second capacitor 39. Subsequently, the ml switch 21 is turned on and the second
When the switch 35 is in a non-conductive state, the second clock signal A of the third level is inputted to the first 38th clock signal input terminal 631 of the third switch, and the second level clock signal A is input to the m3b clock signal input terminal 65. is input, the third switch 71 becomes conductive, and the data input signal S! is input to the third input terminal 55. An electrical signal corresponding to the above is stored in the first capacitor 79 in the third storage circuit section 51. Next, the third a and b clock signal input terminals 63.6
5 is inverted, the third switch becomes non-conductive, and the third clock signal B of the fourth level is input to the fourth a clock signal input terminal 67.
is input, and the third clock signal of the second level is input to the fourth b clock signal input terminal 69,
The fourth switch 73 becomes conductive, and the output signals Q and SQ corresponding to the data input signal SI input to the third input terminal 55 are output from the second and fourth output terminals, and the second
An electrical signal corresponding to the data input signal SI is stored in the capacitor 39. As described above, the clock signal causes the switches in each storage circuit section to operate, and the output terminal receives the data input signal input to the two input terminals. A corresponding output signal is output, and the effect is almost the same as the embodiment shown in FIG. 1(a).

An embodiment using the clocked inverter shown in FIG. 5(b) and performing the same operation as in FIG. 5(a) is also shown in FIG. 5(a).
) has the same effect as the embodiment shown in ().

The configuration of the embodiment shown in FIG. 6(a) is as follows:
and the second memory circuit section 3 are connected in series, and the third memory circuit section 51 and the fourth memory circuit section 57 are connected in series. Each has an input end and an output end, and the first memory circuit section 1 and the fourth memory circuit section 53 are connected. Said 1st.
Second. 3rd degree and 4th ta mouth part 1.3.51.53
has a switch, a capacitor, and an inverter each having substantially the same configuration as the embodiment shown in FIG.
The memory circuit section 51 includes a third capacitor 97 that is not shared with other memory circuit sections, and the first... Fourth storage circuit section 1, 5
The capacitor 29 and inverter 33 of No. 3 are shared, and the first output terminal 7 and the fourth output terminal 61 are connected in series.

The operation of this embodiment is as follows: the first and second memory circuit sections 1.
3 first and second switches 21.35 18th and second
b The clock signal input terminal 13.19 has the th level (L-0)
a clock signal φ of the first storage circuit section 1 is inputted, and a clock signal f of a second level (H-1) is inputted to the 1b and 2a clock signal input terminals 15.17; When a data input signal is input, a data output signal SQ corresponding to the data input signal is output from the fourth output terminal 61, and a data output signal SQ corresponding to the data input signal is outputted to the first storage circuit section 1. The electrical signals generated are stored. Subsequently, when the level potentials of the clock signals φ and M are inverted, a data output signal Q corresponding to the data input signal is outputted from the second output terminal 11 of the second storage circuit section 3; An electrical signal corresponding to the data input signal is stored in the second capacitor 39.

Next, the M3 switch 71. The clock signal A of the third level is input to the third a clock signal input terminal 63 of the third level.
A second level clock signal is input to the clock signal input terminal 65, and the third switch 71 becomes conductive.
A data input signal SI is inputted to the third input terminal 55, and an electrical signal corresponding to this data input signal S1 is outputted from the third output terminal 57. Subsequently, the level potential of the signal input to the third switch is inverted, the clock signal B of the level 4 is input to the 4a clock signal input terminal, and the second level clock signal is input to the 4b clock signal input terminal. When the signal ■ is input, the third switch 71 becomes non-conductive, and the fourth switch 73 becomes conductive, so that the data input from the electrical fourth output terminal 61 to the third input terminal 55 is A data output signal SQ corresponding to the signal SI is output, and a data input signal S is supplied to the first capacitor 29.
An electrical signal corresponding to I is stored. In this way, different data input signals are inputted from the two input terminals, and data output signals corresponding to the data input signals are outputted from the two output terminals depending on the state of the clock signal. This embodiment has almost the same effect as the embodiment described above.

An embodiment using the clocked inverter shown in FIG. 6(b) and performing the same operation as FIG. 6(a) is also available as shown in FIG. 6(a).
) has the same effect as the embodiment shown in ().

As described above, in each embodiment of the present invention, testing of dynamic shift registers and combinational circuits is facilitated. Furthermore, while the clock signal is stopped, the LSI becomes usable, and static current consumption can be measured to check for physical abnormalities in the transistors in the CMo5.

Note that the present invention allows the dynamic shift register with scan function of the present invention to be incorporated into an LSI even in a configuration other than the present embodiment, as long as it is composed of four memory circuits that operate in the same manner as the present embodiment. It is possible to easily perform a functional test of the entire LSI.

[Brief explanation of the drawing]

FIG. 1(a) is a block diagram of a dynamic register with scan function showing a first embodiment of the present invention, and FIG.
) is a block diagram of a dynamic shift register with a scan function using a clocked inverter that performs the same operation as that shown in FIG. 1(a), and FIG.
FIG. 4(a), FIG. 5(a) and FIG. 6(a) are timing diagrams of the circuit shown in FIG. 4(b) is a configuration diagram of a dynamic shift register with a scanning function shown in FIG.
), Figure 5(b), and Figure 6(b) are respectively similar to Figure 4(a).
), FIG. 7(a) is a configuration diagram of a dynamic shift register with a scan function using a clocked inverter that performs the same operation as in FIG. 5(a) and FIG. 6(a), and FIG.
) is a configuration diagram of a conventional dynamic shift register, and FIG. 7(b) is a conventional dynamic shift register using a clocked inverter that performs the same operation as FIG. 7(a). ...First output terminal, 9...Second input terminal, 1
1... Second output end, 21... First switch, 2
9... first capacitor, 33... first inverter,
35... Second switch, 37... Second inverter, 39... Second capacitor, -49... Clocked inverter, 51... Third storage circuit section, 53
. . . fourth storage circuit section, 55 . . . third input terminal 57
...Third output terminal, 59...Fourth input terminal, 61.
...4th output terminal, 71...3rd switch, 73.
...Fourth switch, 79...Fourth capacitor, 9
3...Third inverter, 95...Fourth inverter, 97...Third capacitor

Claims (5)

[Claims] (1) a first input terminal to which a data input signal D is input; a first switch whose state is set according to the level of a first clock signal; one end connected to the first input terminal; a first capacitor connected to the other end of the switch, the other end connected to a reference potential, and storing an electrical signal; an input end connected to the other end of the first switch and one end of the first capacitor; A first inverter that outputs an inverted input potential; and a first output terminal that is connected to the output terminal of the first inverter and outputs an output signal.
a memory circuit section; like the first memory circuit section, it has a second input terminal, a second switch, a second capacitor, a second inverter, and a second output terminal; the second input terminal is The second switch is connected to the first output terminal of the first storage circuit section, and the second switch is connected to the first output terminal of the first storage circuit section.
a second storage circuit section that is set to a different state from the switch and outputs the data output signal Q from the second output terminal; a third input terminal that receives the data input signal SI; and a level of the second clock signal. a third switch, one end of which is connected to the third input terminal, one end of which is the other end of the third switch, the other end of the second switch of the second storage circuit section, the second one end of the capacitor and the second
a third inverter connected to an input end of the inverter, the input potential is inverted and outputted; and a third output end connected to the output end of the third inverter, and an output signal is outputted; a third memory circuit unit that shares the second capacitor of the two memory circuit units; and a fourth input terminal, a fourth switch, a fourth inverter, and a fourth output terminal, similar to the first memory circuit unit. and the fourth
The input terminal is connected to the third output terminal of the third storage circuit section, the state of the fourth switch is set according to the level of the third clock signal, and the data output signal SQ is output from the fourth output terminal. A dynamic shift register with a scan function, comprising: a fourth storage circuit section. (2) The third storage circuit unit has a third input terminal to which the data input signal SI is input, and a third switch whose state is set depending on the level of the second clock signal, and one end of which is connected to the third input terminal. and one end is connected to the other end of the third switch, the other end of the first switch of the first storage circuit section, one end of the first capacitor, and the input end of the first inverter, so that the input potential is inverted. and a third output terminal connected to the output terminal of the third inverter and outputting an output signal, and sharing the first capacitor of the first storage circuit section. A dynamic shift register with a scan function according to claim 1. (3) Similarly to the first storage circuit section, a third input terminal and a third
It has a switch, a third capacitor, and a third output terminal,
a third storage circuit, wherein a data input signal SI is input to the third input terminal, a state of the third switch is set according to a level of the second clock signal, and an output signal is output from the third output terminal; one end is connected to the output terminal of the third inverter of the third storage circuit section, and the other end is connected to the other end of the second switch of the second storage circuit section, one end of the second capacitor, and the third inverter of the third storage circuit section. a fourth switch connected to the input terminal of the second inverter and whose state is set according to the level of the third clock signal; and a fourth output terminal from which the data output signal SI is output; 2. The dynamic shift register with a scan function according to claim 1, further comprising a second capacitor, a second inverter, and a fourth storage circuit section that shares the second output terminal. (4) One end is connected to the output end of the third inverter of the third storage circuit section, and the other end is connected to the other end of the first switch of the first storage circuit section, one end of the first capacitor, and the third inverter of the third storage circuit section. a fourth switch connected to the input end of the first inverter and whose state is set depending on the level of the third clock signal;
a fourth output terminal from which a data output signal SQ is output;
4. The dynamic shift register with a scan function according to claim 3, further comprising a fourth memory circuit section that shares the first capacitor, first inverter, and first output terminal of the first memory circuit section. (5) Claim (1) or (1) characterized in that the first, second, third, and fourth switches and the first, second, third, and fourth inverters are constituted by clocked inverters. 2
), or the dynamic shift register with a scan function described in (3) or (4).