JPH01218035A - Inspection of semiconductor device - Google Patents
Inspection of semiconductor deviceInfo
- Publication number
- JPH01218035A JPH01218035A JP4385388A JP4385388A JPH01218035A JP H01218035 A JPH01218035 A JP H01218035A JP 4385388 A JP4385388 A JP 4385388A JP 4385388 A JP4385388 A JP 4385388A JP H01218035 A JPH01218035 A JP H01218035A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor
- semi
- finished
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000007689 inspection Methods 0.000 title abstract description 7
- 239000000523 sample Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000012360 testing method Methods 0.000 claims description 11
- 230000007547 defect Effects 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 9
- 238000000465 moulding Methods 0.000 abstract description 6
- 239000011265 semifinished product Substances 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 9
- 239000000047 product Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体装置の検査方法に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a method for testing a semiconductor device.
(従来の技術)
一般に、半導体装置は、以下のような工程により製造さ
れる。(Prior Art) Generally, a semiconductor device is manufactured by the following steps.
すなわち、まず半導体ウェハ上に精密写真転写技術等に
より多数の半導体チップを形成し、この後、個々の半導
体チップに切断する。そして、この半導体チップをリー
ドを有する基体、例えばリードフレームに配置し、半導
体チップの電極パッドとリードフレームのリードとを例
えばワイヤボンディング等によって接続する。しかる後
、例えばモールド等により半導体チップの保護体を形成
し、半導体装置を得る。なお、例えばTAB(tape
automated bondlng)等により基板
上に半導体チップを実装した半導体装置もある。That is, first, a large number of semiconductor chips are formed on a semiconductor wafer by precision phototransfer technology or the like, and then the semiconductor wafer is cut into individual semiconductor chips. Then, this semiconductor chip is placed on a base having leads, such as a lead frame, and the electrode pads of the semiconductor chip and the leads of the lead frame are connected by, for example, wire bonding or the like. Thereafter, a protector for the semiconductor chip is formed by, for example, molding, and a semiconductor device is obtained. Note that, for example, TAB (tape
There are also semiconductor devices in which a semiconductor chip is mounted on a substrate using an automated bonding method or the like.
そして、一般に上述のような半導体装置の製造工程では
、半導体ウェハの状態でのプローブ装置を用いた検査と
、ハンドラあるいは基板検査装置等を用いた完成品の半
導体装置の検査が行われている。In general, in the semiconductor device manufacturing process as described above, the semiconductor wafer is inspected using a probe device, and the finished semiconductor device is inspected using a handler, a substrate inspection device, or the like.
また、本発明者等は、完成品の半導体装置を、トレイ上
に配置°して検査する方法を、特願昭61−29964
6、特願昭62−158924等で提案している。The inventors of the present invention also proposed a method for inspecting a finished semiconductor device by placing it on a tray in Japanese Patent Application No. 61-29964.
6. It has been proposed in Japanese Patent Application No. 158924/1984.
(発明が解決しようとする課8)
上述のように従来は、半導体ウェハの状態および完成品
の半導体装置の検査を行っている。したがって、例えば
ワイヤボンディングの不良等、半導体ウェハの状態での
検査後に生じた不良は、完成後でなければ発見すること
ができず、生産性の低下を招くという問題があった。(Problem 8 to be Solved by the Invention) As described above, conventionally, the state of semiconductor wafers and finished semiconductor devices have been inspected. Therefore, defects such as defects in wire bonding, which occur after the semiconductor wafer is inspected, cannot be discovered until after the semiconductor wafer is completed, which poses a problem of lowering productivity.
また、完成品の状態での検査では、完成品のリード部分
が曲ってしまうために、モールドによる製品不良の割合
が少ない割に、連続的に検査するハンドラにおいて生産
がとどこおる問題があった。In addition, when inspecting the finished product, the lead portion of the finished product is bent, so there is a problem in that production is delayed in the handler that continuously inspects the product, even though the percentage of product defects due to molding is small.
本発明は、かかる従来の事情に対処してなされたもので
、半導体チップの電極パッドと基体のリードとを接続し
た状態の半完成品の半導体装置を、効率良く検査するこ
とができ、従来に較べて生産性の向上を図ることのでき
る半導体装置の検査方法を提供しようとするものである
。The present invention has been made in response to such conventional circumstances, and enables efficient inspection of a semi-finished semiconductor device in which the electrode pads of the semiconductor chip and the leads of the base body are connected. It is an object of the present invention to provide a semiconductor device testing method that can improve productivity in comparison.
[発明の構成]
(課題を解決するための手段)
すなわち本発明は、半導体チップの電極パッドと基体の
リードとを接続した状態の半完成品の半導体装置を位置
決め機構を有するトレイ上に複数配置し、この後前記ト
レイを搬送、位置決めし、しかる後前記リードに探針を
接触させて前記半完成品の半導体装置の電気的な検査を
行うことを特徴とする。[Structure of the Invention] (Means for Solving the Problems) That is, the present invention provides a method for arranging a plurality of semi-finished semiconductor devices in which the electrode pads of the semiconductor chip and the leads of the base are connected on a tray having a positioning mechanism. After that, the tray is transported and positioned, and then the semi-finished semiconductor device is electrically inspected by bringing a probe into contact with the lead.
(作 用)
上記構成の本発明の半導体装置の検査方法では、半導体
チップの電極パッドと基体のリードとを接続した状態の
半完成品の半導体装置、例えばモールド前のリードフレ
ーム状態の半導体装置を、位置決め機構を有するトレイ
上に複数配置し、このトレイを搬送、位置決めし、リー
ドに探針を接触させて、半完成品の半導体装置の電気的
な検査を行う。(Function) In the semiconductor device inspection method of the present invention having the above configuration, a semi-finished semiconductor device in which the electrode pads of the semiconductor chip and the leads of the base are connected, for example, a semiconductor device in a lead frame state before molding, is inspected. A plurality of devices are arranged on a tray having a positioning mechanism, the tray is transported and positioned, and a probe is brought into contact with a lead to electrically test a semi-finished semiconductor device.
したがって、例えばワイヤボンディングの不良等、半導
体ウェハの状態での検査後に生じた不良をモールド前に
発見することができ、従来に較べて生産性の向上を図る
ことができる。また、トレイ上に半完成品の半導体装置
を複数配置するので、例えば大型基板用プローブ装置等
を用いて効率良く検査することができる。Therefore, defects such as wire bonding defects that occur after inspection of the semiconductor wafer can be detected before molding, and productivity can be improved compared to the conventional method. Further, since a plurality of semi-finished semiconductor devices are arranged on the tray, it is possible to efficiently inspect the semiconductor devices using, for example, a probe device for large substrates.
さらに、リード曲りのための検査の停止を防ぐことがで
き、生産性の向上が得られる。Furthermore, it is possible to prevent inspection from being stopped due to lead bending, resulting in improved productivity.
(実施例)
以下本発明の半導体装置の検査方法の実施例を図面を参
照して説明する。(Example) Hereinafter, an example of the semiconductor device testing method of the present invention will be described with reference to the drawings.
例えば矩形の板状に形成されたトレイ1は、絶縁材料か
らなり、所定サイズ例えば大型基板用プローブ装置によ
って検査可能な基板と同等なサイズとされており、この
トレイ1には、複数の凹部2が列設されている。For example, the tray 1 formed into a rectangular plate shape is made of an insulating material and has a predetermined size, for example, the same size as a board that can be inspected by a large board probe device. are set up in a row.
これらの凹部2は、半導体チップの電極パッドと基体の
リードとを接続した状態の半完成品の半導体装置、例え
ばリードフレーム3aのリードと半導体チップ3bの電
極パッドとをワイヤー30によってボンディングした状
態の半完成品の半導体装置3を収容するとともに、この
リードフレーム状態の半導体装置3を所定精度、例えば
大型基板用プローブ装置でリードに探針を接触可能な精
度に位置決めすることができるよう構成されている。These recesses 2 are formed in a semi-finished semiconductor device in which the electrode pads of the semiconductor chip and the leads of the base are connected, for example, the leads of the lead frame 3a and the electrode pads of the semiconductor chip 3b are bonded by wires 30. It is configured to accommodate a semi-finished semiconductor device 3 and to position the semiconductor device 3 in a lead frame state with a predetermined accuracy, for example, to an accuracy that allows a probe to touch a lead using a probe device for large substrates. There is.
そして、上記トレイ1の各凹部2に、半完成品の半導体
装置3を配置し、例えば大型基板用プローブ装置を用い
て、搬送、位置決めし、第2図に示すように、リードフ
レーム3aのリードに探針4を接触させて、半完成品の
半導体装置3の電気的な検査を行う。Then, semi-finished semiconductor devices 3 are placed in each recess 2 of the tray 1, and transported and positioned using, for example, a probe device for large substrates.As shown in FIG. The semi-finished semiconductor device 3 is electrically inspected by bringing the probe 4 into contact with the semi-finished semiconductor device 3.
したがって、例えばワイヤボンディングの不良等、半導
体ウェハの状態での検査後に生じた不良をモー”ルビ前
に発見することができ、従来に較べて生産性の向上を図
ることができる。また、トレイ1上に半完成品の半導体
装置3を複数配置し、大型基板用プローブ装置を用いて
検査を行うので、特別な検査装置を必要とすることなく
、効率良く検査することができる。Therefore, defects such as wire bonding defects that occur after the semiconductor wafer is inspected can be detected before the semiconductor wafer is inspected, and productivity can be improved compared to the conventional method. Since a plurality of semi-finished semiconductor devices 3 are placed on top and tested using a probe device for large substrates, testing can be carried out efficiently without the need for a special testing device.
なお、上記実施例では、リードフレーム3aのリードと
半導体チップ3bの電極パッドとをワイヤー3Cによっ
てボンディングした状態の半完成品の半導体装置3につ
いて説明したが、その他の半完成品の半導体装置、例え
ばTABによってボンディングを行い、テープを切断し
た後の半完成品の半導体装置、あるいは基板上に直接半
導体チツブを搭載したC OB (chlp on b
oard )の半完成品の半導体装置等でも同様にして
検査することができる。また、COBの半完成品の半導
体装置の検査を行う場合、基板の大きさによっては、ト
レイ1を使用せずに検査することも可能である。In the above embodiment, the semi-finished semiconductor device 3 in which the leads of the lead frame 3a and the electrode pads of the semiconductor chip 3b are bonded with the wire 3C has been described, but other semi-finished semiconductor devices, such as A semiconductor device is a semi-finished product after bonding is performed by TAB and the tape is cut, or a COB (chlp on b) is a semiconductor device with a semiconductor chip mounted directly on the substrate.
Semi-finished semiconductor devices and the like can also be inspected in the same manner. Furthermore, when inspecting a COB semi-finished semiconductor device, it is possible to inspect it without using the tray 1 depending on the size of the substrate.
さらに、トレイ内にモールドされた完成品を設置して完
成品検査も行うことができる。Furthermore, it is also possible to inspect the finished product by placing the molded finished product in the tray.
[発明の効果]
上述のように、本発明の半導体装置の検査方法では、半
導体チップの電極パッドと基体のリードとを接続した状
態の半完成品の半導体装置を、効率良く検査することが
でき、従来に較べて生産性の向上を図ることができる。[Effects of the Invention] As described above, the semiconductor device testing method of the present invention can efficiently test a semi-finished semiconductor device in which the electrode pads of the semiconductor chip and the leads of the base are connected. , it is possible to improve productivity compared to the conventional method.
第1図は本発明の一実施例の半導体装置の検査方法を説
明するためのトレイの平面図、第2図は第1図のトレイ
上に半完成品の半導体装置を配置して探針を接触させた
状態を示す側面図である。
1・・・・・・トレイ、2・・・・・・凹部、3・・・
・・・半完成品の半導体装置。
筒1 ワ
驚22FIG. 1 is a plan view of a tray for explaining a semiconductor device testing method according to an embodiment of the present invention, and FIG. 2 shows a semi-finished semiconductor device placed on the tray shown in FIG. FIG. 3 is a side view showing a state in which they are in contact. 1...Tray, 2...Recess, 3...
...Semi-finished semiconductor device. Tube 1 Wa surprise 22
Claims (1)
続した状態の半完成品の半導体装置を位置決め機構を有
するトレイ上に複数配置し、この後前記トレイを搬送、
位置決めし、しかる後前記リードに探針を接触させて前
記半完成品の半導体装置の電気的な検査を行うことを特
徴とする半導体装置の検査方法。(1) A plurality of semi-finished semiconductor devices with the electrode pads of the semiconductor chip and the leads of the base body connected are placed on a tray having a positioning mechanism, and then the tray is transported;
1. A method for testing a semiconductor device, which comprises positioning and then electrically testing the semi-finished semiconductor device by bringing a probe into contact with the lead.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63043853A JPH07107911B2 (en) | 1988-02-26 | 1988-02-26 | Semiconductor device inspection method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63043853A JPH07107911B2 (en) | 1988-02-26 | 1988-02-26 | Semiconductor device inspection method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01218035A true JPH01218035A (en) | 1989-08-31 |
JPH07107911B2 JPH07107911B2 (en) | 1995-11-15 |
Family
ID=12675270
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63043853A Expired - Lifetime JPH07107911B2 (en) | 1988-02-26 | 1988-02-26 | Semiconductor device inspection method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07107911B2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5335407U (en) * | 1976-09-01 | 1978-03-28 | ||
JPS62147741A (en) * | 1985-12-20 | 1987-07-01 | Nec Corp | Substrate for sorting semiconductor element and sorting method for the element |
-
1988
- 1988-02-26 JP JP63043853A patent/JPH07107911B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5335407U (en) * | 1976-09-01 | 1978-03-28 | ||
JPS62147741A (en) * | 1985-12-20 | 1987-07-01 | Nec Corp | Substrate for sorting semiconductor element and sorting method for the element |
Also Published As
Publication number | Publication date |
---|---|
JPH07107911B2 (en) | 1995-11-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100681772B1 (en) | Method and apparatus for testing semiconductor devices | |
JP2002040095A (en) | Semiconductor device and mounting method thereof | |
KR100585142B1 (en) | Structure of flip chip semiconductor package for testing a bump and method of fabricating the same | |
JPH02211648A (en) | Semiconductor device | |
JP2003031595A (en) | Manufacturing method for semiconductor package, and the semiconductor package | |
JPH0685019A (en) | Semiconductor wafer and its testing method | |
JPH01218035A (en) | Inspection of semiconductor device | |
JPS62261139A (en) | Semiconductor device | |
JPH11111650A (en) | Manufacture of semiconductor device, and jig used thereof and semiconductor device | |
JPH0645419A (en) | Semiconductor device | |
JPH06151535A (en) | Semiconductor wafer and its testing method | |
JP2005345271A (en) | Test socket and manufacturing method of semiconductor device | |
JPS6222448A (en) | Wafer to which ic is formed | |
JPH03104252A (en) | Manufacture of tape carrier | |
JPH0439950A (en) | Semiconductor device | |
JP2010114161A (en) | Inspecting method for semiconductor wafer, and inspecting device for semiconductor wafer | |
JPS62279648A (en) | Semiconductor integrated circuit device | |
JPS61187354A (en) | Semiconductor integrated circuit device | |
JPH0220034A (en) | Semiconductor device | |
JP3938876B2 (en) | Manufacturing method of semiconductor device | |
JPH0282548A (en) | Inspection of semiconductor wafer | |
JP2004031946A (en) | Semiconductor device and its manufacturing method | |
JPH03206978A (en) | Test device for semiconductor device | |
JP2005072252A (en) | Semiconductor device and its manufacturing method | |
JPH0637157A (en) | Semiconductor wafer and inspecting method therefor |