JPH01205055A - Substrate material for semiconductor device - Google Patents
Substrate material for semiconductor deviceInfo
- Publication number
- JPH01205055A JPH01205055A JP63030202A JP3020288A JPH01205055A JP H01205055 A JPH01205055 A JP H01205055A JP 63030202 A JP63030202 A JP 63030202A JP 3020288 A JP3020288 A JP 3020288A JP H01205055 A JPH01205055 A JP H01205055A
- Authority
- JP
- Japan
- Prior art keywords
- substrate material
- semiconductor device
- weight
- thermal expansion
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 title claims abstract description 30
- 239000000463 material Substances 0.000 title claims abstract description 28
- 239000011521 glass Substances 0.000 claims abstract description 10
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 238000002844 melting Methods 0.000 claims abstract description 6
- 230000008018 melting Effects 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000002245 particle Substances 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 abstract description 16
- 239000000956 alloy Substances 0.000 abstract description 16
- 239000000843 powder Substances 0.000 abstract description 7
- 238000001816 cooling Methods 0.000 abstract description 3
- 238000005245 sintering Methods 0.000 abstract description 2
- 239000000155 melt Substances 0.000 abstract 3
- 238000000465 moulding Methods 0.000 abstract 3
- 229910002796 Si–Al Inorganic materials 0.000 abstract 1
- 238000000889 atomisation Methods 0.000 abstract 1
- 238000010298 pulverizing process Methods 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- 235000015842 Hesperis Nutrition 0.000 description 2
- 235000012633 Iberis amara Nutrition 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 238000009689 gas atomisation Methods 0.000 description 2
- 238000001192 hot extrusion Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005242 forging Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 231100000331 toxic Toxicity 0.000 description 1
- 230000002588 toxic effect Effects 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Powder Metallurgy (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、軽量で信頼性の高い半導体装置用基板材料に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lightweight and highly reliable substrate material for semiconductor devices.
従来から、半導体装置用の基板材料にはセラミックが多
用されている。例えば、サーデイツプ型パッケージにお
いては、セラミック基板上に半導体素子を塔載し、ガラ
スで気密封止する形態が採用されている。尚、パッケー
ジに関する技術は、例えば工業調査会発行「ＩＣ化実装
技術」（日本マイクロエレクトロニクス協会編）の１３
５〜１５０ 頁に詳しい。Conventionally, ceramics have been frequently used as substrate materials for semiconductor devices. For example, in a ceramic substrate type package, a semiconductor element is mounted on a ceramic substrate and hermetically sealed with glass. In addition, for the technology related to packaging, for example, 13 of ``IC Mounting Technology'' (edited by the Japan Microelectronics Association) published by the Industrial Research Council.
Details on pages 5-150.
しかしながら、最近の半導体技術に著しい進歩は、半導
体素子の大型化及び集積度の増加を招来しており、それ
に伴なって基板やパッケージ等の材料についても熱放散
性や熱膨張差の問題、あるいは重量の問題が生じてきて
いる。However, recent remarkable advances in semiconductor technology have led to larger and more integrated semiconductor devices, and along with this, materials for substrates, packages, etc. are also facing issues such as heat dissipation, thermal expansion differences, and Weight is becoming an issue.
即ち、セラミックは金属に比較して熱伝導度が小さいた
め熱放散性が悪いので、集積度が高く消費電力の大きな
半導体装置では、放熱フィンを取付ける等の対策を講じ
なければならないという不都合が生じている。熱伝導度
が良いセラミックとしてＢｅＯやＡＩＮがあるが、これ
らは密度が夫々２．６９シ糎及び３．２６−と大きく、
大型化する半導体装置の１惜が重くなる欠点があり、Ｂ
ｅＯは毒性が高く安全性の点でも問題があった。In other words, ceramics have a lower thermal conductivity than metals and therefore have poor heat dissipation properties, resulting in the inconvenience of having to take measures such as installing heat dissipation fins in semiconductor devices with a high degree of integration and high power consumption. ing. BeO and AIN are ceramics with good thermal conductivity, but these have high densities of 2.69 and 3.26, respectively.
B
eO is highly toxic and has safety issues.
更に、ＡＩＮ等のセラミックは薄板やキャヒティ程度の
加工は可能であるが、例えばタップ加工等により複雑な
形状とすることが困難で、パッケージ等としての形状に
制限があった。Further, although ceramics such as AIN can be processed into thin plates or cavities, it is difficult to form them into complex shapes by tapping, for example, and there are restrictions on the shapes that can be used as packages or the like.
このような問題を解決するため、珪素を３０〜５０重量
％含有するアルミニウム合金からなる基板ないしパッケ
ージが提案されている（特開昭６１−８７８４３号及び
特開昭６１−２８１５４１号参照）。In order to solve these problems, a substrate or package made of an aluminum alloy containing 30 to 50% by weight of silicon has been proposed (see Japanese Patent Laid-Open No. 61-87843 and Japanese Patent Laid-Open No. 61-281541).
この５ｉ−Ａ１合金の基板材料は、熱膨張係数及び熱伝
導度の点では大型化及び高集積化しつつある半導体装置
に適応しうるものであった。This 5i-A1 alloy substrate material was suitable for semiconductor devices that are becoming larger and more highly integrated in terms of thermal expansion coefficient and thermal conductivity.
〔発明が解決しようとする課題〕
しかしながら、最近では自動車のみならず航空機やロケ
ット、人工衛星等に塔載される半導体装置について軽量
化の要望が大きく、また信頼性についても一層の改善が
望まれている。このような用途ないし要望に対しては従
来のセラミックの基板材料では限界があり、上記した５
ｉ−Ａ／！合金からなる基板材料でも不充分であった。[Problem to be solved by the invention] However, recently there has been a strong demand for lighter weight semiconductor devices installed not only in automobiles but also in aircraft, rockets, artificial satellites, etc., and further improvements in reliability are desired. ing. Conventional ceramic substrate materials have limitations in meeting such uses and demands, and the above-mentioned 5
i-A/! Even substrate materials made of alloys were insufficient.
本発明はかかる従来の事情に鑑み、従来よりも更に軽量
化され、信頼性の高い半導体装置用基板を提供すること
を目的とする。SUMMARY OF THE INVENTION In view of the conventional circumstances, it is an object of the present invention to provide a substrate for a semiconductor device that is lighter than the conventional one and has high reliability.
本発明の半導体装置用基板材料は、５０重量％を超え８
０重量％までの珪素な含有するアルミニウム合金からな
り、その密度が２．３〜２．５ ｇ７４）／ｎ 。The semiconductor device substrate material of the present invention contains more than 50% by weight of 8
It consists of an aluminum alloy containing up to 0% by weight of silicon and its density is 2.3-2.5 g74)/n.
熱膨張係数が６Ｘ１０−６〜１２Ｘ１０−６６／℃、及
び熱伝導度が０．２０〜０．２７ ｃａｌ／ｓｅｃ、
Ｃであることを特徴とするものである。Thermal expansion coefficient is 6X10-6 to 12X10-66/℃, and the thermal conductivity is 0.20 to 0.27 cal/sec.
It is characterized by being C.
この基板材料は、ガスアトマイズ法等の噴霧法により溶
湯を平均冷却速度１０ Ｋ／ｓｅｃ以上で凝固させて
アルミニウムと珪素の合金粉末を形成し、４２メツシユ
以下のこの合金粉末を熱間での押出や鍛造などの塑性加
工する方法により、パッケージ等の所望の形状に固化成
形することができる。This substrate material is made by solidifying molten metal at an average cooling rate of 10 K/sec or more using a spraying method such as gas atomization to form an alloy powder of aluminum and silicon, and then hot extrusion or hot extrusion to form an alloy powder of 42 meshes or less. By a plastic working method such as forging, it can be solidified and formed into a desired shape such as a package.
特に、溶湯用るつぼ、アトマイズ用ノズル、アトマイズ
雰囲気の制御な検討することで、従来よりも高温で１−
３ｉ合金溶湯をアトマイズすることが可能となったので
、従来不可能であった５０〜８０重量％のＳｌを固溶さ
せることができるようになり一％熱彫張係数並びに熱伝
導度を半導体装置用として適当な値に保ちながら、−層
の軽量化を図れるようになったものである。In particular, by examining the control of the molten metal crucible, atomizing nozzle, and atomizing atmosphere, we are able to
Since it has become possible to atomize 3i alloy molten metal, it has become possible to dissolve 50 to 80% by weight of Sl, which was previously impossible. This makes it possible to reduce the weight of the - layer while keeping the value appropriate for the purpose.
尚、本発明における基板材料とは所謂半導体基板を構成
する材料のみではなく、各種形状のパッケージを構成す
る材料も含むものである。又、この基板材料の表面には
半田やガラスとの濡れ性を改善したり耐食性を付与した
り、絶縁性を確保する目的で、ＡｕやＮ１等の金属又は
Ａ４０ や５１０２等の絶縁物の表面層を形成するこ
とができる。しかも、この基板材料はｌｄがベースとな
っているのでガラス封止に充分な程度のＡｔ Ｏ表面層
が自然に且つ容易に形成される利点がある。Note that the term "substrate material" in the present invention includes not only a material constituting a so-called semiconductor substrate, but also a material constituting packages of various shapes. In addition, the surface of this substrate material is coated with a metal such as Au or N1 or an insulator such as A40 or 5102 in order to improve wettability with solder or glass, provide corrosion resistance, and ensure insulation. layers can be formed. Furthermore, since this substrate material is based on ld, it has the advantage that an At 2 O surface layer sufficient for glass sealing can be naturally and easily formed.
本発明においては、基板材料として５０重量％を超え８
０重量％までのＳｌを含むＡｌ−５ｉ合金を用いるので
、下表に示すように熱膨張係数並びに熱伝導度を半導体
装置用として適当な値に保ちながら、その密度を小さく
することができた。In the present invention, the substrate material contains more than 50% by weight of 8
By using an Al-5i alloy containing up to 0% by weight of Sl, we were able to reduce its density while keeping the thermal expansion coefficient and thermal conductivity at values appropriate for semiconductor devices, as shown in the table below. .
合 金 密 度 熱膨張係数 熱伝導度Ａ４−５０
Ｓｉ ２．５０ １）．２ ０．２７Ａ
ｌ−６０Ｓ１２．４３ ９．８ ０．２５
Ａ／ −７０Ｓｉ ２．４０ ８，７ ０
．２３Ａｌ−８０Ｓｉ ２．３８ ６．５
０．２０Ａｌ−９０Ｓｉ ２．３５ ４．５
０．１８Ｓｉ濃度が５０重量％以下では密度が高
くなる為充分な軽量化が図れず、また熱膨張係数も大さ
くなりパッケージとした場合にガラス封止が困難になる
。逆に８１濃度が８０重量％を超えると、ｓｌとＡｌの
界面での接合が不充分になって界面での熱抵抗が大きく
なるので、熱伝導度が小さくなり放熱性が低下する。更
に、硬度も高くなって被剛性が著しく低下し、加工性が
悪くなる。Alloy density Thermal expansion coefficient Thermal conductivity A4-50
Si 2.50 1). 2 0.27A
l-60S12.43 9.8 0.25
A/-70Si 2.40 8,7 0
．． 23Al-80Si 2.38 6.5
0.20Al-90Si 2.35 4.5
If the 0.18Si concentration is less than 50% by weight, the density will be high, making it impossible to achieve sufficient weight reduction, and the coefficient of thermal expansion will also increase, making it difficult to seal with glass when used as a package. On the other hand, when the 81 concentration exceeds 80% by weight, the bonding at the interface between sl and Al becomes insufficient and the thermal resistance at the interface increases, resulting in a decrease in thermal conductivity and a decrease in heat dissipation. Furthermore, the hardness increases, and the rigidity is significantly reduced, resulting in poor workability.
又同−８１濃度であっても、ｓ１初晶の粒径が太さいと
工具の摩耗が激しく、シかも複雑な形状の加工が困難で
寸法精度が低下するので、合金粉末生成時の冷却速度を
速くして、ｓ１初晶の粒径分５０μｍ以下とするのが好
ましい。例えば、同−Ｓ１濃度でＳ１初晶が５０μｍと
１５０１）ｍのＡｌ−３ｉ合金を、速度３５０ ｍ／ｍ
ｉｎ及び切込み０．１ ｍｆ％／ｒｅｖの条件で切削し
た場合のフランク摩耗量と切削時間との関係は第３図に
示す如くである。Even at the -81 concentration, if the grain size of the S1 primary crystals is large, tool wear will be severe, making it difficult to process complex shapes and reducing dimensional accuracy. It is preferable to increase the speed so that the grain size of the s1 primary crystal is 50 μm or less. For example, an Al-3i alloy with the same -S1 concentration and S1 primary crystals of 50 μm and 1501) m was heated at a speed of 350 m/m.
FIG. 3 shows the relationship between flank wear amount and cutting time when cutting is performed under conditions of in and depth of cut of 0.1 mf%/rev.
（実施例〕
実施例１
ガスアトマイズ法により溶湯を平均冷却速度２゜
１０ Ｋ／’８θＣ以上で凝固させ、６０重量％のｓｌ
を含有するＡｌ−５ｉ合金粉末を製造した。Ａｌ−８ｉ
合金中の初晶Ｓ１の粒径は５０μｍ以下であった。次に
、このＡｌ−８ｉ合金粉末を５００Ｃの温度及び５ ｔ
ｏｎＡＢ２の圧力で加圧焼結し、基板材料を製造した。(Example) Example 1 Molten metal was solidified by gas atomization at an average cooling rate of 2°10 K/'8θC or higher, and 60% by weight of sl
An Al-5i alloy powder containing the following was produced. Al-8i
The grain size of the primary crystal S1 in the alloy was 50 μm or less. Next, this Al-8i alloy powder was heated at a temperature of 500 C and 5 t.
Pressure sintering was performed at a pressure of onAB2 to produce a substrate material.
この基板材料の密度は２．４２ ｇ７ｔ）ｍ 、熱膨張
係数は９．５×１０４、及び熱伝導度は０．２５ ａａ
ｊ／ｓｅｃ、Ｃであった。The density of this substrate material is 2.42 g7t) m, the coefficient of thermal expansion is 9.5 × 104, and the thermal conductivity is 0.25 aa
j/sec, C.
この基板材料で製造したサーデイツプ型パッケージを用
いて、第１図に示す半導体装置を製造した。Ａｌ−３ｉ
合金からなるパッケージ主体部１の四部２にＡｕペース
ト３で半導体素子４を塔載しである。半導体素子４とリ
ードフレーム５はボンディングワイヤ６で接続され、熱
膨張係数が６Ｘ１０＝〜ｌ０ＸＩＯ−６／ｌ：の低融点
ガラス７により、リードフレーム５を固定すると同時に
同じＡｌ−３ｉ合金のキャップ８を気密に取付けである
。尚、パッケージ主体部１及びキャップ８の表面には、
アルマイト処理によって厚さ０．５μｍのＡ４０ 表
面層９が形成しである。A semiconductor device shown in FIG. 1 was manufactured using a deep dip package manufactured using this substrate material. Al-3i
A semiconductor element 4 is mounted on four parts 2 of a package main part 1 made of an alloy with Au paste 3. The semiconductor element 4 and the lead frame 5 are connected by a bonding wire 6, and the lead frame 5 is fixed by a low melting point glass 7 with a thermal expansion coefficient of 6X10=~l0XIO-6/l, and at the same time a cap 8 made of the same Al-3i alloy is attached. It is installed airtight. In addition, on the surfaces of the package main body 1 and the cap 8,
An A40 surface layer 9 having a thickness of 0.5 μm is formed by alumite treatment.
この半導体装置の重量は従来のセラミック製サーデイツ
プ型パッケージより約３０％はど軽量化できた。又、熱
抵抗は従来のセラミック製サーデイツプ型パッケージの
１７２以下と良好な熱放散性を達成でき、その結果消費
電力がＩＷ以上の半導体素子を搭載できることが確認で
きた。気密封止性については、Ｈｅリークテストの結果
５Ｘ１０ ｃｃ／ＳｅＱ、以上の気密性が得られた。The weight of this semiconductor device is approximately 30% lighter than that of conventional ceramic ceramic dip-type packages. In addition, it was confirmed that the thermal resistance was 172 or less than that of the conventional ceramic cer-dip type package, achieving good heat dissipation, and as a result, it was possible to mount a semiconductor element with power consumption greater than IW. Regarding hermetic sealability, as a result of a He leak test, an airtightness of 5×10 cc/SeQ or more was obtained.
更に、この半導体装置ｆ −６５Ｃｇ＋ １５Ｏｒの温
度変化を３５サイクル繰返す温度サイクルテスト後、Ｈ
ｅリークテストを行なったところ９ Ｘ １Ｏ−９ｃｃ
／ｓｅｃ、の値が得られ、充分な信頼性を得ることがで
さた。Furthermore, after a temperature cycle test in which the temperature change of this semiconductor device f-65Cg+15Or was repeated for 35 cycles, H
When I did the e-leak test, it was 9 x 1O-9cc.
/sec, and it was possible to obtain sufficient reliability.
実施例２
実施例１と同様にして製造した基板材料から、第２図に
示す箱状のケース１０とフタ１）からなるパッケージを
製造した。Example 2 A package consisting of a box-shaped case 10 and a lid 1) shown in FIG. 2 was manufactured from a substrate material manufactured in the same manner as in Example 1.
ケースの所定位置にリード線１２を低融点ガラス１３で
封止固定した後、厚さ２μｍのＡｕメツキをケース１０
とフタ１）の全表面に施した０次に、ケース１０内に所
定の回路を形成し、半導体素子を塔載した後、ケース１
０とフタ１）をＡｕ−８ｉ共晶半田１４で接合封止した
。After sealing and fixing the lead wire 12 in a predetermined position of the case with low melting point glass 13, a 2 μm thick Au plating is attached to the case 10.
After forming a predetermined circuit in the case 10 and mounting a semiconductor element on the entire surface of the lid 1), the case 1
0 and the lid 1) were bonded and sealed with Au-8i eutectic solder 14.
第２図に示すパッケージは航空機用レーダーに使用され
るもので、従来このパッケージはコバールやステンレス
で作られ重量が重いことが欠点とされていた。然るに、
本発明のＡｌ−３ｉ合金のパッケージを用いることによ
り、従来のものに比較して重量を約半分にすることがで
きた。The package shown in Figure 2 is used for aircraft radar, and conventionally this package was made of Kovar or stainless steel and had a drawback of being heavy. However,
By using the Al-3i alloy package of the present invention, it was possible to reduce the weight by about half compared to the conventional package.
本発明によれば、従来よりも更に軽量化され、信頼性の
高い半導体装置用基板材料を提供することができる。従
って、本発明は航空機やロケット、人工衛星等の分野に
使用される半導体装置に特に有用である。According to the present invention, it is possible to provide a substrate material for a semiconductor device that is lighter in weight than conventional materials and has high reliability. Therefore, the present invention is particularly useful for semiconductor devices used in fields such as aircraft, rockets, and artificial satellites.
第１図及び第２図は夫々本発明の基板材料を用いた半導
体装置の具体例である。第３図は本発明の基板材料中の
８１初晶の粒径と、これを切削する工具のフランク摩耗
量との関係を示すグラフである。
１・・パッケージ主体部 ４・・半導体素子５・・リー
ドフレーム ７・・低融点ガラス８・・キャップ ９・
・Ｉ Ｏ表面層
１０・・ケース １）・・フタ １２・・リード線１３
・・低融点ガラス １４・・Ａｕ−３ｉ共晶半田出願人
住友電気工業株式会社
代理人 弁理土中打勝□′成１）．パ
）り世〜し
第１図
第２図
切削時間（ｒｎｉｎ）1 and 2 are specific examples of semiconductor devices using the substrate material of the present invention, respectively. FIG. 3 is a graph showing the relationship between the grain size of 81 primary crystals in the substrate material of the present invention and the amount of flank wear of the tool for cutting them. 1. Main body of package 4. Semiconductor element 5. Lead frame 7. Low melting point glass 8. Cap 9.
・IO surface layer 10...Case 1)...Lid 12...Lead wire 13
...Low melting point glass 14...Au-3i eutectic solder Applicant Sumitomo Electric Industries Co., Ltd. Attorney Uchikatsu Dochu□'Nari 1). Figure 1 Figure 2 Cutting time (rnin)
Claims (3)
るアルミニウム合金からなり、密度が２．３〜２．５ｇ
／ｃｍ＾３、熱膨張係数が６×１０＾−＾６〜１２×１
０＾−＾６／℃、及び熱伝導度が０．２０〜０．２７ｃ
ａｌ／ｓｅｃ．℃であることを特徴とする半導体装置用
基板材料。(1) Made of aluminum alloy containing more than 50% by weight and up to 80% by weight, and has a density of 2.3 to 2.5g.
/cm^3, thermal expansion coefficient is 6 x 10^-^6 ~ 12 x 1
0^-^6/℃ and thermal conductivity 0.20~0.27c
al/sec. A substrate material for semiconductor devices characterized by a temperature of ℃.
る請求項（１）記載の半導体装置用基板材料。(2) The substrate material for a semiconductor device according to claim (1), wherein the particle size of the primary silicon crystals contained is 50 μm or less.
＾６／℃の低融点ガラスで形成したリード線又はリード
フレームの封止部を具える請求項（１）記載の半導体装
置用基板材料。(3) Thermal expansion coefficient is 6 x 10^-^6 ~ 10 x 10^-
The substrate material for a semiconductor device according to claim 1, further comprising a lead wire or lead frame sealing portion made of low melting point glass of ^6/°C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63030202A JPH01205055A (en) | 1988-02-12 | 1988-02-12 | Substrate material for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63030202A JPH01205055A (en) | 1988-02-12 | 1988-02-12 | Substrate material for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01205055A true JPH01205055A (en) | 1989-08-17 |
Family
ID=12297155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63030202A Pending JPH01205055A (en) | 1988-02-12 | 1988-02-12 | Substrate material for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01205055A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0500750A1 (en) * | 1989-11-15 | 1992-09-02 | Olin Corp | A method for housing a tape-bonded electronic device and the package employed. |
| JPH08502554A (en) * | 1992-11-18 | 1996-03-19 | エルケム・アクシエセルスカプ | "Method for producing silicon alloy, silicon alloy and method for producing consolidated product from silicon alloy" |
| EP0713250A2 (en) | 1994-11-15 | 1996-05-22 | Sumitomo Electric Industries, Ltd. | Material for semiconductor substrate, process for producing the same, and semiconductor device with such substrate |
| EP1727215A3 (en) * | 2005-05-23 | 2010-10-06 | Samsung LED Co., Ltd. | Vertical structure semiconductor light emitting device and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6187843A (en) * | 1984-10-03 | 1986-05-06 | Sumitomo Electric Ind Ltd | Material for substrate for semiconductor device and its manufacture |
| JPS61130438A (en) * | 1984-11-29 | 1986-06-18 | Sumitomo Electric Ind Ltd | Manufacture of material for semiconductor device |
| JPS61281541A (en) * | 1985-06-06 | 1986-12-11 | Sumitomo Electric Ind Ltd | Package for semiconductor device |
-
1988
- 1988-02-12 JP JP63030202A patent/JPH01205055A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6187843A (en) * | 1984-10-03 | 1986-05-06 | Sumitomo Electric Ind Ltd | Material for substrate for semiconductor device and its manufacture |
| JPS61130438A (en) * | 1984-11-29 | 1986-06-18 | Sumitomo Electric Ind Ltd | Manufacture of material for semiconductor device |
| JPS61281541A (en) * | 1985-06-06 | 1986-12-11 | Sumitomo Electric Ind Ltd | Package for semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0500750A1 (en) * | 1989-11-15 | 1992-09-02 | Olin Corp | A method for housing a tape-bonded electronic device and the package employed. |
| JPH08502554A (en) * | 1992-11-18 | 1996-03-19 | エルケム・アクシエセルスカプ | "Method for producing silicon alloy, silicon alloy and method for producing consolidated product from silicon alloy" |
| EP0713250A2 (en) | 1994-11-15 | 1996-05-22 | Sumitomo Electric Industries, Ltd. | Material for semiconductor substrate, process for producing the same, and semiconductor device with such substrate |
| EP0713250A3 (en) * | 1994-11-15 | 1997-05-14 | Sumitomo Electric Industries | Material for semiconductor substrate, process for producing the same, and semiconductor device with such substrate |
| US5828127A (en) * | 1994-11-15 | 1998-10-27 | Sumitomo Electric Industries, Ltd. | Semiconductor substate with improved thermal conductivity |
| EP1727215A3 (en) * | 2005-05-23 | 2010-10-06 | Samsung LED Co., Ltd. | Vertical structure semiconductor light emitting device and method for manufacturing the same |
| EP2439798A1 (en) * | 2005-05-23 | 2012-04-11 | Samsung LED Co., Ltd. | Vertical structure semiconductor light emitting device and method for manufacturing the same |
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