JPH01191491A - Multiple circuit board - Google Patents
Multiple circuit boardInfo
- Publication number
- JPH01191491A JPH01191491A JP1606888A JP1606888A JPH01191491A JP H01191491 A JPH01191491 A JP H01191491A JP 1606888 A JP1606888 A JP 1606888A JP 1606888 A JP1606888 A JP 1606888A JP H01191491 A JPH01191491 A JP H01191491A
- Authority
- JP
- Japan
- Prior art keywords
- mounting board
- mounting
- conductor
- type electronic
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 abstract description 22
- 229910000679 solder Inorganic materials 0.000 abstract description 20
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 229910052709 silver Inorganic materials 0.000 abstract description 3
- 239000004332 silver Substances 0.000 abstract description 3
- 229910052797 bismuth Inorganic materials 0.000 abstract description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005485 electric heating Methods 0.000 abstract description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 7
- 239000011521 glass Substances 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- -1 etc. can be applied Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000012254 powdered material Substances 0.000 description 1
- 238000003303 reheating Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子機器に用いる回路基板に関し、とりわけ
、複数の回路板の積み重ね構造に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a circuit board used in electronic equipment, and more particularly to a stacked structure of a plurality of circuit boards.
従来の技術
従来、複数の回路板としては、まず第1に部品が上下の
表層のみに配置されている場合には、スルーホールめっ
き接続を有する多層配線板が、ガラス布基材エポキシ樹
脂積層材料を用いて製造されていた。また、セラミック
質の多層配線板も、スルーホール接続を備えて一部製造
されている。Conventional technology Conventionally, multilayer wiring boards with through-hole plating connections are made of glass cloth-based epoxy resin laminated materials when components are arranged only on the upper and lower surface layers. It was manufactured using. Additionally, some ceramic multilayer wiring boards are also manufactured with through-hole connections.
次に、第2の方法として、部品が回路板の間隙に存在す
る場合について回路基板の四隅に貫通孔を加工し、四本
柱を通す構造物が容易に考えられる。また、第3の方法
として、セラミック基板の端部にノツチと称する、半月
状の欠は部を多数設け、その壁面をメタライズして、リ
ード線等をはんだ付けして、連接し、ある間隔に配置し
た回路板とした構成で、かつてマイクロモジュールと呼
ばれていたものがある。Next, as a second method, when a component is present in a gap between circuit boards, it is easy to imagine a structure in which through holes are formed at the four corners of the circuit board and four pillars are passed through. In addition, as a third method, a large number of half-moon-shaped notches called notches are provided at the end of the ceramic substrate, the walls of which are metalized, and lead wires etc. are soldered and connected to each other at certain intervals. There is a structure that consists of arranged circuit boards, and was once called a micromodule.
発明が解決しようとする課“題
複数の回路板を重層に構成する目的は、回路部品の実装
密度を高め、高い信頼性を保つことにある。第1の多層
配線板では、表層、すなわち上・下層以外に部品を配置
することは、不可能もしくは困難である。しかも高価で
ある。第2の四本柱をたててつなぐ構造物は、機械的接
続だけであって、電気的結線は別にリード線或はコネク
ターを使っておこなわなければならない。第3のマイク
ロモジュール構成は、多数のリードまたは端子のはんだ
付けがおこないに<<、量産的手法でなく、従って、製
造コストの高い欠点があった。また、リードの曲りがあ
りリードの形状保持性も良(ない欠点もある。Problems to be Solved by the Invention The purpose of configuring multiple circuit boards in layers is to increase the mounting density of circuit components and maintain high reliability.In the first multilayer wiring board, the surface layer, that is, the upper・It is impossible or difficult to place components other than on the lower layer, and it is also expensive.The structure that connects the second four pillars is only a mechanical connection, and the electrical connection is made using separate leads. This has to be done using wires or connectors.The third micromodule configuration has the drawback of requiring soldering of a large number of leads or terminals, is not a mass-produced method, and is therefore expensive to manufacture. .Also, there is a drawback that the lead is bent and the shape retention of the lead is not good.
課題を解決するための手段
本発明は、−枚の基板面へのチップ型電子部品の搭載を
他の上面実装部品搭載と同時に行ない、底部の第1実装
基板とし、それらの搭載後、別の上面実装基板を第2実
装基板として重ねて搭載し、この二重構造に対して、−
挙に、はんだリフロウ用の加熱をトップ及びボトムの両
面から適用できるものである。その際、第2実装基板の
下面すなわち、前記チップ型電子部品の電極当接部分に
対しては、第1及び第2実装基板に印刷、またはディス
ペンスするのと同じはんだペーストをあらかじめ印刷し
ておく。Means for Solving the Problems In the present invention, chip-type electronic components are mounted on one board surface at the same time as other top-mounted components are mounted on the bottom first mounting board, and after mounting them, another The top mounting board is stacked as the second mounting board, and for this double structure, -
Moreover, heating for solder reflow can be applied from both the top and bottom sides. At that time, the same solder paste that is printed or dispensed on the first and second mounting boards is printed in advance on the lower surface of the second mounting board, that is, on the electrode contact part of the chip type electronic component. .
作用
本発明による構成では、第1基板面、第2基板面及びチ
ップ型電子部品の電極面に、同じ融点のはんだペースト
を用いることができ、更にはんだ付けを多層でおこなう
ことができる。Function: With the configuration according to the present invention, solder pastes having the same melting point can be used on the first substrate surface, the second substrate surface, and the electrode surface of the chip type electronic component, and furthermore, soldering can be performed in multiple layers.
何故なら、はんだ付けによるはんだ付け部のゆるみは回
避され、はんだ付けの信頼性を高度に維持できる。また
、はんだ付け炉の通過回路を1回とするので、基板及び
装着部品に対する125℃をこえた熱ショックを与える
頻度を最小に留めることができる。基板材質としては、
セラミック。This is because loosening of the soldered portion due to soldering is avoided, and a high degree of reliability of soldering can be maintained. Furthermore, since the soldering furnace passes through the circuit only once, it is possible to minimize the frequency of applying thermal shocks exceeding 125° C. to the board and mounted components. As for the substrate material,
ceramic.
ガラスを始め、ガラスエポキシ、紙エポキシ、紙フエノ
ール、紙ボリエステルアーラミドエポキン、ガラスポリ
イミド等のリジッド型のプリント配線板用積層枚などが
適用でき、銀、銅、金などの箔または粉末状導体をそれ
らの基板面に形成して用いることができる。これらの材
料は、200〜300℃のはんだ付け作業温度に対する
耐熱性と、はんだ付けの可能な良い濡れ性をそなえたも
のとして市場に存在する。Rigid printed wiring board laminates made of glass, glass epoxy, paper epoxy, paper phenol, paper polyester aramid epoxy, glass polyimide, etc. can be applied, as well as foil or powdered materials such as silver, copper, and gold. Conductors can be formed on the surfaces of these substrates. These materials exist on the market as having heat resistance to soldering temperatures of 200 to 300° C. and good wettability to enable soldering.
実施例
第1図に本発明の実施例を示す。1は第1実装基板、2
は第2実装基板介在させる導体チップ3を第1実装基板
1に他の表面実装部品、いわゆるチップ型電子部品8と
共に導体4とはんだ5に合致させて載置する。別に用意
した第2実装基板2の導体面9に印刷したはんだ9に導
体チップ3の上面を対応して当接する。この導体チップ
3の高さHにより、第1実装基板1と第2実装基板2と
の実装間隙Jがきまる。例えば、第1実装基板1に高さ
1.25mmの磁器コンデンサチップを実装した状態で
導体チップの高さHを1.50mmに設定して、0.2
5mmのギャップを第1実装基板1と第2実装基板2と
の物理的間隙として得る。第1実装基板1と第2実装基
板2との間隙はほぼ導体チップ3の高さ(1,50mm
)と、導体8及び導体4の厚さ(15μm×2)、それ
に、はんだ5及び同9の厚さ(15μm×2)として、
約1.56間となる。基板厚さを1.0mmとすれば、
基板配置中心間隙は2.56m++++となる。はんだ
は用例の多い錫−鉛(重量比率63−37)のものでよ
いが、時としてビスマス入りの低温はんだ、銀入り l
ははんだも用いられる。加熱源は上下のいずれか一方は
好ましくな(、上下同時加熱のものが温度分布性がよい
。熱源の種類は、赤外、直赤外、電熱のいずれでもよい
が、例えば215℃±5℃15±1秒のはんだ付け実行
条件の制御可能な搬送装置としであることが望ましい。Embodiment FIG. 1 shows an embodiment of the present invention. 1 is the first mounting board, 2
The conductor chip 3 interposed on the second mounting board is placed on the first mounting board 1 together with other surface-mounted components, so-called chip-type electronic components 8, in alignment with the conductor 4 and the solder 5. The upper surface of the conductor chip 3 is brought into contact with the solder 9 printed on the conductor surface 9 of the second mounting board 2 prepared separately. The height H of the conductor chip 3 determines the mounting gap J between the first mounting board 1 and the second mounting board 2. For example, if a ceramic capacitor chip with a height of 1.25 mm is mounted on the first mounting board 1, and the height H of the conductor chip is set to 1.50 mm,
A gap of 5 mm is obtained as a physical gap between the first mounting board 1 and the second mounting board 2. The gap between the first mounting board 1 and the second mounting board 2 is approximately the height of the conductor chip 3 (1.50 mm).
), the thickness of conductor 8 and conductor 4 (15 μm x 2), and the thickness of solder 5 and solder 9 (15 μm x 2),
It will be about 1.56 minutes. If the substrate thickness is 1.0mm,
The center gap between the substrates is 2.56 m++++. The solder may be tin-lead (weight ratio 63-37), which is often used, but sometimes low-temperature solder containing bismuth, solder containing silver, etc.
Solder is also used. As for the heating source, it is preferable to use either the upper or lower heating source (the one that heats the upper and lower simultaneously has good temperature distribution.The type of heat source may be infrared, direct infrared, or electric heating, but for example, 215°C ± 5°C). It is desirable to use a conveying device that can control soldering execution conditions of 15±1 seconds.
発明の効果
本発明により、第1に実装基板の多重化を、リード線、
端子を使用することなく、おこなえるので、位置不整、
端子コストの増大を招かない、第2に導体チップは、回
路面の小面積に随所に配置でき、端部に限定される必要
はない、従って第1及び第2実装基板での配線の引きま
わしを短縮できる。第3に接続は、多くの表面実装と同
時に行ない得るので、工程数を増加させず、はんだ付け
再加熱による、はんだのゆるみ、部品の熱的捉信を招か
ない。Effects of the Invention According to the present invention, firstly, multiplexing of mounting boards can be achieved by using lead wires,
This can be done without using terminals, so there is no need to worry about irregular positions or
Second, the conductor chip can be placed anywhere in a small area of the circuit surface, and does not need to be limited to the edges. Therefore, it is easy to route the wiring on the first and second mounting boards. can be shortened. Third, since the connection can be performed simultaneously with many surface mounting operations, the number of steps is not increased, and reheating during soldering does not cause loosening of the solder or thermal trapping of the components.
よって、高濃度実装を低いコストで、信頼性高〈実施す
ることができる。Therefore, high-density packaging can be carried out at low cost and with high reliability.
第1図、第2図は本発明実施例の組立以前、組立後の状
態を示す各断面図である。
1・・・・・・第1実装基I板、2・・・・・・第2実
装基板、3・・・・・・導体チップ、4・・・・・・第
1基板の導体、5・・・・・・4に印刷したはんだ、6
・・・・・・第2基板の導体、7・・・・・・6に印刷
したはんだ、8・・・・・・第1実装基板に実装する表
面装着部品、9・・・・・・8に形成した電極、10・
・・・・・第2実装基板に実装する表面装着部品。
代理人の氏名 弁理士 中尾敏男 ほか1名/−−−;
1− / 実技基板
2−汁2実長基板
3−導体チップ
4− 才1基扶の導体
S−4に〔n刷した1よんだ
6−第2基扶の導体
H−−一厚体チツブの島さ
J−一一実表基枝の配置間隙
第2図FIGS. 1 and 2 are sectional views showing the state before and after assembly of the embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... First mounting board I board, 2... Second mounting board, 3... Conductor chip, 4... Conductor of first board, 5・・・・・・Solder printed on 4, 6
...Conductor of second board, 7...Solder printed on 6, 8...Surface mounting component to be mounted on first mounting board, 9... The electrode formed at 8, 10.
...Surface mounting component mounted on the second mounting board. Name of agent: Patent attorney Toshio Nakao and 1 other person/---;
1-/Practical board 2-Last board 2-Full-length board 3-Conductor chip 4-1 printed on conductor S-4 of 1 base 6-2nd base conductor H--1 thick chip NoshimasaJ-11 Diagram 2 of the arrangement gap of the basal branch of the fruit table
Claims (1)
有し、同電極にチップ型電子部品の各電極を固着接続す
るとともに、前記チップ型電子部品を介して複数の回路
基板を重ねて一体とした多重回路板。The insulating rectangular parallelepiped has a printed electrode dedicated to soldering, and each electrode of a chip-type electronic component is firmly connected to the electrode, and multiple circuit boards are stacked and integrated via the chip-type electronic component. multiplexed circuit board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1606888A JPH01191491A (en) | 1988-01-27 | 1988-01-27 | Multiple circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1606888A JPH01191491A (en) | 1988-01-27 | 1988-01-27 | Multiple circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01191491A true JPH01191491A (en) | 1989-08-01 |
Family
ID=11906253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1606888A Pending JPH01191491A (en) | 1988-01-27 | 1988-01-27 | Multiple circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01191491A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0996323A2 (en) * | 1998-10-07 | 2000-04-26 | TDK Corporation | Surface mounting part |
KR100370330B1 (en) * | 1998-06-04 | 2003-01-29 | 가부시키가이샤 히타치세이사쿠쇼 | A method of manufacturing the electronic circuit board and an apparatus of manufacturing the same |
WO2005072033A1 (en) * | 2004-01-27 | 2005-08-04 | Matsushita Electric Industrial Co., Ltd. | Circuit board and method for mounting chip component |
-
1988
- 1988-01-27 JP JP1606888A patent/JPH01191491A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100370330B1 (en) * | 1998-06-04 | 2003-01-29 | 가부시키가이샤 히타치세이사쿠쇼 | A method of manufacturing the electronic circuit board and an apparatus of manufacturing the same |
EP0996323A2 (en) * | 1998-10-07 | 2000-04-26 | TDK Corporation | Surface mounting part |
EP0996323A3 (en) * | 1998-10-07 | 2000-05-03 | TDK Corporation | Surface mounting part |
US6373714B1 (en) | 1998-10-07 | 2002-04-16 | Tdk Corporation | Surface mounting part |
WO2005072033A1 (en) * | 2004-01-27 | 2005-08-04 | Matsushita Electric Industrial Co., Ltd. | Circuit board and method for mounting chip component |
US7667299B2 (en) | 2004-01-27 | 2010-02-23 | Panasonic Corporation | Circuit board and method for mounting chip component |
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