JPH01189145A - Manufacture of semiconductor substrate - Google Patents
Manufacture of semiconductor substrateInfo
- Publication number
- JPH01189145A JPH01189145A JP1433688A JP1433688A JPH01189145A JP H01189145 A JPH01189145 A JP H01189145A JP 1433688 A JP1433688 A JP 1433688A JP 1433688 A JP1433688 A JP 1433688A JP H01189145 A JPH01189145 A JP H01189145A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- semiconductor
- film
- insulating film
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 20
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 229910052796 boron Inorganic materials 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 239000010408 film Substances 0.000 description 48
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- JQXXHWHPUNPDRT-WLSIYKJHSA-N rifampicin Chemical compound O([C@](C1=O)(C)O/C=C/[C@@H]([C@H]([C@@H](OC(C)=O)[C@H](C)[C@H](O)[C@H](C)[C@@H](O)[C@@H](C)\C=C\C=C(C)/C(=O)NC=2C(O)=C3C([O-])=C4C)C)OC)C4=C1C3=C(O)C=2\C=N\N1CC[NH+](C)CC1 JQXXHWHPUNPDRT-WLSIYKJHSA-N 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】 以下の順序に従って本発明を説明する。[Detailed description of the invention] The present invention will be described in the following order.
Ａ、産業上の利用分野
Ｂ０発明の概要
Ｃ０従来技術［第２図］
Ｄ０発明が解決しようとする問題点
Ｅ０問題点を解決するための手段
Ｆ８作用
Ｇ、実施例［第１図］
Ｈ０発明の効果
（Ａ、産業上の利用分野）
本発明は半導体基板の製造方法、特に表面に絶縁膜を形
成した２枚の半導体基板を貼り合わせて１つの半導体基
板を得る半導体基板の製造方法に関する。A. Industrial field of application B0 Overview of the invention C0 Prior art [Fig. 2] D0 Problem to be solved by the invention E0 Means for solving the problem F8 Effect G. Examples [Fig. 1] H0 Invention Effects (A. Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor substrate, and particularly to a method for manufacturing a semiconductor substrate in which one semiconductor substrate is obtained by bonding two semiconductor substrates each having an insulating film formed on the surface thereof.
（Ｂ、発明の概要）
本発明は、上記の半導体基板の製造方法において、
低い温度で強固に半導体基板を貼り合わせることができ
るようにするため、
少くとも一方の半導体基板の表面の絶縁膜に非金属不純
物を含有させておくものである。(B. Summary of the Invention) In the method for manufacturing a semiconductor substrate described above, the present invention provides the following method: in order to be able to firmly bond the semiconductor substrates together at a low temperature, an insulating film on the surface of at least one semiconductor substrate is coated with the insulating film. It contains non-metallic impurities.
（Ｃ，従来技術）［第２図］
ＳＯＩ基板表面の半導体層にＭＩＳトラジスタ等の素子
を形成するＳｏｌ技術は電気的特性の優れた回路を形成
することができる等の種々の利点を有しており、最近Ｓ
ｏｌ技術の開発、研究が盛んに行われている。ところで
、ＳＯＩ基板は、シリコン半導体基板の形成に絶縁膜を
部分的に形成し、半導体基板の表面に窓（露出部）を種
として半導体層をエピタキシャル成長させるという方法
で製造することができる。しかし、このような製造方法
では良好で均質なｒｐ−結晶半導体層を形成することが
難しく、実用性が低いという問題があった。(C, Prior Art) [Figure 2] Sol technology, which forms elements such as MIS transistors in the semiconductor layer on the surface of an SOI substrate, has various advantages such as being able to form circuits with excellent electrical characteristics. Recently, S
The development and research of ol technology is actively being carried out. Incidentally, an SOI substrate can be manufactured by a method in which an insulating film is partially formed in the formation of a silicon semiconductor substrate, and a semiconductor layer is epitaxially grown on the surface of the semiconductor substrate using a window (exposed portion) as a seed. However, such a manufacturing method has a problem in that it is difficult to form a good and homogeneous RP-crystalline semiconductor layer, and the practicality of the method is low.
そこで、最近有望視されてきたのが２枚の半導体ウェハ
を貼り合わせるＳＯＩ基板の製造方法である。勿論、チ
ップどうしを貼り合わせる半導体基板の製造方法は特公
昭４１−８１７３号公報、特公昭３９−１７８６９号公
報によって紹介されているように古くから知られている
が、２枚の半導体基板を製造する技術は比較的最近開発
された技術である。第２図（Ａ）乃至（Ｃ）はかかるＳ
ｏｌ基板の製造方法の従来例を工程順に示すものである
。この製造方法は同図（Ａ）に示すように表面に絶縁Ｈ
９，ｂを形成した２枚の半導体基板ａ、ｃを用意し、同
図（Ｂ）に示すようにその２枚の゛ｈ導体基板ａ、ｃど
うしを絶縁膜す、ｂにて熱圧着して貼り合わせ、その後
、同図（Ｃ）に示すように一方の半導体基板例えばａを
裏面から研磨し、その半導体基板が薄い半導体層ａ′と
して残存するようにするものである。ａ″は研磨により
除去された部分である。Therefore, a method of manufacturing an SOI substrate in which two semiconductor wafers are bonded together has recently been viewed as promising. Of course, the manufacturing method of semiconductor substrates by bonding chips together has been known for a long time as introduced in Japanese Patent Publication No. 41-8173 and Japanese Patent Publication No. 39-17869. This is a relatively recently developed technology. Figures 2 (A) to (C) show such S
A conventional example of a method for manufacturing an OL substrate is shown in order of steps. This manufacturing method is as shown in the same figure (A).
Two semiconductor substrates a and c on which 9 and b are formed are prepared, and as shown in the same figure (B), the two conductor substrates a and c are bonded together by thermocompression with insulating films 9 and b. Then, as shown in FIG. 2C, one semiconductor substrate, for example, a, is polished from the back side so that the semiconductor substrate remains as a thin semiconductor layer a'. a'' is a portion removed by polishing.
このような方法によれば、５ｉｎ２からなる絶縁膜ｂ、
ｂの表面に存在するＯＨ基によって５ｉｎ２が水素結合
し、絶縁膜す、ｂどうしが密着し、２枚のウェハ状半導
体基板ａ、ｃを１枚のウェハ状Ｓｏｌ基板にすることが
できる。According to such a method, the insulating film b consisting of 5in2,
5in2 is hydrogen bonded by the OH group present on the surface of b, the insulating films S and B are brought into close contact with each other, and the two wafer-shaped semiconductor substrates a and c can be made into one wafer-shaped Sol substrate.
（Ｄ、発明が解決しようとする問題点）ところで、絶縁
膜す、ｂは５ｉｎ２からなり融点が高いので、貼り合わ
せのための加熱温度を相当に高くしなければ強固に半導
体基板ａ、ｃどうしを固着することができない。(D. Problem to be solved by the invention) By the way, the insulating films A and B are made of 5in2 and have a high melting point, so unless the heating temperature for bonding is considerably high, the semiconductor substrates A and C cannot be firmly connected to each other. cannot be fixed.
そこで、本発明は比較的低い温度で加熱処理しても２枚
の半導体基板を強固に貼り合わせることかできるように
することを目的とする。Therefore, an object of the present invention is to enable two semiconductor substrates to be firmly bonded together even when heat-treated at a relatively low temperature.
（Ｅ、問題点を解決するための手段）
本発明半導体基板の製造方法は上記問題点を解決するた
め、
貼り合される２枚の半導体基板の少なくとも一方の半導
体基板の絶縁膜に非金属不純物を含有させておくことを
特徴とする。(E. Means for Solving the Problems) In order to solve the above-mentioned problems, the method for manufacturing a semiconductor substrate of the present invention includes the step of adding non-metallic impurities to the insulating film of at least one of the two semiconductor substrates to be bonded together. It is characterized by containing.
（Ｆ、作用）
本発明半導体基板の製造方法によれば、一方の半導体基
板の絶縁膜に非金属不純物が含有されているので、その
絶縁膜の融点が低くなる。従って、低い温度で加熱して
も半導体基板どうしを固着することができる。しかも、
非金属不純物は加熱処理の際に拡散して２つの絶縁膜の
境界部での界面結合の介在物として働くので、２つの絶
縁膜を強固に固着することができる。(F. Effect) According to the method for manufacturing a semiconductor substrate of the present invention, since the insulating film of one semiconductor substrate contains a nonmetallic impurity, the melting point of the insulating film is lowered. Therefore, the semiconductor substrates can be fixed to each other even when heated at a low temperature. Moreover,
The nonmetallic impurities diffuse during the heat treatment and act as inclusions for interfacial bonding at the boundary between the two insulating films, so that the two insulating films can be firmly bonded.
（Ｇ、実施例）［第１図］
以下、本発明半導体基板の製造方法を図示実施例に従っ
て詳細に説明する。(G, Example) [FIG. 1] Hereinafter, the method for manufacturing a semiconductor substrate of the present invention will be described in detail according to the illustrated example.
第１図（Ａ）乃至（Ｃ）は本発明半導体基板の製造方法
の一つの実施例を工程順に示す断面図である。FIGS. 1A to 1C are cross-sectional views showing one embodiment of the method for manufacturing a semiconductor substrate of the present invention in the order of steps.
先ず、第１図（Ａ）に示すように表面に絶縁膜が形成さ
れた２枚のウェハ状の半導体基板１．２を′用意する。First, as shown in FIG. 1A, two wafer-shaped semiconductor substrates 1.2 having insulating films formed on their surfaces are prepared.
一方の半導体基板１の表面には例えばホウ素Ｂ及びリン
Ｐがドープされたシリコン酸化膜であるＢＰＳＧ膜３が
形成されており、他方の゛ト導体基板２の表面には熱酸
化によりノンドープシリコン酸化膜４が形成されている
。A BPSG film 3, which is a silicon oxide film doped with, for example, boron B and phosphorus P, is formed on the surface of one semiconductor substrate 1, and a non-doped silicon oxide film 3 is formed on the surface of the other conductor substrate 2 by thermal oxidation. A film 4 is formed.
次に、同図（Ｂ）に示すように半導体基板２の表面に半
導体基板１を表面を下向きにして貼り合わせ、そして、
半導体基板ＩＭしにＣＯ２レーザからのレーザビームを
シリコン酸化膜３．４に照射する。すると、比較的低い
温度でＢＰＳＧＩＩＱ３の表面にリフローが生しシリコ
ン酸化１摸４と接着し易くなる。そして、ＢＰＳＧ膜３
中のホウ素ＢあるいはリンＰがシリコン酸化膜４中に拡
散し、ＢＰＳＧ膜３とシリコン酸化膜４の境界部での界
面結合の介在物として働き、同図（Ｃ）に示すようにＢ
ＰＳＧ膜３とシリコン酸化ｒＩＦＡ４とが一体のシリコ
ン酸化膜５となる。その結果、低い加熱温度で強固に半
導体基板１と２を貼り合わせることができる。Next, as shown in the same figure (B), the semiconductor substrate 1 is bonded to the surface of the semiconductor substrate 2 with the surface facing downward, and
The silicon oxide film 3.4 is irradiated with a laser beam from a CO2 laser while the semiconductor substrate IM is being processed. Then, reflow occurs on the surface of BPSGIIQ3 at a relatively low temperature, making it easier to adhere to silicon oxide 1 and 4. And BPSG film 3
The boron B or phosphorus P inside diffuses into the silicon oxide film 4 and acts as an inclusion for interfacial bonding at the boundary between the BPSG film 3 and the silicon oxide film 4, and as shown in FIG.
The PSG film 3 and silicon oxide rIFA 4 form an integrated silicon oxide film 5. As a result, the semiconductor substrates 1 and 2 can be firmly bonded together at a low heating temperature.
その後は図示しないが、−・方の半導体基板例えば半導
体基板１をその裏面側から研磨し半導体基板ｌがシリコ
ン酸化膜５上に薄く残存するようする。すると、ＳＯＩ
構造の半導体基板が出来上ることになる。そして、シリ
コン酸化膜５上に薄く残存した半導体基板に薄膜トラン
ジスタ等の素子が形成されることになる。Thereafter, although not shown, the semiconductor substrate 1, for example the semiconductor substrate 1, is polished from its back side so that the semiconductor substrate 1 remains thin on the silicon oxide film 5. Then, SOI
A semiconductor substrate with this structure is completed. Elements such as thin film transistors are then formed on the semiconductor substrate remaining thinly on the silicon oxide film 5.
尚、上記実施例においではＣ０２レーザ光の照射により
加熱処理をしていた。これは、Ｃ０２レーザ光の波長が
約１０μｍであり、シリコンの結晶中は透過するが５ｉ
ｎ２には吸収され半導体基板１を徒らに温度上昇させる
ことな（ＢＰＳＧＪＩ５！ ３、シリコン酸化膜４を効
果的に加熱することができるからである。これは貼り合
わせ後半導体基板が加熱されて結晶欠陥が生じるのを防
止することにもなる。尚、レーザ光をパルスにして与え
れば半導体基板ｌの温度上昇を非常に有効に防止しなが
ら貼り合わせのためのＢＰＳＧ膜３、シリコン酸化膜４
の加熱を行うことができる。しかし、普通の加熱処理に
より貼り合わせを行うようにしても良いことはいうまで
もない。In the above embodiment, the heat treatment was performed by irradiation with C02 laser light. This is because the wavelength of the C02 laser beam is approximately 10 μm, and although it passes through the silicon crystal, 5i
This is because the silicon oxide film 4 can be effectively heated without being absorbed by n2 and causing the temperature of the semiconductor substrate 1 to rise needlessly (BPSGJI5! 3).This is because the semiconductor substrate is heated after bonding. This also prevents crystal defects from occurring.Incidentally, if the laser beam is applied in the form of pulses, the temperature rise of the semiconductor substrate 1 can be very effectively prevented, while the BPSG film 3 and silicon oxide film 4 used for bonding can be prevented.
can be heated. However, it goes without saying that the bonding may be performed by ordinary heat treatment.
また、上記実施例においては、一方の絶縁膜３がＢＰＳ
Ｇからなり、他方の絶縁Ｗ；８４がノンドープのシリコ
ン酸化膜からなっていた。しかし、一方の絶縁１１！２
３をＢＰＳＧに代えてＰＳＧ、ＢＳＧあるいはＡｓ５Ｇ
で形成するようにしても良いし、更には絶縁膜３を例え
ばＢＰＳＧ等非金属不純物がドープされた絶縁膜とノン
ドープの絶縁膜の二層構造にしても良い。Further, in the above embodiment, one of the insulating films 3 is made of BPS.
The other insulator W; 84 was made of a non-doped silicon oxide film. However, one insulation 11!2
Replace 3 with BPSG: PSG, BSG or As5G
Furthermore, the insulating film 3 may have a two-layer structure of an insulating film doped with a non-metallic impurity such as BPSG and a non-doped insulating film.
また、一方の絶縁膜３を非金属不純物ドープ絶縁膜とノ
ンドープ絶縁膜の二層構造にし、他方の絶縁膜４をＢＰ
ＳＧあるいはＰＳＧ等非金属不純物がトープされたシリ
コン酸化膜で形成するようにしても良い等本発明には種
々の変形例が考えられ得る。Further, one insulating film 3 has a two-layer structure of a non-metal impurity doped insulating film and a non-doped insulating film, and the other insulating film 4 has a BP-doped insulating film.
Various modifications can be considered to the present invention, such as forming the silicon oxide film doped with nonmetallic impurities such as SG or PSG.
（Ｈ，発明の効果）
以上に述べたように、本発明半導体基板の製造方法は、
互いに貼り合される２枚の半導体基板の少くとも一方の
半導体基板の表面に形成された絶縁膜の少なくとも表面
部に非金属不純物を予めドープしておくことを特徴とす
るものである。(H, Effect of the invention) As described above, the method for manufacturing a semiconductor substrate of the present invention is as follows:
This method is characterized in that at least the surface portion of an insulating film formed on the surface of at least one of two semiconductor substrates that are bonded together is doped with a non-metallic impurity in advance.
従って、本発明半導体基板の製造方法によれば、一方の
半導体基板の絶縁膜に非金属不純物が含有されているの
で、その絶縁膜の融点が低くなる。従って、低い温度で
加熱しても半導体基板どうしを固着することができる。Therefore, according to the method for manufacturing a semiconductor substrate of the present invention, since the insulating film of one semiconductor substrate contains non-metallic impurities, the melting point of the insulating film is lowered. Therefore, the semiconductor substrates can be fixed to each other even when heated at a low temperature.
しかも、非金属不純物は加熱処理の際に拡散して２つの
絶縁膜の境界部での界面結合の介在物として働くので、
２つの絶縁膜を強固に固着することができる。Moreover, nonmetallic impurities diffuse during heat treatment and act as inclusions for interfacial bonding at the boundary between two insulating films.
Two insulating films can be firmly fixed.
第１図（Ａ）乃至（Ｃ）は本発明半導体基板の製造方法
の一つの実施例を工程順に示す断面図、第２図（Ａ）乃
ｔ（Ｃ）は従来例を工程順に示す断面図である。
符号の説明
１．２・・・半導体基板、
３・・・非金属不純物がドープされた絶縁膜、４・・・
絶縁膜。
出 願 人 ソニー株式会社FIGS. 1(A) to (C) are cross-sectional views showing one embodiment of the method for manufacturing a semiconductor substrate of the present invention in the order of steps, and FIGS. 2(A) to (C) are cross-sectional views showing a conventional example in the order of steps. It is. Explanation of symbols 1.2... Semiconductor substrate, 3... Insulating film doped with non-metallic impurities, 4...
Insulating film. Applicant Sony Corporation
Claims (1)
膜表面どうしが密着するように重ねて加熱処理すること
により貼り合わせて１枚の半導体基板とする半導体基板
の製造方法において、 互いに貼り合される２枚の半導体基板の少くとも一方の
半導体基板の表面に形成された絶縁膜の少なくとも表面
部に非金属不純物を予めドープしておくことを特徴とす
る半導体基板の製造方法(1) In a method of manufacturing a semiconductor substrate, in which two semiconductor substrates each having an insulating film formed on their surfaces are stacked and heat-treated so that the surfaces of the insulating films are in close contact with each other, the semiconductor substrates are bonded together to form a single semiconductor substrate. A method for manufacturing a semiconductor substrate, comprising doping in advance at least a surface portion of an insulating film formed on the surface of at least one of two semiconductor substrates to be bonded together with a non-metallic impurity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1433688A JPH01189145A (en) | 1988-01-23 | 1988-01-23 | Manufacture of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1433688A JPH01189145A (en) | 1988-01-23 | 1988-01-23 | Manufacture of semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01189145A true JPH01189145A (en) | 1989-07-28 |
Family
ID=11858225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1433688A Pending JPH01189145A (en) | 1988-01-23 | 1988-01-23 | Manufacture of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01189145A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453394A (en) * | 1992-01-31 | 1995-09-26 | Canon Kabushiki Kaisha | Process for preparing semiconductor substrate by bringing first and second substrates in contact |
| JP2019513294A (en) * | 2016-03-07 | 2019-05-23 | グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． | Semiconductor on insulator structure including low temperature flowable oxide layer and method of manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5451388A (en) * | 1977-09-29 | 1979-04-23 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of producing semiconductor |
| JPS5717158A (en) * | 1980-07-04 | 1982-01-28 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS62287648A (en) * | 1986-06-06 | 1987-12-14 | Yokogawa Electric Corp | Si bonding method |
-
1988
- 1988-01-23 JP JP1433688A patent/JPH01189145A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5451388A (en) * | 1977-09-29 | 1979-04-23 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of producing semiconductor |
| JPS5717158A (en) * | 1980-07-04 | 1982-01-28 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS62287648A (en) * | 1986-06-06 | 1987-12-14 | Yokogawa Electric Corp | Si bonding method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453394A (en) * | 1992-01-31 | 1995-09-26 | Canon Kabushiki Kaisha | Process for preparing semiconductor substrate by bringing first and second substrates in contact |
| JP2019513294A (en) * | 2016-03-07 | 2019-05-23 | グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． | Semiconductor on insulator structure including low temperature flowable oxide layer and method of manufacturing the same |
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