JPH01185897A - Refresh control circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption and the needed number of a capacitor by providing a refresh cycle setting circuit and a dynamic RAM control signal generation circuit sending a control signal to every memory element group divided into some with the aid of a refresh demand signal so as to execute refresh operation. CONSTITUTION:A counter 12 receiving a clock signal 11 counts up and sends a counter output signal group 13 to the refresh cycle setting circuit 14. When the circuit 14 receives the signal group 13, it sends the refresh demand signal group 16 to the DRAM control signal generation circuit 15 of a next stage. The circuit 15 receiving the signal group 16 outputs the DRAM control signal group 21 to the DRAM groups 17-20. Thus, the refresh operation is executed fro the respective DRAM groups 17-20. As the result of that, the power consumption can be reduced and the number of the capacitor can be reduced according to that.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to storage devices used in information processing, communication systems, etc., and particularly to a dynamic RAM memory controller.

[Conventional technology]

There are various configurations of memory devices, and among them, dynamic RAM (hereinafter referred to as DRAM) plays a major role in increasing the degree of integration of memory devices because it can increase the number of bits per chip.

This DRAM device basically consists of a transistor and a capacitor, and the capacitor is responsible for holding data. It is well known that, due to its physical properties, this capacitor portion has a property unique to DRAM devices in that it transitions to a state in which a large amount of electrons are stored over a long period of time. Therefore, a device is required for periodically regenerating, or refreshing, the information in the memory cells to the correct level. A device that performs such refresh is known as a refresh control device.

[Problem to be solved by the invention]

Conventionally, in this type of refresh control device, refresh control has generally been performed not on individual memory cells but on a plurality of memory cells at once. However, in that case, as the number of memory elements increases, power consumption increases, so there is a problem in that capacitors must be added.

SUMMARY OF THE INVENTION An object of the present invention is to provide a refresh control device for a DRAM device that can eliminate the conventional drawbacks by dividing a plurality of memory elements into several memory element groups and performing refresh for each group. .

[Means to solve the problem]

The dynamic RAM refresh control device of the present invention includes a counter that counts up based on a clock signal;
The output from this counter and the refresh request selection signal output a refresh request signal, and the refresh request signal causes a control signal to be sent to each memory element group divided into several groups. A dynamic RAM control signal generation circuit is provided.

Therefore, when the dynamic RAM refresh control device according to the present invention is used, the refresh cycle setting circuit outputs a refresh request signal in response to an output from a counter that counts up in response to a clock signal and an external refresh request control signal. Then, based on this refresh request signal, the dynamic RAM control signal generation circuit sends a control signal to each divided memory element group, and refreshes them.

Thereby, power consumption can be reduced and the number of capacitors required for this can be reduced.

〔Example〕

The present invention will be described in detail with reference to Examples below.

FIG. 1 is a schematic block diagram showing an embodiment of a dynamic RAM refresh control device according to the present invention, and FIG. 2 is a block diagram showing its details.

In FIG. 1, a counter 1 receives a clock signal 11.
2 counts up and sends the counter output and signal group 13 to the refresh cycle setting circuit 14. The refresh cycle setting circuit 14 uses these counter output signal group 13
Upon receiving the refresh request signal group 16, the refresh request signal group 16 is sent to the DRAM control signal generation circuit 15 at the next stage. The DRAM control signal generation circuit 15 receiving these refresh request signal groups 16 sends all 21 DRAM RAM control signals to the DRAM groups 17-20. As a result, each of the DRAM groups 17 to 20 is refreshed.

Next, this embodiment will be explained in more detail with reference to FIG.

However, the same parts as in FIG. 1 are given the same reference numerals, and the explanation will be omitted as appropriate.

The counter 12 is connected to a flip-flop 23, which is reset by being given a reset signal 24 from the outside. Furthermore, set signals 25 to 28 at the time of presetting are set in the counter 12, and the counter 12 starts counting up based on the clock signal 11.

The counted up values are output to the AND circuit 29 at the next stage as counter output signals 30 to 33. AND circuit 29 outputs these counter output signals 30 to 33 to decoder 34 at the next stage. The decoder 34 that received this
On the other hand, the external refresh request selection signal 35.3
6, and its output is the refresh request signal 37~
Select and activate one of the 40. These refresh request signals 37-40 are connected to the next stage DRAM control signal generation circuits 41-44, respectively.

Further, each of the DRAM control signal generation circuits 41 to 44 is connected to each of the DRAM groups 17 to 20, and
It is configured to provide control signals 45-48.

As described above, any one of the DRAM control signal generation circuits 41 to 44 that receives a selectively activated signal among the refresh request signals 37 to 40 responds to one of the DRAM control signals 45 to 48. DRAM 17
~20. As a result, DRAM1
Among DRAM control signals 7 to 20, the one that receives one of the DRAM control signals 45 to 48 is refreshed.

Note that the counter 12 receives its counter output signals 30 to 3.
3 is given to the AND circuit 29, but by branching the output of this AND circuit 29, it is configured to be reset by the signal input to itself via the flip-flop 23 and start counting from zero anew. has been done.

〔Effect of the invention〕

In this way, the dynamic RAM refresh control device of the present invention performs refresh for each divided memory element group, thereby achieving
This has the effect of reducing power consumption and, therefore, reducing the number of capacitors for this purpose.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing an embodiment of a dynamic RAM NoriFressini control device according to the present invention, and FIG. 2 is a block diagram showing details of FIG. 1. 12...Counter, 14...Refreshini cycle setting circuit, 17-2
0...DRAM. 41-44...DRAM control signal generation circuit.

Claims (1)

[Claims] A counter that counts up based on a clock signal; a refresh cycle setting circuit that outputs a refresh request signal based on the output from the counter and a refresh request selection signal from the outside; 1. A refresh control device comprising: a dynamic RAM control signal generation circuit that sends a control signal to perform refresh for each divided memory element group.