JPH01173750A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To form a memory cell hardly making a soft error to be highly integrated easily by a method wherein capacitance parts of a memory cell and insulation isolating regions are formed in grooves formed around a switching transistor. CONSTITUTION:Grooves 10 as isolating regions are formed around a unit memory cell on a P type semiconductor substrate 1. Plate electrodes 14 as cell capacitances are formed of a conductive material such as poly Si etc. in the grooves 10 through the intermediary of insulating films 11, accumulating electrodes 12 of cell and capacitor insulating films 13. Then, thick insulating films 30 are buried above the plate electrodes 14 to electrically isolate the adjacent transistors simultaneously forming a switching transistor composed of a drain 2, a source 3, a gate insulating film 4, a word line 5 and a bit line 6 such as Al etc., in an island region 20. Consequently, a large capacitance cell hardly making a soft error by alpha rays and causing no leakage can be formed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device, particularly a novel device structure for increasing the density of a DRAM cell array.

Conventional technology As a high-density DRAM memory cell, the "1-transistor/1-capacitor" type memory cell, which consists of one transistor and one capacitor, has fewer components and can easily miniaturize the cell area. , widely used.

In recent years, DRAMs have been pursued to have higher density within a limited chip area, and miniaturization of elements has been required. In a one-transistor/one-capacitor type memory cell, a reduction in memory cell capacity must be avoided as much as possible in order to maintain ease of information determination. For this reason, as a conventional technique, a groove is dug in a semiconductor substrate and the side surface of the groove is used as a capacitor part, thereby reducing the planar area of the capacitor part and increasing the density of the element.

For example, in the configuration shown in FIG. 4, a groove is dug in the p-type semiconductor substrate 61, the plate electrode 58 is embedded, and a capacitor portion is formed on the side surface of the groove. Here, 62 is a bit line, 66 is n
63 is a word line, 66 is a capacitor insulating film, 59 is an isolation region by channel stop, 64 is a gate insulating film, and 67 is a charge storage region.

The above is described, for example, in Japanese Patent Application No. 50-53883.

Problems to be Solved by the Invention In the above conventional configuration, the switching transistor and
It was difficult to increase the density of the -layer because each unit cell required a charge storage region formed in the trench and an isolation region to electrically insulate adjacent memory cells. .

The present invention has been made in view of this point, and an object of the present invention is to provide a semiconductor memory with a higher density than the conventional configuration.

Means for Solving the Problems In order to solve the above-mentioned problems, the memory cell of the semiconductor memory device of the present invention has a structure in which a trench serving as an isolation region is formed in the region where the memory cell array is formed, and the trench is surrounded by the isolation region. A switching transistor is formed within the island of the semiconductor substrate.

An insulating film is formed inside the trench, and a first conductive material is embedded on the insulating film inside the trench. The buried conductive material is electrically divided between adjacent cells within the trench, and the upper end of each divided conductive material is electrically connected to the source portion of the switching transistor.

A thin insulating film is formed on the first conductive material inside the groove, a second conductive material is buried thereon, and an arbitrary bias voltage can be applied to the second conductive material from the outside. . The second conductive material and the first conductive material are electrically insulated, and a thin insulating film between them forms a cell capacitor.

The first part inside the groove. A thick insulating film is formed on the second conductive material, and this thick insulating film electrically isolates adjacent transistors, resulting in a one-transistor/one-capacitance type D
Realize a RAM memory cell.

According to the above-described structure, the present invention uses the first conductive material embedded in the trench of the isolation region formed around the unit memory cell as the storage electrode of the memory cell, and The insulating film formed on the conductive material is used as a capacitor insulating film, the second conductive material embedded on this insulating film is used as a plate electrode, and the storage electrode, capacitor insulating film, and plate electrode form a cell capacitor. form. The above-mentioned No. 1 inside the groove. A thick insulating film is buried on the second conductive material to electrically isolate adjacent transistors and at the same time form a birthbeak-free insulating isolation region.

Embodiment An embodiment of the present invention is shown in FIGS. 1 and 2. Figure 1 shows
FIG. 2 schematically shows a planar configuration of a memory cell array according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line II' in FIG. For ease of explanation, identical components will be described using common numbers.

Here, 1 is a p-type semiconductor substrate, 2 is an n+ type impurity diffusion layer forming the drain of a switching transistor, and 3 is a p-type semiconductor substrate.
is an n+ type impurity diffusion layer which also forms the source of the switching transistor, 4 is a gate insulating film, and 6 is a Po1y
A word line 6 made of Si, polycide, or the like is a bit line made of At or the like, and is electrically connected to the drain 2 through a contact window 7 . This switching transistor is formed in an island region 2o surrounded by a groove 10. 1o is a groove formed in the Si substrate 1;
Finally, a cell capacitance storage portion of the memory cell is formed in the lower part of the trench, and an insulating isolation region of the switching transistor is formed in the upper part of the trench. Reference numeral 11 denotes an insulating film formed on the inner side and bottom surfaces of the trench 1o, 12 a storage electrode formed of PolySt, etc., 13 a capacitor insulating film formed on the storage electrode 12, and 14 made of PolySi. This is a cell plate made of etc.

Here, the storage electrode 12 is connected to the n+ diffusion layer 22 on the side wall of the trench at the source connection portion 21, and as a result is electrically connected to the source 3 of the switching transistor. Next, an insulator 30 is buried inside the trench on the storage electrode 12 and the cell plate 14 to serve as an isolation region for adjacent switching transistors. Furthermore,
31 is an interlayer 5 insulating film. 40.41 is the substrate 1
This is a high impurity concentration region of the same conductivity type as .

Here, the manufacturing method of this example will be briefly explained. p
A groove 10 is formed on the shaped substrate 1 by RIE etching,
Next, an oxide film 11 is formed inside the trench by CVD or the like. After removing the oxide film 11 on the upper part of the trench, an n+ impurity layer 22 is formed on the side wall of the trench in that portion by ion implantation or the like. Next, along the side walls inside the groove, Po1ySi which becomes the storage electrode is
12 is buried, n+ impurity is diffused, and the source connection part 2 is
1, it is connected to the n+ impurity layer 22. Next, a thin oxide film is formed on the PolySi 12 by thermal oxidation or the like to form a capacitor insulating film 13. Next, Po1ySi 14 is buried on the insulating film 13 to form a cell plate. Next, the Po1y 5i12.14 inside the groove
An insulator 3o is formed thereon by CVD or the like to form an insulation isolation region for the switching transistor formed in the island region 20. Next, a switching transistor is formed in the island region 20 by a normal process.

A schematic diagram of a cross-sectional structure showing another embodiment of the present invention is shown in FIG. Here, 45 is a p-type high concentration substrate, and 46 is a low concentration impurity layer formed on the high concentration substrate 46 by epitaxial growth or ion implantation, and has the same conductivity type as the high concentration substrate 45. show. Other components include the first
Since it is similar to the embodiment of the present invention, for ease of explanation,
Omitted.

Effects of the Invention As described above, in the present invention, the following effects can be considered by forming the capacitive portion of the memory cell and the insulation isolation region in the groove formed around the switching transistor.

(1) By using the area around the groove as the storage electrode and cell capacitor of the memory cell, it is possible to increase the cell capacity per unit area on a two-dimensional plane.

(2) Also, since signal charges are stored between the Po1ySi storage electrode inside the groove and the cell plate, it is resistant to soft errors caused by a-rays.

Furthermore, when the conventional LOCO8 method is used for isolation, there is a significant increase in the isolation region from the design pattern and leakage due to the sidewall effect of the switching transistor; however, according to the present invention, (3) the isolation region can be Since it is formed by burying an insulator inside the trench, it is possible to form a fine isolation region according to the designed pattern. It is also possible to completely prevent leakage due to the sidewall effect.

As described above, according to the present invention, it is possible to realize a memory cell that is resistant to soft errors and that can be easily increased in density.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of a unit cell in one embodiment of the present invention, FIG. 2 is a sectional view taken along the line II' in FIG. 1, and FIG. 3 is a schematic sectional view showing another embodiment of the present invention. , FIG. 4 is a schematic sectional view showing a conventional example. 1... Semiconductor substrate, 2... Drain,
3... Source, 6... Word line, 6...
...Pit line, 10...Groove, 11...
...Insulating film, 12...Storage electrode, 13...
...Capacitor insulating film, 14...Cell plate, 20...Island region, 21...Source connection portion, 22...N+ impurity layer, 3o・・・・・・
...Insulator, 40...P+ impurity layer, 41...
... p+ impurity layer, 46 ... high concentration substrate,
46...Low concentration impurity layer. Name of agent: Patent attorney Toshio Nakao and 1 other person5-
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Claims (3)

[Claims] (1) A memory cell array is formed on a semiconductor substrate, a plurality of grooves are formed in the substrate, a switching transistor is formed in an island region surrounded by the grooves, and a storage electrode and a cell plate electrode are formed in the grooves. The storage electrode is formed electrically separated, the storage electrode is connected to the source region of the switching transistor, and any bias is applied from the outside to the cell plate electrode, and the storage electrode and the cell plate electrode are A semiconductor memory device, wherein an element isolation region made of an insulator is formed by filling a trench with an insulator, and a unit cell surrounded by the trench is electrically insulated from an adjacent unit cell. (2) The semiconductor memory device according to claim 1, wherein an impurity layer having the same conductivity type as the substrate is formed on the sidewall and bottom surface of the trench on the substrate side. (3) A second semiconductor layer with a low impurity concentration is formed on a first substrate with a high impurity concentration.
The semiconductor memory device described in Section 1.