JPH01171047A - Chip alternation controller for memory element - Google Patents

Abstract

PURPOSE:To shorten a processing time and to prevent the induction of a two-bit error by using a tester equipped with the internal part of an MSU for the control of the validation processing, making the validation processing into the processing closed in the internal part of the MSU and after the data on a defective chip are written on an alternating chip, executing the chip alternation. CONSTITUTION:A tester 4 equipped conventionally in the internal part of a main storage unit (MSU) 1 is used, the MSU 1 is set to the test mode, the data on a memory chip to generate the fixed bit fault are corrected by an ECC circuit 3 in the MSU, and after the data are written on a preliminary alternating chip, the chip is alternated. The issuance and execution of the access by the validation processing become the closed processing in the internal part of the MSU by executing such as control. Thus, a chip alternation processing time is shortened and the induction of the two-bit error can be prevented.

Description

[Detailed Description of the Invention] [Summary] When a fixed failure occurs in a memory element constituting a storage device of a computer system, the main storage unit (MSU) ) The purpose of this technology is to provide a chip replacement control device for memory elements that can significantly shorten processing time by utilizing testers that have been conventionally installed inside storage devices. a memory chip group consisting of a memory chip group and a replacement chip for switching to a memory chip in which a fixed fault has occurred among the memory chip group; and error correction means, and test means capable of performing a unit test of the storage device and controlling replacement of memory chips using the fault detection and error correction means.

[Industrial application field]

The present invention relates to a memory chip replacement control device that switches a memory element to a spare memory element when a fixed failure occurs in a memory element constituting a computer system, and in particular, the present invention relates to a memory chip replacement control device that switches the memory element to a spare memory element when a fixed failure occurs in a memory element that constitutes a computer system. It has an ECC circuit with a bit error correction function and a tester that controls unit testing of the MSU and chip replacement processing, and performs chip replacement after writing data on a memory chip that has a fixed failure to a spare chip. This invention relates to a chip replacement control method.

[Conventional technology]

When using a computer system, it is a nuisance for the system user to be forced to interrupt work or become unable to read important information such as files due to some kind of failure. In addition, when a failure occurs, it is desirable to recover as quickly as possible. High reliability is particularly required for storage devices in computer systems.

Storage devices in current computer systems are composed of semiconductor memory elements that are broadly classified into bipolar type and MOS type. As semiconductor memory devices become more highly integrated, they operate at smaller energy levels, which makes them more susceptible to alpha rays, resulting in more soft errors. A soft error is a temporary failure, but if a memory element is damaged for some reason, a fixed failure that will always result in a bit error will occur at that location. Malfunctions of memory elements, including soft errors, have a large impact on the entire system, and various countermeasures have been proposed and put into practical use.

SEC-DED (Sin
gle Error Correction-Dou
Error Correction (ECC: Error Checking) using ble Error Detection code
In a system that uses both the 1-bit error correction method and the 1-alternate chip method, if an 8-bit code is added to every 8 bytes of data on the main storage unit (MSU) using the ECC method, 1-bit errors can be automatically eliminated. It is possible to correct and also detect 2-bit errors. When a fixed failure (hard burst error, fixed error in n bits in a memory chip) of a memory element is detected, chip replacement control is performed to switch the memory element to a spare memory element.

The memory contents of this spare replacement chip are undefined, and if left as is, the bits in the replacement chip will generate bit errors at a rate of about %, so it is necessary to write correct data onto the replacement chip. Validation is required.

A block diagram of a conventional example of a chip replacement control device for a memory element including validation is shown in FIG. First, the occurrence of a hard burst error occurs in a service processor (not shown).
VP) will be notified. Service Processor (SVP)
In the same figure (a), replacement information is stored in the main memory (MS).
U) Set in the replacement control register (8LCR) 65 in 61 to instruct replacement to the spare chip. After that, Sv
P instructs the memory control unit (MCU) 66 to start alternation, and the MCU 66 instructs not to rewrite any byte of the 8-byte data, that is, all bits of the BM double signal to be described later are O''.
A partial store is performed on the memory element group 62 comprising 8 bytes including replacement chips. For example, in the case of a 64K x 1-bit RAM, this access is performed 64 times by the access generation circuit 67, and the ECC is executed each time.
Validation is completed by correcting data with a 1-bit error by the circuit 63.

The operation of the conventional example shown in FIG. 6 (bl) is exactly the same as that shown in FIG.
The only difference is that it is not inside the MSU 61. In addition, (C) in the same figure shows sv and p that have received a burst error notification.
is instructing the CPU 68 to issue a diagnostic command, and during this time the CPU is
(top state), shows a method for generating partial store access from inside the CPU 68. In addition, in Fig. 6, a tester (TESTER) 64 inside the MSU 61 is used to perform single device tests, some multiple It is equipped so that it can be used for device connection tests, access load tests, etc.

Next, the principle of validation in conventional chip replacement control will be explained with reference to FIG. First, use (a) for 8 byes)
If a 1-pin fixed error state (IBE) is detected at a certain position (*) on the memory area of the X64, the memory chip (1 bit X64K) at that bit position is switched to a spare replacement chip. After that, in (b), read the data in the memory area mentioned above in units of 8 bytes,
The data is input to the ECC circuit, and if an error is detected, it is corrected and then written to the read position again. By repeating this 64 times, the validation completion state (C) is reached.

[Problem that the invention seeks to solve]

The first problem with the above-mentioned memory chip replacement control method is that chip replacement processing takes a long time. In particular, the validation process takes longer as the degree of construction of the memory element increases. For example, if 64 takes 10 seconds with bit RAM, 256 takes 40 seconds with bit RAM. As shown in FIG. 6(C), when the CPU performs validation processing based on a diagnostic command from the SVP,
The CPU will stop for 40 seconds, which has a large impact on the entire system. Here, the main reason why the validation processing takes a long time is shown in Fig. 6 of the conventional example, where the processing is performed by the MCU.
and MSU, or SVP, CPU.

This is done with the involvement of MCU and MSU.

The second problem is that in Figure 6, the variation processing is performed by the MCU.
While this is carried out using the MSU, the CPU MCU, and the MSU and many other devices, the tester 64 inside the MSU plays no role at all, resulting in inefficient use of the hardware. That is, M.S.
As described above, the tester in U is used for initial testing during hardware development, and is hardly used after mid-term testing or after shipping.

The third problem with conventional chip replacement control is that there is a possibility of inducing a 2-bit error during chip replacement control. In the above-mentioned validation process, in the memory element group constituting the same checking block (the unit in which ECC is performed, e.g. 8 bytes), there is one chip other than the replacement chip.
If a bit error occurs, when checking the 8-byte data including that 1 bit, there is a possibility that a 2-bit error will be detected because the data on the replacement chip is undefined.

The case where this 2-bit error occurs will be explained using FIG. 8. 1 bit error (H) fixed to O at ta> in the same figure
B E) is detected and the memory chip at that bit position is switched to the replacement chip. In a situation where 1-bit errors occur frequently within the same checking block, 1-bit errors (IBE) may exist on another line, for example, at the position 2, in addition to the position 2. Furthermore, even during the validation operation shown in FIG. 2B, a 1-bit error (IBE) may occur, for example, at the O position due to a soft error. Since the data on the alternate channel knob is undefined, if validation processing is performed in this state, there is a high possibility that a 2-bit error (28E) will be detected by the ECC circuit on a line with ■ and ■.

'In other words, if it is originally only a 1-bit error, 1
The validation process for relieving bit errors will result in the creation of 2-bit errors, and the chip replacement control will actually lead to a decrease in reliability. This is because conventional chip replacement control assumes that only one 1-bit error occurs within a group of memory elements that make up the same checking block, and takes into consideration situations where 1-bit errors occur frequently. This is because they were not prepared.

As a partial solution to the problem described in detail above, it is possible to use a 2-bit error correction circuit, temporarily save the contents of the current memory, replace the chip, and then perform rewriting and validation using a full store. It is also possible to do this. However, in the former case, the amount of hardware such as an ECC circuit increases, and in the latter case, the amount of hardware such as a buffer increases. For example, even if a 4 KB buffer is used in the latter case, if 64 chips are used as 8 bytes, 512 KB of validation will be required, which will require 123 switching controls, which is unrealistic.

In view of the above-mentioned problems, the present invention provides a main storage device (MSLJ).
), we provide a chip replacement control device for memory elements that can significantly shorten processing time by utilizing the tester conventionally installed in The purpose of this invention is to establish a chip replacement control method that does not induce 2-bit errors even under various conditions.

[Means for solving problems]

A block diagram of a chip alternation control device for a memory device according to the present invention is shown in FIG. FIG. 1 shows the components of the present invention inside the main storage unit-Z (MSU)1.

In the figure, inside the storage means 2, there are a memory group 2a currently used as a main memory, and a replacement chip 2b.
and are included. The fault detection and error correction means 3 is, for example, an ECC circuit, and has a section for correcting 1-bit errors and detecting 2-bit errors. The test means 4 is, for example, a tester that performs a unit test of the main memory device 1, and utilizes the access function to the memory means 2 and controls chip replacement of memory elements using the fault detection and error correction means 3. Further, an alternation control register (ALCR) 5 is used to store data indicating which memory element is to be substituted.

[For production]

In FIG. 1, the test means 4 is a main storage unit (MSU) 1
A service processor (SvP) (not shown) that receives notification of a hard burst error is a tester for performing unit tests of svp-sci (System Con5
Information regarding the chip replacement, such as validation start address, end address, and other data, is sent to the tester in the form of a command through the ole interface.

The testing means 4 sets the MStJl to test mode, reads data from the storage means 2 in units of, for example, 8 bytes, inputs the data to the fault detection and error correction means 3, corrects a 1-bit error, and then reads the data again. Storage means 2
write to the same area.

This operation is repeated until the memory location corresponding to the end address instructed by SvP ends the validation process.

Here, in order to prevent the induction of 2-bit errors as explained in FIG. 8, the present invention uses a validation method different from the conventional example. Figure 2 shows the principle. The same figure (a
), first read the contents of the memory before replacing the chip every 8 bytes, input it to the ECC circuit, and correct the 1-bit error (BE). The corrected data is written on the same line of the memory again, but only the data for the bit position where a 1-bit error has occurred (defective chip) is written on the replacement chip.

When the above operation is repeated 64 times, validation is completed and the state shown in Fig. 2 (bl) is reached, but after validation is completed, data is not read from the bit position where a 1-bit error has occurred, that is, from the defective chip, and the data When reading, the corresponding replacement bin is read.

As explained above, since the present invention uses a tester conventionally provided inside the MSU to control the validation process, the validation process becomes a closed process inside the MSU, and the data on the defective chi-knob is The feature is that chip replacement is performed after writing on the replacement chip.

〔Example〕

Before explaining the embodiments of the MSU and tester of the present invention, the alternation control register (ALC) shown in FIG.
The contents of R) 5 will be explained with reference to FIG. The figure shows an example of a configuration of 14 bits in total, and bit “00” is an alternate enable bit (ALE).
), and when this bit is "1", it indicates that the contents of ALCR5 are valid. Bit “01” is the alternation completion bit (ALC: Alternate Comp
ete, and when this bit is 1'', it indicates that chip replacement has been completed.

Bits "02" to "13" indicate the position of the replacement bit. First, the five bits "02" to "06" are replacement WAY selection bits (WAYS: WAYS).
5elect). Here, WAY means, for example, that the memory is divided into certain unit parts (capacity), each unit part can be accessed independently, and in one unit part, only one 8-byte data can be accessed. This is the division unit part that was made possible. Here, it is assumed that there are WAYs from 0 to 31. Bit “07” to 1
The 4 bits up to 0'' are alternate byte selection bits and indicate one of a total of 9 bytes, including 8 bytes of data and 1 byte of ECC code. The 3 bits from bits "11" to 13 are alternate bytes. Alternate bit position within, 0 to 7
This is a replacement bit selection bit that indicates one of the following.

FIG. 4 shows an embodiment of the main storage unit (MSU) in the present invention. However, the tester built into the MSU is shown separately in FIG. In FIG. 4, selectors 11 to 13 switch between access from a memory control unit (MCU) 66 and access from a tester inside the MSU. Among the signals input to the selector 11, the GO multiplication signal, the activation signal for the MSU, and the opc signal are accompanied by the Go multiplication signal and indicate the type of access to be processed. The basic accesses of MSU include fetch (one after another) and store (write), and stores include partial store (partial write) and full store (
All writing).

Of the signals input to the selector 12, this is the write data to the WD double signal memory.It is an 8-bit signal that corresponds to each byte of the 8-byte data when writing to the BM double signal memory, and corresponds to the byte to be rewritten in the partial store. In the full store, all bits are rewritten as "1". ADR5 input to selector 13
The signal accompanies the GO times signal and indicates the address of the memory to be accessed.

Also, T&A M input to selector 11, 12, 13
The ODE signal is a mode signal indicating operation in the test and chip alternation control mode, and when this signal is enabled,
Interface signal (Go, OPC) from MCU66
, BM, WD, ADR8) is the signal from the tester (“T”
TGOlTOPCSTBMSTWD, TA
DR3) and input to the MSU.

Pipeline processing is used in the present invention, and the output of the selector 11 is input to the control pipeline 14, the output of the selector 12 is input to the write data pipeline 15, and the output of the selector 13 is input to the address pipeline 16. After check bits (8 bits) are added to the data (8 bytes) on the write data pipeline by the full store check bit generator 17, the data is passed through the selector 18 and write data register 19 to the memory element group (RAM). ARRAY)20. At this time, the write position is determined by the address (ADR3) signal output by the selector 13 and the output of the chip select/write enable (C3/WE) timing generation circuit 21 via the register group 22 as the ADR3/C3/WE signal. It is specified by inputting it to RAMΔRRAY20.

When a fixed failure occurs in the RAM ARPAY 20, a replacement RAM 23 is prepared for the bit position of the 1-bit error, and the replacement control register (
The replacement data input to the selector 25.ALCR) 24.
26. The selector 26 has ADR3/C3/
When the WE signal is input, the alternation control register (ALCR) 24
The data to be written to the bit position specified by is input to the alternate RAM 23 via the selector 25 and register 27.

Next, data reading and error detection and correction by the ECC circuit will be explained. RAM ARRAY20
from the read data register 31, and also from the alternate RAM.
Data read from 23 through register 32 is input to merge (combinational circuit) 34 via selector 33. The data is combined with the write data on the write data pipeline 15 and the above-mentioned byte mark BM in the merge 34, and is then converted into read data.
It is input to the CC/PSTCG circuit 35. Here PSTC
The G circuit is a partial store check bit generator that adds a check bit when performing a partial store of data corrected by the ECC circuit. E.C.C.
The circuit is, for example, S E C D E D (S
ingle Error Correction-Dou
Error Detection) code is used to add 8 check bits to 8 bytes of data to correct 1-bit errors and detect 2-bit errors. The data corrected by the ECC/PSTCG35 and with a new check bit added is sent as write data to the RAM ARR via the selector 18, etc.
Rewritten in AY20.

This data is also input to the MCU and tester at the same time. Furthermore, error (ER) information is output from the ECC/PSTCG 35 to the MCU. When the above operation for one checking block is completed, RAM ARR
Memory chips with faulty bit positions within 0 to 8Y are replaced with RA
Can be switched to M23.

FIG. 5 shows an embodiment of the tester built into the MSU according to the present invention. Commands are given to the task control circuit 41 and the replacement chip control circuit 42 from the service processor (SVP) through the interface (SCI). This built-in tester has the ability to independently diagnose the MSU using svp and SCI without using a memory control unit (MCU). As a diagnostic function, in addition to the function used in the present invention, that is, checking the data on the memory by the ECC circuit, it is also possible to compare the data on the memory with the expected value of this tester.

In Figure 5, the test operation register (TOPR)
43 is a register for setting the operation mode of the tester, and its output signals TGO and TOPC are input to the selector 11 in FIG. 4 in a parity-added format. The test write data register (TWDR) 44 is a register for setting write data WD and byte mark BM necessary for store-related access, and its output signal TBM.
, TWD are input to the selector 12 after parity addition.

A test start address register (TSAR) 45 is a register for setting a test start address, and a test end address register (TEAR) 46 is a register for setting a test end address. Test address register (TAR)
Reference numeral 47 is for setting a test address (TADR3), and the test start address output from the TSAR 45 and the output of the address control circuit 4B are input to the increment circuit 49, and the output becomes the test address. During chip replacement control, the test address is incremented so that the same RAM chip, ie, the same bit position, is accessed. The test address and the test end address are constantly compared by the comparison circuit 50, and when a match is detected between the two, the test, or in the present invention, the replacement chip validation process, ends. The comparison circuit 52 is for comparing the read data with the expected value stored in the test conveyor data register 51, and is used for initial operation tests of the MSU. Chip replacement information is also output from the replacement chip control circuit 42 to the replacement control register 24 shown in FIG.

As explained in detail above, in the present invention, the main memory (M
SU) Using the tester conventionally installed inside,
The MSU is set in a test mode, and the data on the memory chip where the fixed bit failure has occurred is corrected by the ECC circuit within the MSU and written onto the spare replacement chip, and then the chip is replaced. By performing this kind of control, the issuance and execution of access in validation processing becomes a closed process within the MSU, which is different from the conventional MCU.
-MSU or 5VP-4CPU → MCU-MSU
high compared to the validation process performed via
Becomes faster. Furthermore, since chip replacement is performed after correct data is written on the replacement chip, 2-bit errors are prevented from occurring.

〔Effect of the invention〕

In the present invention, since the chip replacement process is performed using a tester conventionally provided in the main storage unit (MSU),
Improves hardware usage efficiency.

In addition, since the validation of replacement chips is a closed process within the MSU, the time required for chip replacement processing can be significantly shortened, and furthermore, the ECC method can prevent 1-bit errors from occurring frequently within the same chip replacement block. Even under such circumstances, it is possible to prevent 2-bit errors from occurring due to validation operations.

[Brief explanation of the drawing]

Figure 1 is a principle block diagram of a chip replacement control device for memory elements of the present invention, Figure 2 +8), (b) is a principle diagram of validation of replacement chips in the present invention, and Figure 3 is a replacement control register in an embodiment. (ΔLCR)
Figure 4 is a block diagram of an example of the main storage unit (MSU), Figure 5 is a block diagram of an example of a tester inside the MSU, Figure 6 + 8), (b), (C) are A block diagram of a conventional example of a chip replacement control device. Figures 7(a), (b), and (e) are principle diagrams of conventional chip replacement validation. Figures 8 (a) and (b) are diagrams of conventional chip replacement control. It is an explanatory diagram of a 2-bit error induced case. 1.61...Main storage unit (MSU), 2.62...
Memory chip group, 2a...Memory chip group currently in use, 2b...
Alternate memory chip, 3.63... ECC circuit, 4.64... MSU built-in tester, 5.65... Alternate control register (A L CR), 6
6...Memory control unit (MCU), 67...Validation access generation circuit, 68...Central processing unit (
CPU).

Claims (1)

[Claims] 1) A group of memory chips currently used as memories (
2a) and a replacement chip (2b) for switching to a memory chip in which a fixed fault has occurred among the memory chip group; a detection and error correction means (3); and a test means (4) for performing a unit test of the storage means (2) and controlling replacement of memory chips using the fault detection and error correction means (3); Chip replacement of a memory element, characterized in that the storage means (2), the fault detection and error correction means (3), and the test means (4) are provided inside a storage device (1) of a computer system. Control device. 2) The storage device (1) is a main storage unit (MSU), and the memory chip constituting the storage means (2) is a RAM.
a chip, and the fault detection and error correction means (3)
is an ECC circuit, and the test means (4) is an MSU
The chip alternation control device for a memory element according to claim 1, wherein the device is a tester built in a memory device. 3) Group of memory chips currently used as memory (
In 2a), the data on the memory chip in which the fixed fault has occurred is corrected by the fault detection and error correction means (3), and the corrected data is written on the replacement chip (2b) before the chip is replaced. Features: Chip alternation control device for memory elements. 4) The chip replacement control device for a memory element according to claim 3, wherein the replacement of the memory chip is performed under the control of a testing means (4).