JPH01168171A - Image sensor drive circuit - Google Patents

Abstract

PURPOSE:To obtain time resolution nearly equal to that in the case of using an image sensor of picture element constitution suitable for the picture size even when the size of a picture is small by reading a line of an undesired range at a high speed and reading surely the storage charge of a photoelectric conversion element in the range. CONSTITUTION:The area requiring picture information and the area not requiring the information are divided in the unit of lines, the content is set in a line discrimination circuit 8 in advance, all horizontal switches 2 are always turned on in the case of undesired lines and a vertical shift register 4 is operated at a high speed to apply skipping. Then the vertical shift register 4 transits to a low speed operation and the horizontal switches 2 are restored sequentially to the OFF state during that time on the undesired line just before the required line, and the photoelectric conversion elements are selected alternatively by the horizontal shift register 3 and the vertical shift register 4 on the required line to apply readout. Thus, the time resolution nearly equal to that in the case of using the image sensor of optimum picture element configuration is obtained.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a drive circuit for an image sensor used in an image scanner, camera, OCR, etc. [Prior Art] A commonly used MOS image sensor has a light receiving section in which photoelectric conversion elements are two-dimensionally arranged to accumulate charges according to the amount of received light. This is an element that obtains two-dimensional image information by sequentially selecting columns. FIG. 5 is a diagram showing the configuration of such a MOS type image sensor. Horizontal pulses are taken into the horizontal shift register 3 in synchronization with a horizontal clock and are sequentially transferred. The output of each stage of the horizontal shift register 3 controls the operation of each horizontal switch in the horizontal switch group 2, and when the output pulse level of the horizontal shift register 3 is high, the horizontal switch is turned on, and when it is low, the horizontal switch is turned on. If it is, it will be turned off. The vertical clock vC1 vertical pulse ~'H is input to the vertical shift register 4, and its operation is controlled by the horizontal shift register 3.
can be considered almost the same as the above, but the number and arrangement of vertical switches to be controlled are significantly different. That is, unlike the horizontal switches in the horizontal switch group 2, the number of vertical switches controlled by the vertical shift register 4 is equal to the number of photoelectric conversion elements in the light receiving section 1. FIG. 6 is a timing chart showing the conventional operation of this image sensor. (A) and (B) in the same figure respectively show the vertical pulse V input to the vertical shift register 4.
P and vertical clock vC1 (C) is a temporally expanded version of the vertical clock VC in (B), and (D) and (E) are horizontal pulses input to the horizontal shift register 3, respectively. The timings of HP and the horizontal clock HC are shown with reference to FIG. 4(B). As shown in (A) and (B) of the same figure, normally only one row of vertical switches is selectively turned on, so that a high-level pulse is applied to IV (vertical period ) is input to the vertical shift register 4, and the rest are at low level. Also, the same figure (C)
As shown in (D) and (E), normally, a high-level pulse corresponding to one horizontal clock is sent at the beginning of the IH (horizontal period) so that only one of the horizontal switches is turned on. Only the output signal is input to the horizontal shift register 3, and the rest are at low level. FIG. 5 shows a state in which the photoelectric conversion element (pixel) in the third row and second column is selected based on the operation shown in FIG. 6. [Problems to be Solved by the Invention] By the way, when such an image sensor is used in a device such as an image scanner, it is desirable to use an image sensor with a pixel configuration that matches the purpose. but,
Developing a new image sensor for each applicable device requires a great deal of effort and expense, so in practice one has no choice but to select and apply an image sensor from among existing ones that has specifications close to the required specifications. For example, there may be cases where a 100x100 image sensor must be used even though a device with 10x100 pixels is sufficient. In such a case, it will take 10 times longer to read one screen than when using an image sensor with the optimal pixel configuration (10 x 100 pixels), and the time resolution of the device will decrease accordingly. Deteriorate. If the time resolution is low, the screen may flow when the object moves or changes. [Means for Solving the Problem] The image sensor drive circuit of the present invention has been made in view of the above problems, and includes a basic clock generation circuit that generates a basic clock, and a light receiving circuit that counts the basic clock. A line that determines whether the line being read in the section is a preset necessary line, an unnecessary line immediately before the necessary line, an unnecessary line immediately after the necessary line, or some other unnecessary line. a determination circuit; a horizontal clock generation circuit that generates a horizontal clock of a fixed period based on a basic clock; and a low-speed vertical clock when the content of the determination output of the row determination circuit is a necessary row or an unnecessary row immediately before and after the row determination circuit. A vertical clock generating circuit that outputs a high-speed vertical clock when the line is an unnecessary line, and a horizontal clock that corresponds to one horizontal clock when the judgment output of the line judgment circuit is a necessary line or an unnecessary line immediately before it. A horizontal pulse generating circuit that outputs a pulse at the beginning of one horizontal period and continuously outputs a horizontal pulse when an unnecessary line immediately after a necessary line or an unnecessary line immediately before and after a necessary line; The vertical pulse generation circuit outputs vertical pulses of a constant period. [Operation] By separating areas that require image information from areas that do not require image information on a line-by-line basis, and setting the contents in the line determination circuit in advance,
In unnecessary rows, all horizontal switches are always on, and the vertical shift register operates at high speed to perform skip reading. In the unnecessary row immediately before the necessary row, the vertical shift register shifts to low-speed operation, while the horizontal switches sequentially return to the off state. In the required row, a photoelectric conversion element is selectively selected by a horizontal shift register and a vertical shift register, and normal reading is performed. Thereafter, all the horizontal switches are turned on again in the unnecessary rows immediately after the necessary rows, and in the subsequent unnecessary rows, the vertical shift register operates at high speed with all the horizontal switches turned on, and reading is skipped again. - [Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, an image sensor consisting of a light receiving section 1, a horizontal switch group 2, a horizontal shift register 3, and a vertical shift register 4 is similar to that shown in FIG. However, it is assumed that the photoelectric conversion elements of the light receiving section 1 are arranged in n rows and 5 columns. The basic clock generation circuit 5 is means for generating a basic clock. The basic clock always has a constant speed and is applied to the horizontal pulse generation circuit 6, horizontal clock generation circuit 7, row determination circuit 8, and vertical pulse generation circuit 9 as timing for synchronizing the operations of each circuit. The vertical pulse output from the vertical pulse generation circuit 9 is not only literally sent to the vertical shift register 4 as a vertical pulse, but also sent to the horizontal pulse generation circuit 6, the horizontal clock generation circuit 7, the row determination circuit 8, and the vertical clock generation circuit 10. It is sent to each of these circuits as a reset signal. The row determination circuit 8 is initialized with a vertical pulse, and then counts the basic clock to determine which pixel row in the light receiving section 1 is currently being read. Then, whether the pixel line in question: ■ belongs to a pixel line to be read, that is, a necessary line, ■ belongs to an unnecessary line immediately before the necessary line, ■ belongs to an unnecessary line immediately after the necessary line, or ■ belongs to another unnecessary line. The determination result is sent to the horizontal pulse generation circuit 6 and the vertical clock generation circuit 10. Note that which lines are considered necessary lines and which lines are unnecessary lines are set in advance. The horizontal clock generation circuit 7 generates a constant speed horizontal clock HC based on the basic clock and sends it to the horizontal shift register 3. The horizontal pulse generation circuit 6 sends a high or low pulse to the horizontal shift register 3 in synchronization with the horizontal clock HC. According to the signal from the row determination circuit 8, if the currently read row is an unnecessary row other than the unnecessary row immediately before the necessary row, a high-level pulse is sent across IH to read the necessary row or immediately before the necessary row. When the line is unnecessary, one high-level pulse corresponding to one horizontal clock is sent to the IH as in normal operation. Vertical clock generation circuit 10 sends vertical clock VC to vertical shift register 4. At this time, according to a signal from the row determination circuit 8, if the currently read row is an unnecessary row excluding unnecessary rows immediately before and after the necessary row, a vertical clock higher than normal is activated. When it is a row, a low-speed vertical clock is sent to the vertical shift register 4. Next, the operation of this embodiment will be explained using FIGS. 2 to 4. FIGS. 2(A) to (D) show the vertical pulse v, respectively.
3 is a timing chart showing the timing of the P1 vertical clock vC1 horizontal pulse HP and the horizontal clock HC, and FIG. FIG. 4 is a diagram showing the relationship between the horizontal clock H
3 is a state transition diagram showing the output state of the horizontal shift register 3 that changes at timing C. FIG. The light receiving unit 1 has photoelectric conversion elements arranged in n rows and 5 columns as described above, of which the gth row (4g) to the mth row (#m
) are considered necessary lines, and the rest are unnecessary lines. It is assumed that this is set in the row determination circuit 8. For unnecessary rows #1 to #g-2 and #m+2 to #n, the horizontal pulse HP output from the horizontal pulse generation circuit 6 is always at a high level based on the determination output from the row determination circuit 8. Become. Therefore, all the output stages of the horizontal shift register 3 become high, and thereby all the horizontal switches of the horizontal switch group 2 are turned on. FIG. 4(A) shows the state of the horizontal shift register 3 at this time, and each output stage is always high (O mark). In this state, when each row is sequentially selected by the vertical shift register 4, all vertical switches in the selected row are turned on, and all charges accumulated in the photoelectric conversion elements in that column are read out. In the row immediately before the required row, that is, the #g-1st row, the horizontal pulse corresponds to one horizontal clock HC as usual, so the output of the horizontal shift register 3 is as shown in FIG.
As shown in B), as the signal is sent by the horizontal clock, it becomes low (x mark) one after another. That is, each horizontal switch in the horizontal switch group 2 is turned off in turn. At this time,
The vertical clock VC is slow as shown in FIGS. 2 and 3, and the row is selected until all the horizontal shift registers 3 become low. In necessary lines #g to #m, normal operations are executed. That is, the vertical clock VC is output at low speed, and the horizontal pulse is a high-level pulse signal only at the beginning of IH. Therefore, at this time, while one row is selected by the vertical shift register 4, the fourth
As shown in Figure (C), each output stage of the horizontal shift register 3 goes high in sequence, and each horizontal switch in the horizontal switch group 2 is selected one by one. Therefore, within this area, each photoelectric conversion element is serially read out one by one. In the unnecessary row #m+1 immediately after the necessary stroke, the vertical clock HC remains at a low speed, but the horizontal pulse HP is always high. Therefore, the significant output of the horizontal shift register 3 is as shown in FIG. 4(D). It gradually goes high until all outputs go high. Each horizontal switch of the horizontal switch group 2 is gradually turned on based on the output of the horizontal shift register 3, and finally all the horizontal switches are turned on. [Effects of the Invention] As explained above, according to the image sensor drive circuit of the present invention, it is possible to read lines in an unnecessary range at high speed in order to shorten the readout time, and to ensure that the accumulated charges of photoelectric conversion elements in that range are It does not have the same effect when reading and reading the required range of rows. Therefore, even if the image to be read is smaller than the pixel configuration of the image sensor, it is possible to obtain almost the same temporal resolution as when using an image sensor with the pixel configuration most suitable for the image size. In other words, there is no need to individually design and manufacture image sensors depending on the applicable model, and it is possible to obtain the same functionality as a custom-made product using a low-cost so-called standard product.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram showing one embodiment of the present invention, Figure 2 (A)
or D) are timing charts showing the timing of the vertical pulse VP1, the vertical clock VC1, the horizontal pulse HP, and the horizontal clock HC, respectively, and FIG. A diagram showing the correspondence with the physical layout,
Fig. 4 is a state transition diagram showing the output state of the horizontal shift register that changes at the timing of the horizontal clock HC, Fig. 5 is a configuration diagram showing a general image sensor, and Fig. 6 shows the conventional operation of the image sensor. This is a timing chart. DESCRIPTION OF SYMBOLS 1... Light receiving part, 2... Horizontal switch group, 3... Horizontal shift register, 4... Vertical shift register, 5...
...Basic clock generation circuit, 6...Horizontal pulse generation circuit, 7...Horizontal clock generation circuit, 8...Line determination circuit, 9...Vertical pulse generation circuit, 10...Vertical clock generation circuit . Patent applicant: Sumitomo Electric Industries, Ltd. Representative patent attorney Yoshiki Hase
Salt 1) Tatsuya first evil (A) (B) (C)
(D) Procedural amendment August 17, 1988 Patent Application No. 325741 of 1988 2 Name of the invention Image sensor drive circuit 3 Relationship with the person making the amendment Patent applicant (213) Sumitomo Electric Industries, Ltd. 4 Agent (Postal code 101) 4th floor 5, Foresight Building, 3-5-2 Iwamoto-cho, Chiyoda-ku, Tokyo Description and drawings subject to amendment 6 Contents of amendment (1) The entire text of the specification will be amended as shown in the attached sheet. . (2> Figures 1 to 6 of the drawings are corrected as shown in the attached sheet. Description 1, Title of the invention Image sensor drive circuit 2, Claims photoelectric conversion elements are arranged in a two-dimensional matrix and each photoelectric conversion element is arranged in a two-dimensional matrix. a light receiving section in which vertical switches are connected to the elements on a one-to-one basis; a vertical shift register that sequentially turns on the vertical switches for each row when a vertical gate signal of "1" is inputted in synchronization with a vertical clock; A horizontal switch that is connected one-to-one to a readout line that bundles the outputs of the vertical switches for each column, and a horizontal shifter that sequentially turns on the horizontal switches when a horizontal gate signal of "1" is input in synchronization with a horizontal clock. an image sensor driving circuit comprising: a basic clock generation circuit that generates the basic clock; and a register that counts the basic clock and determines whether the row being read out in the light receiving section is a preset required row; A line determination circuit that determines whether the line is an unnecessary line immediately before a necessary line, an unnecessary line immediately after a necessary line, or another unnecessary line, and generates a horizontal clock with a constant period based on the basic clock. When the content of the judgment output of the horizontal clock generation circuit and the row judgment circuit is a necessary line or an unnecessary line immediately before and after it, a low-speed vertical clock is output, and when it is another unnecessary line, a high-speed vertical clock is output. When the content of the judgment output from the vertical clock generation circuit and the row judgment circuit is a necessary line or an unnecessary line immediately before it, the horizontal gate signal corresponding to the horizontal clock is set to "1" only at the beginning of one horizontal period to identify the necessary line. a horizontal gate signal generation circuit that continuously sets a horizontal gate signal to "1" when the line is an unnecessary line immediately after the line or an unnecessary line immediately before and after the necessary line; 3. Detailed Description of the Invention [Field of Industrial Application] This invention is an image sensor drive circuit equipped with a vertical gate signal generation circuit for "1". 3. Detailed Description of the Invention [Field of Industrial Application] This relates to a sensor drive circuit. [Prior Art] A commonly used MO8 type image sensor has a light receiving section in which photoelectric conversion elements are two-dimensionally arranged to accumulate charges according to the amount of received light. This is an element that obtains two-dimensional image information by sequentially selecting specific rows and columns in a group of photoelectric conversion elements. Fig. 5 is a diagram showing the configuration of such an MO3 type image sensor. Horizontal gate signals are taken into the horizontal shift register 3 in synchronization with the horizontal clock and are sequentially transferred. The output of each stage of the horizontal shift register 3 controls the operation of each horizontal switch in the horizontal switch group 2, and if the output of the horizontal shift register 3 is "1", the horizontal switch is turned on, and the output is "0". ”, it is turned off. Vertical clock VC1 and vertical gate signal VG are input to vertical shift register 4, and its operation can be considered to be almost the same as horizontal shift register 3, but the number and arrangement of vertical switches to be controlled are largely different. That is, unlike the horizontal switches in the horizontal switch group 2, the number of vertical switches controlled by the vertical shift register 4 is equal to the number of photoelectric conversion elements in the light receiving section 1. FIG. 6 is a timing chart showing the conventional operation of this image sensor. (A) and (B) of the same figure are the vertical gate signal VG and vertical clock vC1 input to the vertical shift register 4, respectively. (C) of the figure is (B)
), and (D) and (E) are the timings of the horizontal gate signal HG and horizontal clock HC input to the horizontal shift register 3, respectively. This is shown as a standard. As shown in (A) and (B) of the same figure, normally, a vertical gate signal of "1" is sent to IV in synchronization with one vertical clock VC so that only one row of vertical switches are selectively turned on.
Only one shot is input to the vertical shift register 4 at the beginning of the (vertical cycle), and the rest are "0". Also, the same figure (C)
As shown in (D) and (E), normally, a horizontal gate signal of "1" corresponding to one horizontal clock is placed at the beginning of the IH (horizontal period) so that only one horizontal switch is turned on. Only one shot is input to the horizontal shift register 3, and the rest are "0". FIG. 5 shows a state in which the photoelectric conversion element (pixel) in the third row and second column is selected based on the operation shown in FIG. 6. [Problems to be Solved by the Invention] By the way, when such an image sensor is used in a device such as an image scanner, it is desirable to use an image sensor with a pixel configuration that matches the purpose. but,
Developing a new image sensor for each applicable device requires a great deal of effort and expense, so in practice one has no choice but to select and apply an image sensor from among existing ones that has specifications close to the required specifications. For example, there may be cases where a 100x100 image sensor must be used even though a device with 10x100 pixels is sufficient. In such a case, it takes 10 times longer to read one screen than when using an image sensor with an optimal pixel configuration (10×100 pixels). Each photoelectric conversion element of an image sensor has a time interval between when that element is read and when it is read again.
That is, all the optical information that enters during the time it takes to read one screen is accumulated. Therefore, the longer it takes to read one screen, the worse the time resolution of the device becomes. If the time resolution is low, the screen may flow when the object moves or changes. [Means for Solving the Problem] The image sensor drive circuit of the present invention has been made in view of the above problems, and includes a basic clock generation circuit that generates a basic clock, and a light receiving circuit that counts the basic clock. A line that determines whether the line being read in the section is a preset necessary line, an unnecessary line immediately before the necessary line, an unnecessary line immediately after the necessary line, or some other unnecessary line. a determination circuit; a horizontal clock generation circuit that generates a horizontal clock of a fixed period based on a basic clock; and a low-speed vertical clock when the content of the determination output of the row determination circuit is a necessary row or an unnecessary row immediately before and after the row determination circuit. a vertical clock generating circuit that outputs a high-speed vertical clock when the line is an unnecessary line; and a horizontal clock generating circuit that synchronizes with one horizontal clock when the judgment output of the line judgment circuit is a necessary line or an unnecessary line immediately before it. The gate signal is set to "1" only at the beginning of one horizontal period, and is set to "1" continuously when it is an unnecessary row immediately after a necessary row or an unnecessary row immediately before and after a necessary row.
The present invention includes a horizontal gate signal generation circuit that counts the basic clock and sets a vertical gate signal of a constant period to "1". [Operation] By separating areas that require image information from areas that do not require image information on a line-by-line basis, and setting the contents in the line determination circuit in advance,
In unnecessary rows, all horizontal switches are always on, and the vertical shift register operates at high speed to perform skip reading. In the unnecessary row immediately before the necessary row, the vertical shift register shifts to low-speed operation, while the horizontal switches sequentially return to the off state. In the required row, a photoelectric conversion element is selectively selected by a horizontal shift register and a vertical shift register, and normal reading is performed. Thereafter, all the horizontal switches are turned on again in the unnecessary rows immediately after the necessary rows, and in the subsequent unnecessary rows, the vertical shift register operates at high speed with all the horizontal switches turned on, and reading is skipped again. [Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, an image sensor consisting of a light receiving section 1, a horizontal switch group 2, a horizontal shift register 3, and a vertical shift register 4 is similar to that shown in FIG. However, it is assumed that the photoelectric conversion elements of the light receiving section 1 are arranged in n rows and 5 columns. The basic clock generation circuit 5 is means for generating a basic clock. The basic clock always has a constant speed and is applied to the horizontal gate signal generation circuit 6, horizontal clock generation circuit 7, row determination circuit 8, and vertical gate signal generation circuit 9 as timing for synchronizing the operations of each circuit. The vertical gate signal outputted by the vertical gate signal generation circuit 9 is literally used as a vertical gate signal by the vertical shift register 4.
In addition to being sent to the horizontal gate signal generating circuit 6, the horizontal clock generating circuit 7, the row determining circuit 8, and the vertical clock generating circuit 10, the reset signal is sent to each of these circuits. The row determination circuit 8 is initialized by a vertical gate signal, and then counts basic clocks to determine which pixel row in the light receiving section 1 is currently being read. Then, whether the pixel line in question: ■ belongs to a pixel line to be read, that is, a necessary line, ■ belongs to an unnecessary line immediately before the necessary line, ■ belongs to an unnecessary line immediately after the necessary line, or ■ belongs to another unnecessary line. The determination result is sent to the horizontal gate signal generation circuit 6 and the vertical clock generation circuit 10. Note that which lines are considered necessary lines and which lines are unnecessary lines are set in advance. The horizontal clock generation circuit 7 generates a constant speed horizontal clock HC based on the basic clock and sends it to the horizontal shift register 3. The horizontal gate signal generation circuit 6 sends a high or low gate signal to the horizontal shift register 3 in synchronization with the horizontal clock HC. When the currently read line is an unnecessary line other than the unnecessary line immediately before the necessary line, "1" is sent across the IH according to the signal from the line determination circuit 8, and the necessary line or the unnecessary line immediately before the necessary line is read out. When the row is unnecessary, one "1" corresponding to one horizontal clock is sent to the IH as in normal operation. Vertical clock generation circuit 10 sends vertical clock VC to vertical shift register 4. At this time, according to a signal from the row determination circuit 8, if the currently read row is an unnecessary row excluding unnecessary rows immediately before and after the necessary row, a vertical clock higher than normal is activated. When it is a row, a low-speed vertical clock is sent to the vertical shift register 4. Next, the operation of this embodiment will be explained using FIGS. 2 to 4. 2(A) to 2(D) are timing charts showing the timing of the vertical gate signal VG, vertical lock vC1 horizontal gate signal HG and horizontal clock HC, respectively, and FIG. 3 is a timing chart showing the vertical clock VC and the horizontal gate signal 4 is a diagram showing the correspondence between the timing of HG and the physical arrangement of photoelectric conversion elements in the light receiving section 1, and FIG. 4 is a state transition showing the output state of the horizontal shift register 3 that changes at the timing of the horizontal clock HC. It is a diagram. The light receiving unit 1 has photoelectric conversion elements arranged in n rows and 5 columns as described above, among which the Ωth row (
Lines #g) to m-th line (#m) are necessary lines, and the rest are unnecessary lines. It is assumed that this is set in the row determination circuit 8. For unnecessary rows #1 to #g-2 and #m+2 to #n, the horizontal gate signal HG output from the horizontal gate signal generation circuit 6 is always " 1”. Therefore, all the output stages of the horizontal shift register 3 become "1", and thereby all the horizontal switches of the horizontal switch group 2 are turned on. FIG. 4(A) shows the state of the horizontal shift register 3 at this time, and each output stage is always "1". In this state, when each row is sequentially selected by the vertical shift register 4, all vertical switches in the selected row are turned on, and all charges accumulated in the photoelectric conversion elements in that column are read out. In the line immediately before the required line, that is, the #1-1st line, the horizontal gate signal becomes "1" only at the beginning of one horizontal period in synchronization with one horizontal clock HC as usual, so the output of the horizontal shift register 3 As shown in FIG. 4(B), the signal gradually becomes "0" as it is sent by the horizontal clock. That is, each horizontal switch in the horizontal switch group 2 is turned off in turn. At this time, the vertical clock VC is at a low speed as shown in FIGS. 2 and 3, and the row is selected until the horizontal shift register 3 becomes all "0". In necessary lines #g to #m, normal operations are executed. That is, the vertical clock VC is output at low speed, and the horizontal gate signal is "1" only at the beginning of IH. Therefore, at this time, while one row is selected by the vertical shift register 4, each output stage of the horizontal shift register 3 is sequentially set to "1" as shown in FIG. 4(C).
Then, each horizontal switch in the horizontal switch group 2 is selected one by one. Therefore, within this area,
Each photoelectric conversion element is serially read out one by one. In the unnecessary row #m+1 immediately after the necessary addition, the vertical clock HC remains at a low speed, but the horizontal gate signal HG is always "1".
Therefore, the output of the horizontal shift register 3 gradually becomes "1" as shown in FIG. 4(D),
Finally, all outputs become "1". Horizontal switch group 2
Each horizontal switch is gradually turned on based on the output of the horizontal shift register 3, and finally all horizontal switches are turned on. [Effects of the Invention] As explained above, according to the image sensor drive circuit of the present invention, it is possible to read lines in an unnecessary range at high speed in order to shorten the readout time, and to ensure that the accumulated charges of photoelectric conversion elements in that range are It does not have the same effect when reading and reading the required range of rows. Therefore, even if the image to be read is smaller than the pixel configuration of the image sensor, it is possible to obtain almost the same temporal resolution as when using an image sensor with the pixel configuration most suitable for the image size. In other words, there is no need to individually design and manufacture image sensors depending on the applicable model, and functions equivalent to those of custom-made products can be obtained using low-cost so-called standard products.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram showing one embodiment of the present invention, Figure 2 (A)
or D) are vertical gate signal VG, vertical lock vC1 horizontal gate signal HG, and horizontal clock HC, respectively.
3 is a diagram showing the correspondence between the timing of the vertical clock VC and the horizontal gate signal HG and the physical arrangement of the photoelectric conversion elements in the light receiving section 1. FIG. 4 is a timing chart showing the timing of the horizontal clock HC. FIG. 5 is a state transition diagram showing the output state of the horizontal shift register that changes at the timing of . FIG. 5 is a configuration diagram showing a general image sensor, and FIG. 6 is a timing chart showing the conventional operation of the image sensor. DESCRIPTION OF SYMBOLS 1... Light receiving part, 2... Horizontal switch group, 3... Horizontal shift register, 4... Vertical shift register, 5...
... Basic clock generation circuit, 6... Horizontal gate signal generation circuit, 7... Horizontal clock generation circuit, 8... Row determination circuit, 9... Vertical gate signal generation circuit, 10...
Vertical blackout generation circuit. Patent applicant: Sumitomo Electric Industries, Ltd.

Claims (1)

[Scope of Claims] A light receiving section in which photoelectric conversion elements are arranged in a two-dimensional matrix and a vertical switch is connected to each photoelectric conversion element on a one-to-one basis; A vertical shift register that is turned on sequentially for each row, a horizontal switch that is connected one-to-one to a readout line that bundles the outputs of the vertical switches for each column, and a horizontal pulse that is input in synchronization with a horizontal clock. An image sensor drive circuit comprising: a horizontal shift register that sequentially turns on the horizontal switches; a basic clock generation circuit that generates the basic clock; A line determination circuit that determines whether it is a preset necessary line, an unnecessary line immediately before a necessary line, an unnecessary line immediately after a necessary line, or some other unnecessary line, and a basic clock. a horizontal clock generation circuit that generates a horizontal clock of a constant period based on the horizontal clock; and a horizontal clock generation circuit that generates a horizontal clock of a constant period based on the row determination circuit; A vertical clock generation circuit outputs a high-speed vertical clock at certain times, and when the content of the judgment output of the row judgment circuit is a necessary line or an unnecessary line immediately before it, a horizontal pulse corresponding to one horizontal clock is output at the beginning of one horizontal period. a horizontal pulse generating circuit that continuously outputs horizontal pulses when the line is an unnecessary line immediately after a necessary line or an unnecessary line immediately before and after a necessary line; An image sensor drive circuit equipped with a vertical pulse generation circuit.