JPH01129614A - Lock detection circuit - Google Patents

Abstract

PURPOSE:To keep the lock state when a change signal is within a prescribed range with respect to a reference signal by keeping the output of the lock signal when the PLL is in the lock state and the phase difference is within the prescribed range and outputting an unlock signal when the prescribed range is deviated. CONSTITUTION:If the phase of a reference signal fR and that of a comparison signal fV are deviated, comparison outputs EU, ED are pulse widths corresponding to the phase deviation. While the EU is at L, since the pulse width corresponds within one pulse of original oscillation signal Xin/8, outputs of shift registers D-FF 28, 29 are not both at H. Thus, the signal S5 is not changed to L, a signal S11 is at N and the lock is kept. On the other hand, if the phase difference of the signals fR and fV exceeds the frequency fluctuation of FM modulation, each stage output of the D-/F 28, 29 goes both to H. Thus, the signal S5 goes from H to L and the D-FF 30-32 are reset, the signal S9 goes to H and the output S11 of the unlock detector 42 goes to L from H to be an unlock signal.

Description

[Detailed Description of the Invention] [100th] Overview Industrial Field of Application Prior Art (Figure 4.5) Problems to be Solved by the Invention Means for Solving the Problems Working Examples of the Present Invention Embodiment (Figs. 1 to 3) Effects of the invention [Summary] Regarding the lock detection circuit, even if the change signal fluctuates within a predetermined range with respect to the reference signal, the unlock signal is not output, and the lock state is properly determined. The purpose of the present invention is to provide a lock detection circuit that can maintain a lock, and includes a first circuit that receives a signal with a pulse width corresponding to the phase difference between a reference signal and a comparison signal from a phase comparator, and detects that the pulse width is within a predetermined range. detection means, unlock detection means for outputting an unlock signal when the pulse width exceeds the predetermined range, and a state in which the pulse width is within the predetermined range while outputting the unlock signal; and a second detection means that outputs a lock signal when the lock signal is maintained for a predetermined period of time.

[Industrial application field]

The present invention relates to a lock detection circuit, and for example, to a lock detection circuit used in a PLL frequency synthesizer or the like.

P L L (Phase Locked Loop
: Phase synchronized circuit) is a circuit that generates a signal that is phase-synchronized with a reference signal, and is on the motor rotation speed side? It is widely used in I (for example, audio players) and frequency synthesizers. That is, a synthesizer type oscillation circuit using a PLL is suitable for applications where the oscillation frequency is highly stable and the frequency is variable, and is suitable, for example, for FM transmitters such as car phones. P like this
In LL, the reference signal and ■Co (Votage Con
A lock detection circuit is used to compare the frequency and phase of an input signal from the oscillation of a trolled zero oscillator (voltage controlled oscillator) and detect locking or unlocking of the PLL.

[Prior Art] An example of a conventional lock detection circuit used in a PLL frequency synthesizer is shown in FIG. 4.5. FIG. 4 is a block diagram of an FM transmitter using a PLL frequency synthesizer. In this figure, the reference oscillator 1 is constituted by a stable crystal oscillator circuit,
The reference frequency divider 2 sequentially divides the frequency of the original oscillation signal Xin to generate a reference signal fR having a predetermined reference frequency.

The phase comparator 3 is a digital phase comparison circuit based on logic, and compares the frequency and phase of the comparison signal fv obtained by dividing the output fin from the VCO 4 by the comparison frequency divider 5 and the reference signal fR, and calculates the difference. Comparison output E according to
Output u and En. Here, when the frequency or phase difference of fR and fv is fR>fv (fu is a phase lead or the frequency is high), EU becomes the [L] level for a time corresponding to the phase difference, and at this time El, -[H ) remains the same. On the other hand, when fv>fi, (fv is a phase lead or has a high frequency), ED lasts for a time corresponding to the phase difference [L
] level, and at this time it remains at E, J - (H). On the other hand, when the phases of fR and fv match, E
LI and E. Both become (H) level.

Lock Detector: L
D) 6 is based on the comparison output EU, E, fR and fv
It is detected whether the phases match (locked state) or not (unlocked state), and the detection result is output to the FM transmitting/transmitting unit. On the other hand, the charge pump 8 is P,
It consists of an N-channel MO3I-transistor and an inverter, and based on the comparison outputs Eu and En, EU-E is set at fR=fV.
. - (H), outputs a high impedance signal, and at other times fR>fv or fR<fv (
Outputs a signal that becomes H) or (L). In other words, fR
Corresponding to the delay and advance of the phase of and fv, EU and ED become (L) for the time of the phase difference, respectively, and each MO3) transistor of the charge pump 8 is turned on to cause current to flow into or out of its output line. With this function, the DC error voltage due to the phase difference between fR and fv is detected at the output of the LPF 9 connected to the charge pump 8. The oscillation frequency of VCO4 changes depending on the control voltage, and the phase of VCO4, that is,
If the phase of fv is ahead of fR, the oscillation frequency is lowered to delay the phase, and if the opposite is the case, the oscillation frequency is increased to advance the phase, and the output signal is used as the output signal of the PLL to the FM transmission unit. do. FM signal is VCO
4 by modulating the signal from the microphone MC with an audio signal or the like.

The FMM signal unit is for transmitting the FM signal from the VCO 4, and is based on the output from the lock detector 6.
When the output frequency of CO4 (corresponding to rv) and the reference frequency fR are in synchronization (locked state), normal transmission continues,
If it falls out of a predetermined synchronization holding range (lock range), it is assumed that the lock is unlocked and transmission is stopped.

Here, the lock detector 6 includes an AND gate 10, a buffer 11, a terminal 12 .
13, terminal]2 has a capacitor 1
4 is connected. The lock detector 6 has a comparison voltage Eu,
AND the En and send it to the terminal 1 via the buffer 11.
3 outputs a lock or unlock signal to the outside, but for example, unlock detection is output in the form of a pulse, so in order to actually use it as a muting signal in the FM transmitter unit 7, it must be output once to the outside and connected to a capacitor. 14
The signal is smoothed and passed through the buffer 11.

[Problem that the invention seeks to solve]

However, in such a conventional lock detection circuit, the lock detector 6 has a simple configuration as shown in FIG. 5, so the transmission frequency is shifted according to the audio signal by applying FM modulation to the VCO 4. In this case, there is a problem in that even a slight deviation in frequency causes the unlock signal to be output from the mouth/slip detector 6, and FM transmission is stopped.

Because it is FM modulation, the transmission frequency shifts within a predetermined range, but if the degree of shift is large, it is considered unlocked even if it is within the synchronization retention range, so the lock detector 6 Improvement is desired.

The above are problems when applying a lock detection circuit to FM modulation equipped with a PLL, but there are also problems with devices that include a lock detection circuit in a PLL, such as audio equipment, televisions, etc.
Similar problems occur even in the case of motor control, etc.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a lock detection circuit that does not output an unlock signal even if a change signal fluctuates within a predetermined range with respect to a reference signal, and can appropriately maintain a locked state.

[Means for solving problems]

In order to achieve the above object, the lock detection circuit according to the present invention receives a signal having a pulse width corresponding to the phase difference between a reference signal and a comparison signal from a phase comparator, and detects that the pulse width is within a predetermined range. detection means, unlock detection means for outputting an unlock signal when the pulse width exceeds the predetermined range, and a state in which the pulse width is within the predetermined range while outputting the unlock signal; and second detection means that outputs a lock signal when the lock is maintained for a predetermined period of time.

[For production]

In the present invention, when the phase difference between the reference signal and the change signal is within a predetermined range, a lock signal indicating that the PLL is locked is output, and when the PLL is in the locked state, these phase differences are within the predetermined range. If it is within the second predetermined range, the lock signal continues to be output, and if it is out of the second predetermined range, an unlock signal is output.

Therefore, even if, for example, FM modulation is applied and the change signal changes within a normal range, the unlock signal will not be output and the locked state will be maintained appropriately. or,
- Once the device is in the unlocked state, it does not output a lock signal even if it is pseudo-locked, but outputs a lock signal after it is securely locked.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 3 are diagrams showing one embodiment of a lock detection circuit according to the present invention, and are examples in which the present invention is applied to an FM transmitter equipped with a PLL. Since the lock detection circuit of this embodiment is an example applied to an FM transmitter having the configuration as shown in FIG. 4, as in the conventional case, a redundant explanation of FIG. 4 will be avoided.
A detailed explanation of the present invention regarding the inside of the lock detector 21 will be given.

FIG. 1 is a diagram showing the internal circuit of the lock detector 21,
In this figure, the lock detector 21 is connected to the Nantes gate 22.
25, inverters 26, 27, and D flip-flops 28-32. A comparison output (signal with a pulse width corresponding to the phase difference) Eu 1En is input from the phase comparator 3 to the Nant gate 22, and the Nant gate 22 is composed of two D flip-flops 28 and 29.
connected to the shift register of the stage. The Q output of the D flip-flop 28 is input to one input terminal of the NAND gate 23, and the output of the D flip-flop 29 is input via the inverter 26 to the other input terminal of the NAND gate 23. ing. The above Nantes Gate 22.23,
The D flip-flops 28, 29 and the inverter 26 constitute the first detection means 41. Further, a frequency-divided signal Xin/8 of 1/8 of the original oscillation signal Xin of the reference oscillator 1 shown in FIG. 4 is input to each clock terminal CK of the D flip-flop 28, 29, and
8.29 operates in synchronization with the clock of this frequency-divided signal Xin/8. The first detection means 41 has the number of stages of a shift register constituted by D flip-flops 28 and 29 corresponding to the detection range (predetermined range in the claims) of the phase difference between the reference signal fR and the comparison signal fv, The detection range can be changed by changing the number of stages and the clock frequency Xin/8. The output of the Nant gate 23 is input to two Nant gates 24 and 25 forming an R-S flip-flop, and is also input to each reset terminal R of three D flip-flops 30 to 32 forming an asynchronous counter. It has become so. The Nant gates 24 and 25 constitute unlock detection means 42 by low active R-S flip-flops.

On the other hand, the reference signal fR is input to the clock terminal CK of the D flip-flop 30 via the inverter 27, and the clock terminal C of the other D flip-flops 31 and 32 is inputted to the clock terminal CK of the D flip-flop 30.
The i outputs of the D flip-flops 30 and 31 in the previous stage are respectively input to K. The above inverter 26.27,
The D flip-flops 30 to 32 keep the phase difference between the reference signal fR and the comparison signal fv within a predetermined range (D flip-flop 2
8.29), which counts the reference signal a predetermined number of times.
The detecting means 43 of FIG.

Next, the effect will be explained.

When the VCO 4 is subjected to FM modulation with the audio signal from the microphone MC and the FM transmission unit 7 is performing FM transmission, the reference signal fR and the comparison signal fv are output from the phase comparator 3.
The pulse width comparison outputs Eu, En according to the phase difference with fR,l! are input to the lock detector 21, and fR,l! :FM transmission is continued or stopped depending on the phase difference with fv. Locking and unlocking will be described below with reference to the timing chart of FIG. 2.3.

(1) When outputting the lock state (second box) If the signals of each part of the lock detector 21 are respectively SI to S11 as shown in FIG. 1, the reference signal fR and comparison signal fv are as shown in FIG. When each signal Xin/8, E
u, En, S+ to Sl+ change as shown in FIG. In Fig. 2, ■ is a case where the phases of f and fv coincidentally exist, and at this time, the comparison outputs EU and ED both become [H], and the output S1 of the Nantes gate 22 becomes (L), and the clock Xin/ DFF28 at the timing synchronized with the change of 8.
The output S2 of the gate becomes (L), and the output S5 of the Nantes gate 23 becomes (H). Therefore, as it is, the unlock detection means 42 consisting of the Nant gates 24 and 25 will indicate a locked state (H) even though the phases match only by chance.
However, in this embodiment, since the signal S5 is also input to the reset terminals of the D-level switches 30 to 32, the (H) level lock signal S1+ is not actually output. In other words, since the phase is coincidental, both Eu and En will no longer be (H) by the next cycle of fR, and therefore the signal S
5 changes to (L) immediately in synchronization with the clock Xin/8.

As a result, the D flip-flop knobs 30 to 32 are reset without counting the knobs of fR even once, and the output of the D flip-flop 32 is not inverted and the signal S is (L ) level. Therefore, even if the signal S becomes (H), S9 remains [H], and the output S of the unlock detection means 42 remains (L).
) and maintains the unlock signal. In this way, fR
A lock signal will not be output even if the phases of and fv are coincidental. This is because there are D flip-flops 30 to 32, so at least the phase of fR and fv match, and the signal means that the open/tsuku signal is output only when this state continues for 4 pulses of fR. Output. In case @, the phases are not matched, so the state remains unrotated.

On the other hand, after the phases match as in the case of O, if the phase match state continues for more than 4 pulses of fR, the output S of the D flip-flop 32 is inverted and becomes CL), thereby detecting unlocking. The output Sl+ of the means 42 is (H)
Serves as a level lock signal. Incidentally, by increasing or decreasing the number of stages of the counter constituted by the D clip-flops 30 to 32, it is possible to control the time from when the phases of f, l and fv are established until the lock signal is output.

(II) When outputting the unlocked state (see Fig. 3) In the case of ■ in Fig. 3, fR and fv are in phase, and the output S of the unlocking detection means 42 indicates the locked state. (H) level signal (lock signal).If the phase difference between fR and fv is small as in the case (■), specifically, the signal Xin/8 rises once or less. This is a case where the VCO only captures
This corresponds to a phase shift equivalent to that obtained by applying FM modulation to 4 in the normal state. Therefore, it is not preferable that an unlock signal is generated with such a normal phase shift.

Therefore, in this embodiment, the process is as follows. That is, when the phase shifts as described above, the comparison output E0 or E[l becomes a pulse having a width corresponding to the phase shift width. In the case of ■ in FIG. 3, the period during which ELl is at (L) corresponds to the above width. At this time, Ev= (L)
Since the period corresponds only to within one pulse of the signal Xin/8, the D flip-flop 28.2
Since the outputs of each stage of the shift register configured by 9 do not become (H), and the signal S does not change to [L],
The signal Sl+ still remains at the [H] level (remains a lock signal). On the other hand, as in case ■, fR and f
When the phase difference of v is large and exceeds the normal frequency fluctuation due to FM modulation, specifically, when the rising edge of the signal Xin/8 is captured twice or more, the D flip-flop 28.2
The outputs of each stage of the shift register 9 become [H], and the signal S changes from (H) to [L]. Therefore, the D flip-flops 30 to 32 are reset and the signal S becomes (HE), and the output S11 of the unlock detector 42 changes from [H] to [L] and becomes an unlock signal. The degree of phase shift between fR and fv depends on the number of stages of the shift register composed of D flip-flops 28 and 29 and the clock frequency of the shift register (X
It can be adjusted by changing (in/8).

In this way, in this embodiment, when f8 and fv are locked, even if FM modulation is applied to VCO4 and the oscillation frequency fluctuates, unlike the conventional example, an unlock signal is not output, and the locked state is properly maintained. can be maintained to ensure normal FM transmission.

Note that although the above embodiment is an example in which the present invention is applied to an FM transmitter equipped with a PLL, the application of the present invention is not limited to this. That is, it is not only applicable to lock detection circuits used in PLLs, such as audio equipment, televisions, wireless communication equipment, motor control, etc., but also to other lock detection circuits not used in PLLs. Applicable.

〔effect〕

According to the present invention, when the phase difference between the reference signal and the comparison signal is in the locked state, if the phase difference is within a predetermined range, the lock signal is continued to be output, and if it is outside the predetermined range, the unlock signal is output. Therefore, even if the oscillation frequency changes within the normal range due to FM modulation, for example, an unlock signal will not be output and the locked state will be maintained appropriately. Further, when the − degree unlocked state is detected, the lock signal is not output unless the phase synchronization state is maintained while the first detection means counts Xin a predetermined number of times.

Therefore, in various devices equipped with the lock detection circuit according to the present invention, the stability of frequency control can be improved by avoiding the output of erroneous lock signals due to detection of unnecessary unlock states and detection of pseudo phase synchronization. can be ensured.

[Brief explanation of the drawing]

Figures 1 to 3 show an F to which the lock detection circuit according to the present invention is applied.
FIG. 1 is a circuit diagram of the lock detector, FIG. 2 is a timing chart when the M transmitter is in the locked state, and FIG. 3 is when the transmitter is in the unlocked state. Fig. 4.5 is a diagram showing an example of an FM transmitter to which a conventional lock detection circuit is applied, Fig. 4 is a block diagram thereof, and Fig. 5 is an example of a conventional lock detector. FIG. 1...Reference oscillator, 2...Reference frequency divider, 3...Phase comparator, 4...VC○, 5... Comparison frequency divider, 6... Lock detector, 7... FM transmitting unit, 8... Charge pump, 9... L P F, 21. ...Lock detector, 22-25... Nantes gate, 26.27...
...Inverter, 28-32...D flip-flop, 41...
...First detection means, 42... Unrotter detection means, 43...
-Second detection means.

Claims (1)

[Claims] a first detection means for receiving a signal having a pulse width corresponding to a phase difference between the reference signal and the comparison signal from a phase comparator and detecting that the pulse width is within a predetermined range; an unlock detecting means for outputting an unlock signal when the pulse width exceeds the predetermined range; and a second unlock detecting means for outputting a lock signal when the pulse width remains within the predetermined range for a predetermined time while outputting the unlock signal. A lock detection circuit comprising: a detection means;