JPH01126752A - Control system for duplexing system - Google Patents

Abstract

PURPOSE:To improve a processing speed and reliability by equipping a data storage, which is commonly accessable, to respective two systems. CONSTITUTION:In respective high order devices 10A and 10B of two systems #A and #B, >=1 data storages 12A and 12B are provided to be accessable from a self-system and the other system. When the parallel operation of the both systems #A and #B is established, the data of the system to start the operation at first, for example, the data of the data storage 12A of the system #A are read, transferred and stored to the data storage 12B of the other system #B. Then, in such a condition, the common data of the systems #A and #B are stored to the both data storages 12A and 12B. After that, when the writing of the data is executed by CPUs 10A and 10B of the respective systems #A and #B, this data writing is commonly executed to the both data storages 12A and 12B and a data sharing is maintained in the data storages 12A and 12B.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a control method for a redundant system in which common data is stored in the data storage devices of two systems so that they can be accessed mutually, without affecting processing speed, and while reducing the power supply and installation location. The purpose of this system is to easily realize non-stop operation without any need for consideration, and each of the host devices of the two systems is equipped with at least one or more data storage devices that can be accessed from the own system and other systems, and the operation of both systems is controlled. When the system is started, the data in the data storage device of the system that first started operation is read and transferred to and stored in the data storage device of the other system, and after that, the data of each system is written in common to both data storage devices. Configure.

[Industrial Application Field] The present invention relates to a control method for a duplex system in which common data is stored in the data storage devices of two systems so that they can be accessed mutually.

In recent years, with the spread of computer systems, when a system stops, it has a severe impact not only on users but also on society, and for this reason, there is a strong demand for non-stop computers.

When considering system redundancy as a way to realize such a non-stop computer, the CPLI and data storage device are installed in two systems, one system is normally operated, and in the event of a system error or system down during operation, A redundant system is known that switches to the operation of another system that is on standby.

However, since it is disadvantageous in terms of running costs to have two systems and keep one in standby as a backup, in recent years two systems with different control processes have been introduced.
A redundant system has been proposed in which a data storage device that can be accessed in common from the system systems is provided to commonly store data used by the CPUs of each system.

[Prior Art] FIG. 9 is a block diagram of a conventionally considered duplex system in which data storage devices can be commonly accessed.

In FIG. 9, systems #A and #B are each provided with CPU10A and IOB as host devices, and each has a channel CH and an input/output interface I1.
Appropriate external devices are connected via 0. System #A
and #B, a data storage device 12 is provided as an independent unit, and the data storage device 12 has a system #B.
Data used in A and #B are stored in common, and can be mutually accessed from the CPU 10A or IOB under the control of memory control units 14A and 14B provided in each system.

[Problems to be Solved by the Invention] However, in such a conventional duplex system, while one system is accessing the data storage device, the other system cannot access it, which may slow down the processing speed. In addition, considering maintainability, the data storage device 1
2 is housed in a separate socket, this requires a dedicated power supply for the data control device, which increases costs and requires additional installation space.

The present invention was made in view of these problems, and
It is an object of the present invention to provide a control method for a duplex system that can easily share a data storage device and realize non-stop operation without affecting processing speed or considering power supply or installation location.

[Means for solving problems] FIG. 1 is a diagram explaining the principle of the present invention.

In Figure 1, there are two systems: Et'A, -1t
At least one or more data storage devices 12A, 12B that can be accessed from the mountain system and other systems are provided in each of the host devices 10A, 10B of -B.

When parallel operation of both systems #A and #B is established, data from the data storage device 12A of the system that started operation first, for example, system #A, is read and transferred to the data storage device 12B of the other system #B. In this state, system #A is stored in both data storage devices 12A and 12B.
The state is such that the common data #B is stored.

After that, the CPUs 10A and 10 of each system #A and #B
When B writes data, this data writing is performed commonly to both data storage devices 12A, 12B, and data sharing in the data storage devices 12A, 12B is maintained.

[Effect] By making the data storage devices of two systems accessible from the own system and other systems, when both systems start operating, the data in the data storage device of the system that started operating first can be accessed later. It is transferred and stored in the data storage device of the system that has started operation (copy operation), thereby establishing the operational state of the duplex system in which common data is stored in the two data storage devices, and subsequent data writing will be performed on both data storage devices. Since this is done commonly for storage devices, the operational status of the duplex system can be maintained.

If one of the systems goes down, the normal system can maintain the minimum necessary functions of the down system by accessing the data storage device that stores common data, so-called non-stop operation. A computer can be realized.

In addition, since each system is equipped with a data storage device, processing is executed by accessing the own system's data device during normal operation, so there is no negative effect on processing speed, and the data storage device is stored in a locker for each system. There is no need to secure a separate installation location, and it is only necessary to add a system configuration that makes it accessible from other systems and white systems, so the system can be easily customized. In particular, in recent years, the degree of integration of memory elements themselves has improved significantly, and even if the storage capacity of the data storage device of each system is increased to the extent that common data can be stored, the cost is still lower than that of conventional systems. There is no significant difference, and there is no practical problem.

[Example] FIG. 2 is a block diagram showing one embodiment of the present invention.

In FIG. 2, the duplex system of the present invention is composed of system #A and system #B, and system -tl:A,
Each #B has a CPU 10A as a host device,
10B is provided. CPtJloA.

10B are connected to main storage devices 16A, 16B, and channel adapters 18A, 18B for connecting appropriate external devices via input/output interfaces. Furthermore, data storage devices 12A and 12B are connected to the CPUs 10A and 10B, respectively, and the data storage devices 12A and 12B are connected to the memory control devices 22A and 22B connected via the other system interface 20 and the shared memory 2.
4A.

Equipped with 24B.

FIG. 3 shows the line configuration of the other system interface 20 that connects the memory control devices 22A and 22B in FIG. A control line L5 is provided.

Here, the memory control devices 22A and 22B are devices that control the mountain system shared memories 24A and 24B and the other system interface 20, respectively, and the CPUs 10A and 10B.
It has the functions of interrupting, copying data from the shared memory of the other system to the shared memory of the white system (copy operation), and connecting and disconnecting the interface 20 of the other system (connect operation and disconnect operation).

Further, the shared memories 24A and 24B are memories having a storage capacity for storing common data of the system #A and the system #B, and are in a predetermined common data storage state in the initial state.

Next, the control processing of the duplex system shown in the embodiment of FIG. 2 will be explained with reference to FIGS. 4A and 48.

Note that FIGS. 4A and 4B take as an example a case where system #A starts operating first, and then system #B starts operating.

In FIG. 4A, when the system #A starts operating by turning on the power, after the initial processing routine IPL is completed by the program #A, the program #A issues a connect operation to the memory control device 22A. Perform system start-up processing. Upon receiving this connect operation, the memory control device 22A turns on the CNCT line L1 of the other system interface 20, and
Subsequently, program #A checks for a certain period of time whether or not the CNCT line L2 is turned on by the memory control device 22B of system #B via the memory control device 22A. At this time, since system #B has not started up, CNCT line L2 is off, and program #A
detects that the CNCT line L2 is turned off, it initiates a disconnect operation from the memory controller 22.
Issued to A, the CNCT line L1, which was turned on once, is turned off again and the own system starts operating.

In the white operation state using this program #A,
Data writing and data reading are performed only to the mountain storage memory 24A.

At a certain point after the system #A has started up in this way, when the system #B starts up by turning on the power (power-on), after similarly executing the initial processing routine IPL according to the program #B, the memory control unit 22B Issues a connect operation to notify that the system has started up. The memory control device 22B turns on the CNCT line L2 of the other system interface 20, and then the program #B turns on the memory control device 22 of the system #A.
It is monitored for a certain period of time whether or not the CNCT line L1 from A is line segment 1.

On the other hand, when program #A of system #A detects that the CNCT line L2 from memory control device 22B of system #B is turned on during operation, it issues a connect operation to memory control device 22A, and 2
2A is the CNCT line L1 line piece 1 of the other system interface 20. At this time, program #A can recognize that system #B has started up.

Program #B is the CNCT from the memory control device 22A.
When detecting that the line L1 becomes line segment 1, it issues a copy operation to the memory control device 22B. When the memory control device 22B detects the copy operation, it uses the data bus L3 of the other system interface 20 to read the contents of the common memory 24A through the memory control device 22A of the system #A, and stores them in the common memory 24B of its own system. Of course, during the copy operation by program #B, program #A uses the common memory 24B of its own system.
Since new data may be written to the system #B, the data writing in this case is also commonly performed to the shared memory 24B of the system #B through the other system interface 20.

Subsequently, as shown in FIG. 4B, the memory control device 22B
When the copy operation is completed, program #A is notified of the end of the copy operation, and at this point, system #A and system #B are using the shared memory 24A.
, 24B are stored with duplicated common data.

When program #A or program #B writes data after such a copy operation is completed, both shared memories 24A.

As a result, it is possible to maintain the dual storage state of the shared data in the shared memories 24A and 24B.

FIG. 5 shows a processing operation when system #A goes down due to a failure while system #A and system #B are in operation in the embodiment shown in FIG.

In FIG. 5, when system #A goes down, the CNCT line L1 from the memory control device 22A becomes line segment 1, and system #B is notified of the system down of system #A. When program #B detects the CNCT line L1 line segment 1, it issues a disconnect operation to the memory control device 22B of its own system, turns off the CNCT line [2, and accesses only the shared memory 24B of its own system. to move to. Furthermore, the system #B that has detected the system #A going down uses the data stored in the shared memory 24B to perform the minimum functions necessary for the operation of the down system #A.

Therefore, after system #B transitions to an independent operating state, if you turn off the power to system #A, replace the faulty device, and start system #A again, the system will start up as shown in Figure 4A. Through the copy operation in the sequence, operation as a redundant system is started again.

FIG. 6 is an explanatory diagram showing a specific example of the system-down memory control device 22A in the example of FIG. 2.

In FIG. 6, the memory control device 22A includes a microcontroller 30 that performs overall control of the memory control device 22A.
A. A higher-level device interface control unit 34A that controls the interface 32A with the higher-level device; a transfer control unit 36A that controls the transfer of the own system and other systems; It is composed of a self-system CM control section 40A that writes or reads data, and an other-system control section 42A that controls data transfer with the other-system memory control device 22B through the other-system interface 20.

Incidentally, the bus control line in the other system interface 20 is as follows:
It is composed of a bus black line L50 and a bus busy line L52.

Next, data transfer processing in the memory control device 22A of FIG. 6 will be described with reference to FIGS. 7A and 7B.

First, in step S1, the microcontroller 30A monitors the presence or absence of a data transfer request from the host device, and upon receiving a data transfer request from the host device, proceeds to step S2.
The microcontroller 30A recognizes a data transfer activation request (P-RQ) from the host device interface controller 34A. Subsequently, in step S3, the microcontroller turns on the transfer mode (TEXEC>) of the transfer controller 36A.

In the next step S4, it is determined whether it is a write transfer or not.
If it is a write transfer, the process advances to step S5, where the transfer control section 36A turns on a data transfer request (TRQ) to the host device to the host device interface control section 34A, and the process advances to the next step S6. In step S6, the higher-level device interface control unit 34A detecting that the data transfer request (TRQ> is turned on) goes to fetch data from the higher-level device, and notifies the higher-level device of completion of data fetch (TEND).

In step S7, the host device interface control unit 34
The transfer control unit 36A that detected (TEN+)) from A outputs the other system transfer request (AN-REQ>) to the other system control unit 42A. The system control unit 42A checks the CNCT lines L1 and L2 in step S8.

If both systems are in operation at this time, the CNCT
Since the lines Ll and 12 are in the on state due to the connect operation, it is determined in step S9 that both the lines are on, and the process proceeds to the next step SIO, where the other system control unit 42A sets (BusBUSY) to the bus busy line L52. and acquires the other system data bus L3.

Subsequently, the other system control unit 42A transfers the write data from the host device obtained by the transfer control unit 36A to the other system memory control device 22B in step S11.

When it is determined in step S12 that the data transfer to the other system has ended, the process proceeds to step S13, where the transfer control unit 36A (A
N-END) and proceeds to step S14 in FIG. 7B. In step S14, the transfer control unit 36A that has detected (AN-END) turns on (SLFREQ) for its own CM control unit 40A.

Mountain-based commercial where (SLFREQ) was detected in step 815
The control unit 40A notifies the 0M24A of the access start.

That is, (CMRQ) is turned on.

In the next step 316, it is determined whether or not it is a write transfer, and since it is a write transfer at this time, step 3
Proceeding to step 17, the mountain CM control unit 40A detecting the ON state of (CMRQ) issued in step 811 transfers and writes all data to 0M24A.

When 0M24A completes data writing in the next step S18, it notifies (CMEND> to its own CM control unit 40A. The mountain CM control unit 40A, which detected (CMEND>
Notify. The transfer control unit 36A that has detected this (SLFEND) determines in step 320 whether or not to continue the transfer.

When it is determined in step 820 that the transfer is to be canceled, the transfer control unit 3
6A turns off the transfer mode (TEXEC> set by the microcontroller 30A in step S22, and
After the transfer is completed, the microcontroller 1 section 30A that has detected the off state of EXEC) notifies the host device in step S23 through the host device interface control section 34A, and again requests data transfer from the new host device as shown in step S1 of FIG. 7A. Return to standby state.

On the other hand, when read transfer is determined in step S4 of FIG. 7A, the transfer control unit 36A turns on a local request (SLFREQ) to the local CM control unit in step S24, and proceeds to step S15 of FIG. 7B. Step S
The mountain CM control unit 40 detects (SLFREQ) at 15.
A notifies C'M 24A of the start of access, and in the next step 816 read transfer is determined and the process proceeds to step 325.

0M24A that detected (CMRQ) is the self-system CM control unit 4
Transfer the read data to 0A, and at the end of the transfer (CMEND>
Notify. In step 826, the self-system CM control unit 40A sends the successive data received from the 0M24A to the transfer control unit 36A, and upon detection of (CMEND>, notifies (SLFEND>).

In the next step 827, the transfer control unit 36A that has detected (SLFEND) turns on (TRQ) for the host device interface control unit 34A, and the next step 3
At step 28, the higher-level device interface control section 34A detects that (TRQ) is turned on and transfers the successive data from the transfer control section 36A to the higher-level device, and notifies the transfer control section 36A of (TEND) when the transfer is completed.

The transfer control unit 36A detecting (TEND) takes step 3.
In step S29, it is determined whether or not to continue the transfer, and as in the case of write transfer, the process proceeds to step S21, where it is determined whether or not to continue the transfer. When it is determined in step 321 that the transfer has ended, step 3
In step 22, the transfer control unit 36A turns off the transfer mode (TEXEC), and in the next step 323, the microcontroller 30A detecting the off state of (TEXEC) notifies the host device of the end of the transfer through the host device interface control unit 34A. The process returns to the standby state of step S1 again.

On the other hand, in either write transfer or read transfer, if it is determined in step 321 that the transfer should be continued, the process returns to step S4 in FIG. 7A to repeat the write transfer or read transfer process.

8A and 8B show the processing operation of the copy operation in the memory control device 22A of FIG.
A case is shown in which a copy operation is performed from the memory control device 22B to the memory control device 22A.

In FIG. 8A, first, in step S1, the presence or absence of a copy processing request from the host device is monitored, and when a copy processing request is received, the process proceeds to step S2, and the microcontroller 30A
detects a copy processing request (P-RQ) from the host device interface control unit 34A and recognizes the copy operation. Subsequently, in step S3, the microcontroller 3
0 turns on the copy control line L4 of the other system control unit 42A.

Subsequently, in step S4, the microcontroller 30A turns on an other-system read request (M-ANRQ) to the other-system controller 42A. In step S5, the other system control unit 42A
Line L1. Check L2, and if both systems are in a normal operating state, the CNCT line L'l and L2 are in the on state, so it is determined in step S6 that both lines are on, and the process proceeds to step S7. On the other hand, in step S6
If both the NCT lines Ll and L2 are not in the ON state, the process advances to step S22, where the host device is notified that the copy operation has ended abnormally, and the process returns to the standby state of step S1 again.

When proceeding to step 7 because both CNCT lines L1 and L1.12 are on, the other system control unit 42A turns on (BLJS BU
SY) to the bus busy line L5 to connect to the other system data bus L.
Get 3.

Subsequently, in step S8, the other-system control unit 42A requests data transfer from the other-system memory control device 22B.

The other-system control unit 42B of the memory control device 22B that received this data transfer request transfers the data to the own-system CM control unit 40 in step S9.
Turn on the other system transfer request (AN-CMRQ) for B. Self-system CM control unit 4 that detected this (AN-CMRQ)
0B is sent to white CM24B (CMRQ) in step S10.
-ON) is sent.

(The CM24B detecting CMRQ-ON>
Read the data with 1'l and send the continuous data to the mountain commercial.
The data is sent to the control unit 40B, and upon completion of the sending, it is notified (CMEND>) and the process proceeds to step S12 in FIG. 8B.

In step 812, the mountain CM control unit 40B sends the read data to the other system control unit 42B, and when receiving (CMEND), turns on (AN-CMEND>).

In the next step 313, the other system control unit 42B that detected (AN-CMEND) sends data to the other system control unit 42A of the memory control device 22A through the data bus L3, and when the data transmission is finished, turns on (BUSEEND). do. When the other system control unit 42A detects that this (BUSEEND) is turned on, the micro control unit 30
Turn on M-ANEND> for A. Step S1
5, the microcontroller 3.OA detects the ON of (M-ANEND> from the other system control unit 42A).
(M-3LFRQ
) makes a write request to turn on.

In step 316, (M-3LF
The mountain CM control unit 40A detects the ON of 0M
CMRQ) for 24A and sends write data. The 0M24A that detected this (CMRQ) writes the data to the memory in step 317, and when the writing is completed, the mountain range C
CMEND> is sent to the M control unit 40A. The self-system CM control unit 40A that detected this (CMEND>
END). The microcontroller 30A that has detected (M-8LFEND) determines whether or not to continue the copy operation in step S19, and when it is determined in step 320 that the copy operation has ended, step 821
After the copying is completed, the microcontroller 30A notifies the higher-level device through the higher-level device interface control unit 34A,
The process returns to the standby state of step S1 in FIG. 7A again.

On the other hand, if it is determined in step S20 that copying should be continued, the process returns to step S4 in FIG. 8A, and the same copying operation is repeated.

Furthermore, Figures 8A and 8B show the memory control device 2 of system #B.
Although the case where data is copied from 2B to the memory control device 22A of system #A is taken as an example, a similar copy operation is also performed when data is copied from the memory control device 22A to 22B. is easy to understand.

[Effects of the Invention] As explained above, according to the present invention, since each of the two systems is provided with a data storage device that can be accessed in common, there is no need to store the data storage device in a separate box. There is no need for a separate power supply or installation location.
Since it is only necessary to make the data storage devices of each system mutually accessible, a duplex system can be realized with a simple configuration.

In addition, since two data storage devices storing common data are provided, even if one system goes down, redundant operation can be continued using the normal data storage device, improving reliability by realizing a non-stop computer system. can be significantly improved.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment, Fig. 3 is an explanatory diagram of the line of the other system interface, Fig. 4A,
Figure 4B is an operation flow diagram at system startup, Figure 5 is an operation flow diagram at system down time, Figure 6 is an explanatory diagram of an embodiment of the memory control device, and Figures 7A and 78 are data transfer operation flow diagrams of the memory control device. , FIG. 8 is a copy operation flow diagram of the memory control device, and FIG. 9 is an explanatory diagram of a conventional system. In the figure, 10A, 10B: host device (CPU) 12A, 12B: data storage device 16A, 16B: main storage 18A, 18B: Channel adapter 20: Other system interface 22A, 22B: Memory control device 24A, 24B: Shared memory 30A: Micro control section 32A: Upper device interface 34A: Upper device interface control section 36A: Transfer control section 38A: 0M interface 40A: Own system CM control unit 42A: Other system control unit

Claims (1)

[Claims] At least one of the host devices (10A) and (10B) of the two systems is accessible from the own system and the other system.
The above data storage devices (12A) and (12B) are provided, and when the operation of both systems is started, the data in the data storage device of the system that started operation first is read and transferred and stored in the data storage device of the other system. A control method for a duplex system characterized in that, after the transfer and storage, data writing of each system is performed in common to both data storage devices (12A) and (12B).