JPH01106227A - Data processor with branching forecasting function - Google Patents

Abstract

PURPOSE:To forecast branching even when the branch can not be forecasted by history by adding a 2nd branch forecasting means for forecasting whether branching is generated or not from a branching condition of an instruction decoded by an instruction fetching/decoding means. CONSTITUTION:A branching forecasting mechanism 20 independent of the history fetches a 4-bit branching condition code '0000' from a branching condition code register 7 and determines a signal to be outputted to the 2nd branching forecasting signal line 24 from the pattern of the branching condition code. The code '0000' is set up so as to forecast the generation of branching. When a signal from a branching forecast disabling signal line 23 is in an ON state, a selector 21 selects the 2nd branching forecasting signal line 24. Consequently, the generation of a branching can be forecasted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device having a branch prediction function, and in particular has a pipeline mechanism, and when decoding an instruction,
The present invention relates to a data processing device having a branch measuring function for predicting whether or not to take a branch.

[Prior Art] Computer instructions can be broadly classified into non-branch instructions, unconditional branch instructions, and conditional branch instructions. A conditional branch instruction is an instruction that causes a branch if a certain condition is met, and is an obstacle to increasing the speed of pipelined computers. In other words, in a pipelined computer, a branch instruction is executed in the instruction execution unit, and when a branch actually occurs, the instruction being processed in the pipeline at that point is canceled and a new branch destination instruction is fetched. . This creates gaps in the flow of the pipeline, resulting in turbulence in the pipeline.

Therefore, a branch prediction method is adopted that predicts whether or not to branch when a conditional branch instruction is given. This branch prediction method is described in the Institute of Electrical and Electronics Engineers (IEE).
E) Computer Subcommittee (COMPUTERSOCI)
"COMPUTE" published by ETY
R) J January 1984 issue.

FIG. 5 is a schematic block diagram of a conventional data processing device having a branch measurement function. First, with reference to FIG. 5, the configuration of a conventional data processing device having a branch p4-1 function will be described. The instruction register 1 stores instructions output to the data bus. The instructions stored in the instruction register 1 are given to the instruction decoder 2. The instruction decoder 2 decodes instructions and outputs calculation instruction signals and branch displacements (
If the instruction is a conditional branch instruction or an unconditional branch instruction, it outputs the instruction length of the decoded instruction. The execution mechanism 3 executes an instruction based on an operation instruction signal outputted as a result of the instruction being decoded by the instruction decoder.

The branch prediction mechanism 4 stores branch prediction bits corresponding to the addresses of instructions. This branch al bit is
This is to predict whether a branch will occur when an instruction is executed. Then, when the instruction is decoded, the branch prediction mechanism 4 reads the branch r prediction bit from the address corresponding to the instruction and supplies it to the comparator 5 and the next fetch instruction address designation section 6. When a branch is predicted and a branch is executed, the comparator 5 compares the prediction result based on the branch prediction bit with the execution result by the execution mechanism 3- of the conditional branch instruction predicted to take a branch, and determines that they do not match. At this time, a branch prediction failure signal is given to the next fetch instruction address specifying unit 6.

When the comparator 5 determines that the branch prediction has failed, the next fetch instruction addressing unit 6 reads the instruction in the correct direction from the memory based on the branch prediction failure signal. The next fetch instruction address specifying unit 6 includes an adder 61, a decoding program counter 62, and a save register 63. The adder 61 adds the instruction length to the contents of the decoding program counter 62 each time an instruction is executed, and outputs the address signal of the next instruction to be fetched. The next fetch instruction address specification unit 6 is a branch prediction mechanism 4
When a branch prediction bit is given from , address data of a decoding program counter 62 is saved in a save register 63, and an adder 61 adds the branch displacement to the address data counted by the decoding program counter 62.

The reason why the address data of the decoding program counter 62 is saved in the save register 63 is that if branch prediction fails, the saved address data is loaded into the decoding program counter 62 again and the instruction length is added to the address data. This is for fetching the instruction at the next address.

FIG. 6 is a relationship diagram showing the relationship of addresses in the memory to explain the function of the branch 7Tl11. Next, the fifth
A conventional branching element a1 method when a conditional branch instruction is given will be described with reference to the drawings and FIG. Address data from the decoding program counter 62 is output as an address signal to the address bus, and an instruction is read from an address in a memory (not shown) and loaded into the instruction register 1.

This instruction is decoded by the instruction decoder 2, and an operation instruction signal and instruction length are output. The execution mechanism 3 executes processing operations based on the calculation instruction signal.

On the other hand, the adder 61 adds the instruction length decoded by the instruction decoder 2 to the contents of the decoding program counter 62, and outputs the address signal of the next instruction to be fetched to the address bus. If the address signal output from the decoding program counter 62 corresponds to a conditional branch instruction, the branch a1 bit stored corresponding to a part of the address is read out and the next fetch instruction address is read out. It is given to the designation section 6. If the instruction is predicted to branch, and as a result of decoding the instruction, it is found that it is a conditional branch instruction, the next fetch instruction address specification unit 6 determines that the instruction will branch, and decodes the instruction. The contents of the program counter 62 are saved in the save register 63. Then, the adder 61 adds the branch displacement decoded by the instruction decoder 2 to the contents of the decoding program counter 62.

That is, as shown in FIG. 6, the branch displacement is added to the address a of the conditional branch instruction, and an address signal indicating the branch destination address a+b is output. Based on this address signal, the branch destination instruction is read from the memory.

On the other hand, the execution mechanism 3 executes a conditional branch instruction, which branches if a certain condition is met, but does not branch if the condition is not met. For example, when executing a conditional branch instruction that has a condition of branching if the 2 (zero) flag is set, the branch will be taken if the Z flag is set, but the branch will not be taken if the 2 flag is not set. When the execution mechanism 3 executes the conditional branch instruction and the branch is not taken, an execution result signal indicating that the branch is not taken is given to the comparator 5. Since this comparator 5 is given the branch ilN information from the branch a-1 mechanism 4, the comparator 5 determines that the two do not match and sends the branch prediction failure signal to the next fetch instruction address designation section. Give to 6. If the next fetch instruction address designation unit 6 does not branch as a result of executing the conditional branch instruction, the next fetch instruction address specifying unit 6 selects the next address a+ of the conditional branch instruction shown in FIG.
It is necessary to execute the instruction c. However, as described above, when the conditional branch instruction branches, the decoding program counter 62 outputs an address signal indicating the address a and the branch destination. For this reason, the next fetch instruction address designation unit 6 uses the decoding program counter 6.
2 is canceled and the original address a saved in the save register 63 is read out and loaded into the decoding program counter 62. Further, the adder 61 adds the instruction length C to the contents of the decoding program counter 62, and outputs an address signal indicating the address a+c. Thereby, the instruction corresponding to address a+C is read from the memory and executed by the execution mechanism 3.

[Problems to be Solved by the Invention] A conventional data processing device that performs a branch prediction function is configured as described above, so when a branch prediction fails, the address saved in the save register 63 is saved. This requires processing to transfer the address to the decoding program counter 62 and add the instruction length to the address, resulting in a problem that the processing becomes complicated.

Therefore, some of the inventors of the present invention invented a data processing device that solved such problems, and the applicant has filed a patent application in 1983.
No. 1-200557 and Japanese Patent Application No. 204500, and the US application was filed on August 26, 1987, claiming priority to those Japanese applications. The subject matter disclosed in that application is discussed below as prior art to the invention of the present application.

FIG. 3 is a schematic block diagram showing one embodiment of this prior art. First, refer to Figure 3 and use the branch prediction function.
The configuration of the data processing device will be explained. In Fig. 3, instruction register 1, instruction decoder 2, and execution mechanism)
The same branch prediction mechanism 4, adder 61, and decoding program counter 62 as shown in FIG. 5 are used. The register 10 is used to load the instruction length of the instruction decoded by the instruction decoder 2, and the register 11 is used to load the branch displacement or instruction length of the instruction decoded by the instruction decoder 2. The register 11 is loaded with a branch displacement when the instruction is an unconditional branch instruction or a conditional branch instruction, and loaded with an instruction length when the instruction is a non-branch instruction.

Based on the branch prediction bits read from the branch prediction mechanism 4 and information on whether the instruction is a non-branch instruction, an unconditional branch instruction, or a conditional branch instruction, the selector 12
The output of the register 10 and the output of the register 11 are switched. That is, when a non-branch instruction or a conditional branch instruction that is not predicted to branch is read, the output of the register 10 is selected and the instruction length is given to the adder 61, and an unconditional branch instruction or a conditional branch instruction that is predicted to branch is selected. When a conditional branch instruction is read out, the output of the register 11 is selected and the branch displacement is given to the adder 61.

The output of the instruction decoder 2 includes a branch condition code register 7.
and register 13 and register 14 are connected. The branch condition code register 7 loads the branch condition code of the conditional branch instruction decoded by the instruction decoder 2. Register 13 similarly loads the branch displacement of a decoded unconditional branch instruction or conditional branch instruction, or the instruction length for a non-branch instruction, and register 14 loads the instruction length of the decoded instruction. register 13 and register 1
Each output of 4 is given to selector 15.

The selector 15 selects the output of the register 13 and the output of the register 14 based on the branch prediction bit of the branch prediction mechanism and information on whether the instruction is a non-branch instruction, an unconditional branch instruction, or a conditional branch instruction. Switch. In other words, if the instruction is a non-branch instruction, a conditional branch instruction that is not predicted to branch, or an unconditional branch instruction, it is a conditional branch instruction that selects the data loaded into the register 13 and is predicted to branch. If so, select the instruction length loaded into register 14. The output selected by this selector 15 is given to the execution mechanism 3.

The branch condition code register 7 consists of 4 bits, the upper 3 bits represent the branch condition, and the lowest 1 bit represents whether to branch when the branch condition is met or not. . For example, 00
00 indicates that the Z (zero) flag is established, that is, a branch occurs when the result of the operation becomes 0, whereas 0001 indicates that the
If the flag is not established, that is, the result of the operation is not 0, it indicates that the process will branch. The output of the least significant bit of this branch condition code register is applied to the selector 9, and is also inverted by the inverter 8 and applied to the selector 9.

The selector 9 selects the least significant bit of the branch condition code register 7 in the case of a conditional branch instruction that is not predicted to branch, and selects the output of the inverter 8 if it is a conditional branch instruction that is predicted to branch. It is selected and given to the execution mechanism 3.

In the case of a non-branch instruction or an unconditional branch instruction, what kind of data is in the branch condition code register? The execution mechanism 3 ignores this data.

FIG. 4 is a flowchart for explaining the specific operation of an embodiment of this prior art. Next, Figures 3 and 4
The specific operation of this embodiment of the prior art will be described with reference to FIG. 6 and FIG. First, in the same manner as in the conventional example, the contents of the decoding program counter 62 are outputted as an address signal to the address bus, and an instruction is read from an address in a memory (not shown) to the instruction register 1.
loaded into. The instruction loaded into the instruction register 1 is decoded by the instruction decoder 2, an operation instruction signal is given to the execution mechanism 3, and the instruction length of the decoded instruction is loaded into the register 10 and the register 14. The execution mechanism 3 performs execution processing based on the given calculation instruction signal. At the same time, the adder 61 adds the instruction length or branch displacement selected by the selector 12 to the contents of the decoding program counter 62, and outputs an address signal indicating the position of the next instruction to be executed. Based on this address signal, the next instruction to be executed is read from the memory and loaded into the instruction register 1.

Next, it is assumed that a conditional branch instruction having a branch condition code "0000" is read from the memory. Branch condition code “
0000" means that a branch will occur if the Z (zero) flag is set. When this instruction is read, the instruction is decoded and found to be a conditional branch instruction. If the branch prediction bits stored in the branch prediction mechanism 4 corresponding to the upper 8 bits of the address indicate a branch, the selector 12 selects the output of the register 11, and the selector 15 selects the output of the register 14. The selector 9 selects the output of the inverter 8.The selector 12 selects the output of the register 11, so the adder 61 uses the contents of the program counter 62 for decoding the branch displacement shown in FIG. As a result, an address signal indicating the branch destination address a +, b of the conditional branch instruction is output.
Then, the next instruction to be executed is read from the branch destination of the conditional branch instruction on the memory. That is, in a non-branch instruction or a conditional branch instruction that is not predicted to branch, the instruction length C loaded in the register 10 is
1 is added to the contents of the decoding program counter 62. However, in the case of an unconditional branch instruction or a conditional branch instruction predicted to branch, the branch degree 'loaded to the register 11 is added to the contents of the decoding program counter 62. is added to the contents of the decoding program counter 62. On the other hand, the selector 15 sets the instruction length C of the register 14 in the case of a conditional branch instruction that is predicted to branch, and in the case of a non-branch instruction, an unconditional branch instruction, or a conditional branch instruction that is not predicted to branch. Select the output of register 13. In this way, if the decoded instruction is a conditional branch instruction that is predicted to branch, the instruction length and branch displacement are swapped by the swapping mechanism. Here, the switching mechanism is register 10.11.13.14 and selector 12, 1.
It is a conceptual mechanism that includes 5.

Further, the branch condition code "0000" of the instruction decoded by the instruction decoder 2 is stored in the branch condition code register 7.
loaded into. In this case, since a branch is predicted, the upper 3 bits of the branch condition code register 7 are given to the execution unit 3, and the lower 1 bit is inverted by the inverter 8 and sent to the selector 9. It is given to the execution mechanism 3 via the In other words, the branch condition code “
The least significant bit of 00001 is inverted by the inverter 8 and sent to the execution mechanism 3 as the branch condition code '0001'.
You will be saved. This indicates that the process will branch if the Z flag is not set.

The execution mechanism 3 has an adder and a program counter (not shown), the program counter specifies the address a of the conditional branch instruction, and the adder specifies the instruction length C loaded into the register 14 to the program counter. to add.

On the other hand, the instruction to be executed following the conditional branch instruction is read from the memory and loaded into the instruction register 1. In this case, the conditional branch instruction is predicted to branch, and instruction register 1 contains address a+b on memory.
instructions are loaded. If the Z flag is not set in execution mechanism 3, the branch condition code is “0001”.
A conditional branch instruction with a branch position and instruction length C is executed by the execution unit 3, causing a branch to address a+C. This means that the original prediction that a branch would occur in response to a conditional branch instruction was incorrect.

As a result, the instruction located at address a~C on the memory that had been loaded into the instruction register 1 is canceled, the instruction at address a~C on the memory is read out, and this instruction is loaded into the instruction register 1.

On the other hand, if the Z flag is set in the execution mechanism 3, the conditional branch instruction with the branch condition code "0001" will not branch even if executed by the execution mechanism 3. This means that the aPI that caused a branch in response to the original conditional branch instruction was correct as a result.

As a result, the instruction located at address a+b on the memory that had been loaded into the instruction register 1 is valid and is transferred as is to the instruction decoder 2 and execution mechanism 3 for processing.

Note that when a non-branch instruction located at address a on the memory is read, it is loaded into the instruction register 1, decoded by the instruction decoder 2, and if it is found to be a non-branch instruction, the branch prediction mechanism Execute branch Ta1ll at 4 and branch? 'No matter what value the ilF+ bit indicates,
The instruction length C is added to the decoding program counter 62, the decoding program counter 62 points to address a+C, and following this non-branch instruction, the instruction at address a+C on the memory is read.

Furthermore, when an unconditional branch instruction located at address a on the memory is read, it is loaded into the instruction register 1 and decoded by the instruction decoder 2, and if it is found to be an unconditional branch instruction, Branch r with branch prediction mechanism 4
No matter what value the branch prediction bit indicates, the branch displacement value is added to the decoding program counter 62, the decoding program counter 62 points to address a+b, and following this unconditional branch instruction, the branch displacement is added to the decoding program counter 62. The instruction at the upper address a is read out.

As mentioned above, by using the branch prediction function,
By determining conditional branch instructions that are likely to branch at the pipeline decoding stage and branching before the instructions are executed, it is possible to reduce pipeline disturbances caused by branch instructions and improve processing efficiency.

Further, according to the prior art as described above, when a conditional branch instruction is predicted to branch, the inverter 8 inverts the least significant bit of the branch condition code of the conditional branch instruction,
The branch displacement and instruction length are exchanged and executed by the execution mechanism 3.

By doing so, even if the conditional branch instruction predicts a branch and its child n1 misses, the execution mechanism 3 branches to the instruction next to the conditional branch instruction in the program, so the conventional example Branch prediction and associated processing can be performed using a relatively simple method without requiring such complicated processing.

However, if the branch prediction bit of the branch Δ11 mechanism is cleared due to a system reset, etc., the branch prediction function will be disabled unless the branch occurs until a new branch or 1lFI is registered. effect cannot be obtained. In other words, the branch r-run mechanism shown in the above-mentioned conventional example and prior art example is such that as a result of decoding an instruction,
If the instruction is determined to be a conditional branch instruction, it is predicted whether the conditional branch instruction will take a joint branch based on the history of whether or not it actually took a branch when it was previously executed, and if it is predicted that the instruction will take a branch. is a mechanism that changes the instruction capture light to the branch destination. Therefore, the branch prediction table is registered only when a conditional branch instruction is executed and a branch actually occurs, and until then, a branch cannot be predicted for that conditional branch instruction.

Therefore, this invention was made to solve the above-mentioned problems, and allows branch prediction to be easily performed even when a branch cannot be predicted based on the history, and at high speed. It is an object of the present invention to provide a data processing device having a branch 'j' DI function for processing.

[Means for Solving the Problems] A data processing device having a branch prediction function according to the present invention includes the following means.

(M) Instruction fetching/deciphering means for fetching and deciphering instructions.

(b) Instruction execution means for executing the instructions decoded by the instruction fetching/decoding means on the principle of Vibration processing.

(c) The instruction to be fetched and decoded by this instruction fetching and decoding means is a conditional branch instruction, and a branching element 11 that measures whether or not the conditional branch instruction causes a branch.
11 means.

(d) Swapping means for swapping the displacement to the branch destination instruction indicated by the conditional branch instruction and the instruction length of the conditional branch instruction based on the prediction result of the branch prediction means.

The branching device 7IP1 means includes a first branch prediction means for predicting whether or not a branch will occur based on the branch result in the previous processing, and a first branch prediction means for predicting whether or not a branch will occur based on the branch result in the previous processing, and a branch prediction means for predicting whether or not a branch will occur based on the branch condition of the instruction decoded by the instruction fetching/decoding means. and a second branch prediction means for predicting whether or not the branch will occur. Furthermore, when the first branch prediction means cannot predict whether or not a branch will occur, the second branch prediction means predicts whether or not a branch will occur.

[Operation] The data processing device having the branching element aP1 function according to the present invention includes second branching element n1 means for predicting whether or not a branch will occur based on the branch condition of the instruction decoded by the instruction fetching/decoding means. There is. By adding this second branch prediction means, branch prediction can be performed even when branch prediction based on history is impossible. Therefore, the hit rate of the branch element 111J is further improved than in a data processing device having a conventional branch prediction function.

[Embodiment of the Invention] An embodiment of the present invention will be described above with reference to the drawings. 1st
The figure is a schematic block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram for explaining the structure of the storage contents of the branching based on the history shown in FIG. 1. Next, the configuration of an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is a schematic block diagram showing a pipeline data processing device equipped with a branch prediction mechanism according to the present invention. In the figure, the same reference numerals as in FIG. 3 showing the prior art example indicate the same or equivalent functional parts. The branch prediction mechanism 4 based on history is a mechanism for predicting branches based on history, which is also present in conventional examples and prior art examples, but in the embodiment of the present invention, in addition to the branch prediction bit, it has a branch child 11111 nonn1 bit. ing. Branching based on this history]' The configuration of the ilN mechanism 4 is shown in FIG. This branch]' M
According to the FI mechanism 4, one entry is a pair of branch]-measurement bit and branch1-static1 disable bit corresponding to the lower 8 bits of the start address of the branch instruction. When this branch prediction mechanism 4 is initialized, branch unpredictability bits are set in all entries.

While this branch unpredictability bit is set, the branch prediction bit is considered meaningless. One conditional branch instruction consisting of
, the lower 8 of the first address of the conditional branch instruction
The branch apl disable bit corresponding to the bit is cleared. Corresponding to the above two types of bits, a first branch prediction signal line 22 and a branch prediction unpredictability signal line 23 are output from the branch element a-1 mechanism 4 based on the history. This data processing device also includes a branch prediction mechanism 20 that does not rely on history. This history-independent branch prediction mechanism 20 takes in a 4-bit branch condition code from the branch condition code register 7, and outputs a second branch prediction signal line 24 according to the pattern. In this case, since there are 16 combinations of 4-bit conditions, this branch prediction mechanism 20 can be realized with a simple combinational circuit. Further, the circuit can also be realized as a ROM with an address width of 4 bits. It is up to the chip designer to decide which branch condition code pattern will cause a branch to occur. Alternatively, this branch prediction mechanism 20 may be
It is also possible to configure AM, and to set under what conditions a branch is predicted to occur when the system is started up.

The selector 21 selects the first branch prediction f2 line 22 from the history-based branch prediction mechanism 4 and the second branch prediction line 22 from the history-based branch prediction mechanism 20, depending on the state of the signal from the branch prediction impossible signal line 23. Select one of the signal lines of branch r-611 and i retrace line 24. The result selected here is
Similar to the prior art example, this becomes valid only when the instruction decoder 2 decodes a conditional branch instruction.

Next, the specific operation of one embodiment of the present invention will be explained. If the decoded instruction is not a conditional branch instruction,
Alternatively, if the decoded instruction is a conditional branch instruction and the signal from the branch unpredictability signal line 23 from the history-based branch element al1 mechanism 4 is in the OFF state, the operation is exactly the same as the prior art example, so this explanation will be given. I will omit it here. Here, a case different from the prior art example will be described, that is, a case where the decoded instruction is a conditional branch instruction and the signal from the branch prediction impossible signal line 23 from the history-based branch prediction mechanism 4 is in the ON state. Here, the signal from this branch unpredictability signal line 23 is the branch element 111J based on the history.
ON if branch prediction is not registered in mechanism 4 yet.
It shows the state, and if a branch prediction is registered, it shows an OFF state. Therefore, when the signal from the branch element 11F1 disable signal line 23 is in the OFF state, the branch prediction result based on the history is valid, and when the signal is in the ON state, the branch prediction result not based on the history in the present invention is valid.

Assume that a conditional branch instruction with a branch condition code "0000" is read from memory (not shown).The branch condition code "0000" means that the branch will occur if the 2 (zero) flag is set. There is.

When this instruction is read, it is decoded and found to be a conditional branch instruction.

At this time, the branch prediction bit and branch unpredictability bit of the branch prediction mechanism 4 based on history are output to the first branch 71p3 signal line 22 and the branch C1 unpredictability signal line 23. In this case, the output signal from the branch 1I-1 disable signal line 23 is in the ON state. That is, the branch prediction has not yet been registered in the branch prediction mechanism 4 based on history, and this branch prediction mechanism 4 is in a state where it cannot make a prediction.

On the other hand, the branch prediction mechanism 20 that does not depend on the history receives the 4-bit branch condition code "0000" from the branch condition code register 7.
" is extracted, and the signal to be output to the second branch prediction signal line 24 is determined based on the pattern of this branch condition code. It is assumed that the code "0000" is set so that '?'ilF+ occurs when a branch occurs. .

At this time, the selector 21 selects the second branch ]'-δp1 signal line 24 from the branch prediction mechanism 20 that does not depend on the history, since the signal from the branch ΔIII unr prediction signal line 23 is in the ON state. As a result, the branch is predicted to occur. The subsequent processing is the same as when a branch is predicted to occur in the prior art example.

[Effects of the Invention] As described above, according to the present invention, in a data processing device equipped with a first branch prediction mechanism based on history, a second branch prediction mechanism that predicts a branch based on a branch condition not based on history is further provided. By adding , branch prediction becomes possible even when branch prediction based on history is impossible, and the probability of a correct prediction increases, resulting in faster data processing speed and improved system performance.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention, FIG. 2 is a configuration diagram showing the structure of the memory contents of the branch r measurement mechanism based on the history shown in FIG. 1, and FIG. 3 is an example of prior art of the present invention. FIG. 4 is a flowchart for explaining the specific operation of the prior art example of the present invention, FIG. 5 is a schematic block diagram showing a conventional data processing device having a branch prediction function, and FIG. The figure is a relationship diagram showing the relationship of addresses in memory to explain the branch prediction function. In the figure, 1 is an instruction register, 2 is an instruction decoder, and 3 is an instruction register.
is an execution mechanism, 4 is a branch prediction mechanism based on history, 7 is a branch condition code register, 8 is an inverter, 9, 12, 15 .
21 is a selector, 10, 11.13.14 are registers,
20 is a branch 1N mechanism that does not depend on history, 61 is an adder,
62 is a decoding program counter. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (11)

[Claims] (1) A data processing device having a branch prediction function, comprising an instruction fetching/decoding means for fetching an instruction and decoding the instruction, and executing the instruction decoded by the instruction fetching/deciphering means on the principle of pipeline processing. the instruction to be fetched and decoded by the instruction fetch/decipher means is a conditional branch instruction, branch prediction means for predicting whether or not the conditional branch instruction will cause a branch; a replacement means for replacing a displacement to a branch destination instruction indicated by the conditional branch instruction and an instruction length of the conditional branch instruction, based on a prediction result of the means;
Further, the branch prediction means includes a first branch prediction means for predicting whether or not to take a branch based on the branch result in the previous processing, and a first branch prediction means for predicting whether or not to take a branch based on the branch result in the previous processing, and a branch prediction means for taking a branch based on the branch condition of the instruction decoded by the instruction fetching/decoding means. and a second branch prediction means for predicting whether or not to take a branch, and when the first branch prediction means cannot predict whether or not to take a branch, the second branch prediction means determines whether to take a branch. A data processing device having a branch prediction function that predicts whether the branch is negative or not. (2) The first branch prediction means includes a prediction bit, corresponding to the address of the conditional branch instruction, for predicting whether or not the conditional branch instruction will branch based on the branch result in the previous processing; and an unpredictability bit indicating whether or not it is possible to predict whether or not the conditional branch instruction will branch based on the branch result in the previous processing, further comprising means for storing the prediction bit and the prediction. Depending on the disable bit, the first
A data processing device having a branch prediction function according to claim 1, which outputs a branch prediction signal and a branch unpredictability signal. (3) The second branch prediction means outputs a second branch prediction signal according to the pattern of the branch condition code of the instruction decoded by the instruction fetching/decoding means.
A data processing device having a branch prediction function according to claim 2. (4) The branch prediction means is configured to select one of the first branch prediction signal outputted from the first branch prediction means and the second branch prediction signal outputted from the second branch prediction means. a first selection means for selecting a branch prediction impossible signal outputted from the first branch prediction means;
A data processing device having a branch prediction function according to claim 3. (5) The instruction fetching/decoding means includes an instruction register for storing the instruction, and an instruction decoder for decoding the instruction stored in the instruction register and outputting at least an instruction length and displacement. , A data processing device having a branch prediction function according to any one of claims 1 to 4. (6) The rewriting means includes a first register for storing an instruction length decoded by the instruction fetching and decoding means, and a second register for storing a displacement decoded by the instruction fetching and decoding means. A register as claimed in claim 1, comprising: a register; and second selection means for selecting a displacement stored in said second register in response to a branch predicted by said branch prediction means. A data processing device having a branch prediction function according to any one of items 1 to 5. (7) The data processing device includes an address calculation means for calculating the address of the next instruction, and a displacement selected by the second selection means, which is given to the address calculation means, and is indicated by the address calculation means. 7. A data processing device having a branch prediction function according to claim 6, further comprising an adding means for adding the displacement to the address value obtained by the branch prediction function. (8) The second selection means outputs the instruction length stored in the first register when a branch is not predicted by the branch prediction means or when the instruction is a non-branch instruction. A data processing device having a branch prediction function according to claim 6 or 7. (9) The rewriting means includes a third register for storing the instruction length decoded by the instruction retrieval/decoding means, and a fourth register for storing the displacement decoded by the instruction retrieval/decoding means. and a third selection means for giving the instruction length stored in the third register to the instruction execution means in response to a branch being predicted by the branch prediction means. , A data processing device having a branch prediction function according to any one of claims 1 to 8. (10) When a branch is not predicted by the branch prediction means, or when the instruction is a non-branch instruction, the third selection means outputs the displacement stored in the fourth register, and selects the displacement. 10. A data processing device having a branch prediction function according to claim 9, further comprising means for imparting a branch prediction function to said instruction execution means. (11) The replacing means includes branch condition changing means for changing the branch condition of the conditional branch instruction based on the prediction result of the branch predicting means. A data processing device having a branch prediction function according to any one of Item 10.