JPH0992768A - Package for housing semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solder an outer lead terminal rigidly to a specified metalized wiring layer by making the surface rough within a specified range at the area to which the outer lead terminal of the metalized wiring layer is soldered. SOLUTION: This package comprises an insulation base 1 including a plurality of metalized wiring layers 5, a plurality of outer lead terminals 7 which are soldered to a part of the layers 5, and a lid 2, and a semiconductor element 3 is air-tightly housed inside a container 4 consisting of a base 1 and lid 2. In such a package, the surface of an area to which the terminal 7 of the wiring layer 5 is subjected to be soldered is finished at 0.5μm<=Ra<=1μm of mean roughness (Ra) at the center line and at 2μm<=Rmax<=4μm of the maximum height (Rmax). Thus, the wettability of a soldering material 8 against the layer 5 can be improved and the joint area be also enlarged, thereby soldering the terminal to the layer 5 rigidly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element, particularly a semiconductor integrated circuit element such as an LSI, is generally made of an electrically insulating material such as an aluminum oxide sintered body and has a substantially central portion on its upper surface. An insulating base having a plurality of metallized wiring layers made of refractory metal powder such as tungsten, molybdenum, and manganese, which are led out from the periphery of the recess to the outer peripheral edge of the semiconductor device. A plurality of external lead terminals attached to the metallized wiring layer via a brazing material such as silver brazing in order to electrically connect each electrode to an external electric circuit;
A semiconductor element is bonded and fixed to the bottom surface of the concave portion of the insulating base with an adhesive made of glass, resin, brazing material, etc., and each electrode of the semiconductor element is bonded to a predetermined metallized wiring layer with a bonding wire. By electrically connecting the lid to the upper surface of the insulating base through a sealing material such as glass or resin, and hermetically housing the semiconductor element in a container including the insulating base and the lid. It becomes a semiconductor device as a product.

[0003]

However, in this conventional package for accommodating semiconductor elements, the metallized wiring layer is usually formed of a refractory metal powder such as tungsten having a grain size of about 1.2 μm. The surface roughness of the layer is about 0.3μ in terms of center line average roughness (Ra).
m, the maximum height (Rmax) is about 1.2 μm, which is smooth.

Therefore, when the external lead terminals are brazed to the metallized wiring layer via a brazing material such as a silver brazing material, the bonding strength of the brazing material to the metallized wiring layer becomes weak,
It has a drawback that the external lead terminal is separated from the metallized wiring layer by applying a small external force.

Particularly, in recent semiconductor device housing packages, the line width of the metallized wiring layer and the external lead terminals is about 0.5 mm as the number of electrodes increases due to the higher density and higher integration of the semiconductor devices housed inside. As the brazing area of both becomes narrower, the above defects become more remarkable.

[0006]

The present invention comprises an insulating substrate having a plurality of metallized wiring layers, a plurality of external lead terminals brazed to a part of the metallized wiring layers, and a lid. A semiconductor element housing package for hermetically housing a semiconductor element in a container composed of an insulating base and a lid, wherein a surface roughness of a region of the metallized wiring layer to which an external lead terminal is brazed is a center line average roughness. Sa (Ra)
Is 0.5 μm ≦ Ra ≦ 1 μm, and the maximum height (Rmax) is 2 μm ≦ Rmax ≦ 4 μm.

Further, according to the present invention, the surface roughness of the area of the metallized wiring layer to which the external lead terminals are brazed is 0.5 μm ≦ Ra ≦ 1 μm in the center line average roughness (Ra) and the maximum height (Rmax). 2 μm ≦ Rmax ≦ 4 μm, the surface roughness other than the area where the external lead terminals are brazed is 0.2 μm ≦ Ra ≦ 0.4 μm in the center line average roughness (Ra), and the maximum height (Rmax) is 0. 8 μm ≦ Rmax ≦ 1.6 μ
m.

According to the semiconductor element housing package of the present invention, the surface roughness of the region of the metallized wiring layer to which the external lead terminals are brazed is 0.5 as the center line average roughness (Ra).
μm ≦ Ra ≦ 1 μm, maximum height (Rmax) is 2 μm ≦
Since Rmax ≦ 4 μm is set to be appropriately rough, the wettability of the brazing material with respect to the metallized wiring layer can be improved and the bonding area between the metallized wiring layer and the brazing material can be widened. It becomes possible to braze extremely strongly to the metallized wiring layer.

According to the package for housing a semiconductor device of the present invention, the surface roughness of the metallized wiring layer other than the area where the external lead terminals are brazed is the center line average roughness (Ra).
0.2 μm ≦ Ra ≦ 0.4 μm, maximum height (Rma
When 0.8 μm ≦ Rmax ≦ 1.6 μm in x), when the electrode of the semiconductor element is electrically connected to the metallized wiring layer via the bonding wire, the bonding wire and the metallized wiring layer are bonded very strongly. Each electrode of the semiconductor element can be reliably and firmly electrically connected to the external electric circuit.

[0010]

DETAILED DESCRIPTION OF THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a package for housing a semiconductor device according to the present invention, in which 1 is an insulating base,
2 is a lid. The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor element 3.

The insulating base 1 is provided with a recess 1a which forms a space for accommodating the semiconductor element 3 in the center of the upper surface thereof, and the semiconductor element 3 is placed on the bottom surface of the recess 1a.
It is adhered and fixed through an adhesive material such as glass, resin, or brazing material.

The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, and a glass ceramic sintered body. When it is made of an aluminum-based sintered body, it is made by adding and mixing an appropriate organic binder, solvent, etc. to raw material powders of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, etc. Ceramic green sheet (ceramic green sheet) is formed by adopting the roll method or calender roll method, and thereafter, the ceramic green sheet is subjected to appropriate punching processing and a plurality of these are laminated at a temperature of about 1600 ° C. It is manufactured by firing.

A plurality of metallized wiring layers 5 are formed on the insulating substrate 1 from the periphery of the recess 1a to the outer peripheral edge, and the electrodes of the semiconductor element 3 are bonded to the periphery of the recess 1a of the metallized wiring layer 5. An external lead terminal 7 electrically connected through the wire 6 and connected to an external electric circuit is attached to a portion led out to the upper surface of the insulating substrate 1 through a brazing material 8 such as silver brazing. Has been done.

The metallized wiring layer 5 acts as a conductive path when connecting each electrode of the semiconductor element 3 to an external electric circuit, and is formed of a refractory metal powder such as tungsten, molybdenum or manganese.

Further, in the metallized wiring layer 5, as shown in FIG. 2, the surface roughness of the area A to be brazed of the external lead terminals 7 is 0.5 μm ≦ Ra ≦ 1 in terms of center line average roughness (Ra).
μm, maximum height (Rmax) is 2 μm ≦ Rmax ≦ 4 μ
Therefore, the surface of the metallized wiring layer 5 has an appropriate roughness, and the wettability of the brazing material 8 with respect to the metallized wiring layer 5 is good while the bonding area of the metallized wiring layer 5 and the brazing material 8 is wide. As a result, the external lead terminal 7 can be brazed to the metallized wiring layer 5 extremely firmly.

The surface roughness of the area A of the external lead terminal 7 of the metallized wiring layer 5 to be brazed is such that the center line average roughness (Ra) is 0.5 μm> Ra and the maximum height (R).
max) is 2 μm> Rmax, the surface of the metallized wiring layer 5 becomes smooth and the external lead terminals 7 cannot be brazed firmly to the metallized wiring layer 5, and the center line average roughness (Ra) Is 1 μm <Ra,
When the maximum height (Rmax) is 4 μm <Rmax, when the external lead terminals 7 are brazed to the metallized wiring layer 5 through the brazing material 8, the brazing material 8 spreads poorly on the surface of the metallized wiring layer 5. As a result, the external lead terminals 7 cannot be firmly brazed to the metallized wiring layer 5. Therefore, the surface roughness of the brazed area A of the external lead terminals 7 of the metallized wiring layer 5 is 0.5 μm ≦ Ra ≦ 1 μm in the center line average roughness (Ra) and 2 μm ≦ in the maximum height (Rmax). It is specified in the range of Rmax ≦ 4 μm.

The metallized wiring layer 5 has a surface roughness other than the area A where the external lead terminals 7 are brazed, specifically, a surface roughness of the area B located around the recess 1a to which the bonding wire 6 is joined. Centerline average roughness (Ra)
0.2 μm ≦ Ra ≦ 0.4 μm, maximum height (Rma
When 0.8 μm ≦ Rmax ≦ 1.6 μm is set in x), when each electrode of the semiconductor element 3 is electrically connected to the metallized wiring layer 5 through the bonding wire 6, the bonding wire 6 and the metallized wiring layer 5 are joined together. Becomes extremely strong, and each electrode of the semiconductor element 3 can be reliably and firmly electrically connected to an external electric circuit. Therefore, the metallized wiring layer 5 has a surface roughness other than the area A where the external lead terminals 7 are brazed, in terms of center line average roughness (Ra) of 0.2 μm ≦ Ra ≦ 0.4 μm and a maximum height (Rmax).
It is preferable that 0.8 μm ≦ Rmax ≦ 1.6 μm.

Further, the metallized wiring layer 5 has good conductivity such as nickel and gold on the surface thereof, corrosion resistance and a brazing material 8.
A metal having good wettability with
If the metallized wiring layer 5 is deposited to a thickness of 0 μm,
Of the metallized wiring layer 5 and the bonding wire 6 and the brazing of the metallized wiring layer 5 and the external lead terminal 7 via the brazing material 8 can be strengthened. You can Therefore, in order to prevent the oxidative corrosion of the metallized wiring layer 5 and to strengthen the connection between the metallized wiring layer 5 and the bonding wire 6 and the brazing of the metallized wiring layer 5 and the external lead terminal 7, the metallized wiring layer 5 is strengthened. It is preferable that nickel, gold, or the like is layered on the surface of 1 to 20 μm in thickness.

The metallized wiring layer 5 is made of tungsten,
A metal paste obtained by adding and mixing an appropriate organic binder, a solvent, a plasticizer, etc. to a high melting point metal powder such as molybdenum or manganese is used as the insulating substrate 1 by adopting a conventionally known thick film method such as a screen printing method. The ceramic green sheet is preliminarily printed and applied in a predetermined pattern so that the ceramic green sheet is adhered and formed from the periphery of the concave portion 1a of the insulating substrate 1 to the outer peripheral edge.
In this case, two types of metal pastes, one having a high melting point metal powder particle size of 0.8 μm to 1.3 μm and one having a particle size of 1.5 μm to 3 μm were prepared, and the high melting point metal powder particle size was 0.8 μm. To 1.3 μm of metal paste to form a pattern on the periphery of the concave portion 1a of the insulating substrate 1, and a metal paste having a high melting point metal powder particle size of 1.5 μm to 3 μm to form a pattern on the outer peripheral end side of the insulating substrate 1. The surface roughness of the region A of the metallized wiring layer 5 to which the external lead terminals 7 are brazed is defined as the center line average roughness (R
a) 0.5 μm ≦ Ra ≦ 1 μm, maximum height (Rma
x) is set to 2 μm ≦ Rmax ≦ 4 μm, and the surface roughness other than the region A where the external lead terminals 7 are brazed is 0.2 μm ≦ Ra ≦ 0.4 μm in the center line average roughness (Ra) and the maximum height ( Rmax) can be 0.8 μm ≦ Rmax ≦ 1.6 μm.

On the other hand, the external lead terminals 7 brazed to the metallized wiring layer 5 have a function of connecting the semiconductor element 3 housed therein to an external electric circuit, and the external lead terminals 7 of the external electric circuit board. Each electrode of the semiconductor element 3 housed therein by being joined to the wiring conductor via solder or the like is electrically connected to an external electric circuit via the bonding wire 6, the metallized wiring layer 5 and the external lead terminal 7. Become.

The external lead terminal 7 is made of a metal material such as iron-nickel-cobalt alloy or iron-nickel alloy.
The ingot (lump) of the iron-nickel-cobalt alloy or the like is formed into a predetermined shape by subjecting the ingot (lump) to a conventionally known metal working method such as a rolling method or a punching method.

The external lead terminal 7 is also formed by depositing a metal of good conductivity such as nickel and gold and having excellent corrosion resistance on the surface thereof by plating to a thickness of 1 μm to 20 μm. It is possible to effectively prevent oxidative corrosion of 7 and to make good electrical connection between the external lead terminal 7 and the external electric circuit. Therefore, it is preferable to deposit nickel, gold or the like on the surface of the external lead terminal 7 by plating to a thickness of 1 μm to 20 μm.

Further, the insulating base body 1 to which the external lead terminals 7 are attached has a lid 2 around the recess 1a on its upper surface, which is made of glass,
The semiconductor element 3 is hermetically housed in the container 4 composed of the insulating base 1 and the lid body 2 by being bonded via a sealing material made of resin, a brazing material or the like.

The lid 2 is an aluminum oxide sintered body,
Made of electrical insulating material such as mullite sintered body, aluminum nitride sintered body, silicon carbide sintered body, glass ceramics sintered body, or metal material such as iron-nickel-cobalt alloy, iron-nickel alloy, and copper For example, in the case of an aluminum oxide sintered body, a raw material powder of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, etc. is filled in a predetermined press die and pressed by a constant pressure to form it. Then, it is manufactured by firing the molded article at a temperature of about 1500 ° C.,
When it is made of a metal material such as an iron-nickel-cobalt alloy, it is manufactured into a predetermined shape by subjecting the ingot of the iron-nickel-cobalt alloy to a conventionally known metal working method such as rolling or punching. .

Thus, according to the above-mentioned package for accommodating semiconductor elements, the semiconductor element 3 is formed on the bottom surface of the recess 1a of the insulating base 1.
While mounting the semiconductor element 3 on the glass, resin,
The semiconductor element 3 is bonded and fixed through an adhesive made of a brazing material or the like, and then each electrode of the semiconductor element 3 is connected to a predetermined metallized wiring layer 5 through a bonding wire 6, and then the upper surface of the insulating substrate 1 is covered. 2 is joined via a sealing material made of glass, resin, brazing material, etc., and the semiconductor element 3 is hermetically housed in the container 4 made of the insulating base 1 and the lid 2 to form a semiconductor device as a product. Become.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention. For example, as shown in FIG. Has a two-layer structure only in the region to which the external lead terminals 7 are brazed, and the surface roughness of the upper layer surface of the metallized wiring layer 5 is 0.5 μm ≦ Ra in terms of center line average roughness (Ra).
≦ 1 μm, maximum height (Rmax) is 2 μm ≦ Rmax ≦
It may be 4 μm.

[0027]

According to the semiconductor element accommodating package of the present invention, the surface roughness of the region of the metallized wiring layer to which the external lead terminals are brazed is equal to the center line average roughness (Ra) of 0.
5 μm ≦ Ra ≦ 1 μm, maximum height (Rmax) is 2 μm
Since ≦ Rmax ≦ 4 μm is set to be appropriately rough, the wettability of the brazing material with respect to the metallized wiring layer can be improved, and the bonding area between the metallized wiring layer and the brazing material can be widened. It becomes possible to braze extremely strongly to the metallized wiring layer.

According to the package for accommodating semiconductor elements of the present invention, the surface roughness of the metallized wiring layer other than the area where the external lead terminals are brazed is the center line average roughness (Ra).
0.2 μm ≦ Ra ≦ 0.4 μm, maximum height (Rma
When 0.8 μm ≦ Rmax ≦ 1.6 μm in x), when the electrode of the semiconductor element is electrically connected to the metallized wiring layer via the bonding wire, the bonding wire and the metallized wiring layer are bonded very strongly. Each electrode of the semiconductor element can be reliably and firmly electrically connected to the external electric circuit.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.

FIG. 2 is an enlarged cross-sectional view of a main part of the semiconductor element storage package shown in FIG.

FIG. 3 is an enlarged cross-sectional view of an essential part showing another embodiment of the present invention.

[Explanation of reference symbols] 1 ... Insulating substrate 1a ... Recess 2 ... Lid 3 ... Semiconductor element 4 ... Container 5 ... .... Metallized wiring layer 7 ... External lead terminals 8 ... Brazing material

Claims (2)

[Claims] 1. An insulating substrate having a plurality of metallized wiring layers, a plurality of external lead terminals brazed to a part of the metallized wiring layer, and a lid. In a package for housing a semiconductor device in which a semiconductor device is hermetically housed in a container, the surface roughness of a region of the metallized wiring layer to which the external lead terminals are brazed is a center line average roughness (Ra) of 0. 5 μm ≦ Ra ≦ 1 μ
m, maximum height (Rmax) is 2 μm ≦ Rmax ≦ 4 μm
A package for housing a semiconductor device, characterized in that 2. The surface roughness of the metallized wiring layer other than the area where the external lead terminals are brazed is 0.2 μm ≦ Ra ≦ 0.4 μm in center line average roughness (Ra) and the maximum height (Rmax). 2. The package for storing a semiconductor element according to claim 1, wherein 0.8 μm ≦ Rmax ≦ 1.6 μm.