JPH0989993A - Scanning circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use a scanning pin commonly as user pin by performing the input control of an internal circuit by a scanning FF added and inserted into a scan chain instead of a user pin also used as the scanning pin. SOLUTION: Scanning FF 18a, 18b are added to a scan chain, the output end of the FF 18a is connected to a combination circuit 12, and the output of a combination circuit 14 to the FF 18b. A circuit controlled by a user pin in general operation is controlled by the output signal of the added FF 18a in scanning operation. The signal outputted from the user pin in general operation is inputted to the added FF 18b in scanning operation, shifted by the scan chain and outputted. In this way, since input control and output observation can be performed by the FF 18a, 18b instead of the user pin used also as scanning pin, the scanning pin can be used also as the user pin without reducing the failure detecting ratio.

Description

Detailed Description of the Invention

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a scan circuit used for improving controllability and observability of an LSI.

[0002]

2. Description of the Related Art In recent years, as the circuit scale of LSIs has increased, the rate of occurrence of circuit failures has increased, and
The test vector for detecting the circuit failure tends to be complicated. Therefore, in order to facilitate the LSI test, improve the controllability and observability of the LSI, and improve the fault detection rate of the LSI by the test vector, a scan circuit is generally used in the past. ing.

A conventional scan circuit will be described below. FIG. 12 is a block diagram of an example of a circuit using the scan circuit. The circuit 24 includes a combinational circuit 12 to which an input signal is input from a user input pin, a combinational circuit 14 that outputs an output signal via a user output pin, and a scan arranged between these combinational circuits 12 and 14. Circuit 26. Further, the scan circuit 26 includes a plurality of scan flip-flops 18b, 18c, 18d, which form a scan chain (shift register).
18e.

FIG. 13 is a circuit diagram showing an example of a scan flip-flop. The scan flip-flop 18 selectively outputs a signal input to the input terminal 0 or a signal input to the input terminal 1 by a scan enable, and a signal output from the multiplexer 20 by a scan clock. It has a D-type flip-flop 22 which holds it and outputs it from the output terminal 0 and the output terminal 1.

Scan flip-flops 18b, 18
The outputs of the combinational circuit 12 are input to the input terminals 0 of c, 18d, and 18e, respectively, and the scan-in and scan flip-flops 18a of the preceding stage are input to the input terminal 1.
Output terminals 1 of 18b and 18c are input. The output terminals 0 are input to the combinational circuit 14, and the output terminals 1 are input to the scan flip-flops 18 of the next stage.
It is connected to the input terminals 1 of c, 18d and 18e and the scan-out.

In the circuit 24, the combination circuit 12 is controlled by an input signal inputted from a user input pin. The output signals output from the combinational circuit 12 are the scan flip-flops 18b, 18c, 1 according to the scan clock when the scan enable is 0.
8d and 18e are latched, and when the scan enable is 1, the scan clock is shifted each time the scan clock is input and sequentially output from the scan out.

Scan flip-flops 18b, 18
The output signals output from the output terminals 0 of c, 18d, and 18e are sequentially set by shifting the signal input from scan-in each time the scan clock is input when the scan enable is 1. . The combinational circuit 14 is controlled by the output signal output from the output terminal 0 of the scan flip-flops 18b, 18c, 18d, and 18e set in this way, and the combinational circuit 1
The output signal of 4 is output via the user output pin.

As described above, by using the scan circuit, the sequential circuit can be regarded as a combinational circuit and the test can be performed. Therefore, for example, the LSI test can be facilitated by automatically generating a test vector. Since the controllability and observability are improved, the fault coverage can be improved. Further, by providing a plurality of scan chains, the number of steps of the test vector can be reduced, and the time required for testing the LSI can be shortened.

By the way, the scan pins such as scan-in, scan-out, scan enable, and scan clock are, for example, input pins, output pins, 3S (3 state) output pins, IO in order to prevent an increase in the number of pins.
It is preferably used also as a user pin such as an (input / output) pin.

However, when a user pin having an output such as an output pin, a 3S output pin, an IO pin, etc. is also used as a scan-in, an output signal output from the user pin during a normal operation cannot be observed during a scan operation. If the user pin having an input such as an input pin or an IO pin is also used as the scan out, it is impossible to control the internal circuit by the input signal input to the user pin during the normal operation during the scan operation. There is a problem that the fault coverage decreases.

Further, when a user pin having an output is also used as a scan enable, or when a user pin having an input is also used as a scan enable, observability and controllability are similarly deteriorated. Therefore, the scan-in and the scan-out are shared with the input pin and the output pin, respectively. Further, the system clock is used as the scan clock, and the scan enable is provided as a dedicated pin instead of being used as a user pin.

When implementing a scan circuit, first of all,
A multiplexer is inserted just before every flip-flop in the circuit. At the input 0 of this multiplexer,
The signal input to the data input terminal of each flip-flop is input, and the output signal of the flip-flop that is the preceding stage of the scan chain is input to the input terminal 1.
Scan enable is input to both selection input terminals. The output signal of the multiplexer is input to the data input terminal of each flip-flop.

Here, a method of using the scan pin and the user pin in combination will be illustrated. FIGS. 14A and 14B are configuration circuit diagrams of an example of a circuit before and after the combined use of the scan-in and the input pin. As shown in the figure, when the scan-in is also used as the input pin 44, the D-type flip-flop 48 is provided at the input terminal 0 of the multiplexer 50 inserted immediately before the D-type flip-flop 48 at the first stage of the scan chain. The signal input to the data input terminal D is input, and the scan-in is input to the input terminal 1.

FIGS. 15A and 15B are schematic circuit diagrams of an example of a circuit before and after the combined use of the scan-out and the user output pin. When the scan-out is used as the output pin 28, the output multiplexer 46 that selectively outputs the output signal to the output pin 28 is inserted immediately after the D-type flip-flop 48 at the final stage of the scan chain. The output signal Q of the D-type flip-flop 48 at the final stage of the scan chain is input to the input terminal 1 of the multiplexer 46, and the output signal output from the output pin during normal operation is input to the input terminal 0, and the selection input A scan test is input at the end. The output signal of the multiplexer 46 is output from the scan out.

In these circuits, by using the scan-in and the input pin 44 in combination, the internal circuit can be controlled by the data input from the scan-in. Also scan out and output pin 28
Is also used as the output signal Q of the D-type flip-flop 48 at the final stage of the scan chain by switching the normal operation and the scan operation by the scan test.
And the output signal output from the output pin 28 during normal operation can be selectively output from the output pin 28.

However, in the conventional scan circuit,
Since scan-in and scan-out can be used only as input pins and output pins, respectively, for example, in an LSI that frequently uses IO pins instead of input pins and 3S pins or IO pins instead of output pins, , The number of input pins and output pins that can be shared is insufficient, it is necessary to increase the number of pins for scan pins, or the number of scan chains is limited, the number of steps of test vector increases, There is a problem that the LSI test time increases.

On the other hand, as described above, if the scan pin and the user pin are used in combination other than the scan-in and the input pin and the scan-out and the output pin, the user pin that is also used is the original one in the normal operation during the scan operation. Function, that is, if it is a user pin having an input, it controls the internal circuit by inputting a signal, or if it is a user pin having an output, it fulfills the original function of observing the output signal from the internal circuit. Therefore, there is a problem that the failure detection rate decreases in a part of the internal circuit related to the user pin.

[0018]

SUMMARY OF THE INVENTION An object of the present invention is to provide a scan circuit which can be used as both a scan pin and a user pin without lowering the failure detection rate in view of various problems based on the above-mentioned prior art. To provide.

[0019]

In order to achieve the above object, the present invention provides a scan in which a scan pin also used as a user pin and a plurality of scan flip-flops controlled by the scan pin are connected in series. It has a chain and a scan flip-flop that is additionally inserted in this scan chain, and during normal operation,
The internal circuit is controlled by the input signal input to the user pin, the output signal output from the internal circuit is observed by the output signal output from the user pin, and the additional insertion is performed during the scan operation. The internal circuit is controlled by a first output signal output from the scan flip-flop, and the internal circuit is output by a second output signal output from the additionally inserted scan flip-flop. The present invention provides a scan circuit characterized by observing a generated output signal.

Here, in the scan circuit described above,
Furthermore, either one of the input signal input to the user pin during normal operation or the first output signal output from the scan flip-flop during scan operation is input to the user pin during normal operation. It is preferable to have an input multiplexer for selectively outputting to an internal circuit controlled by an input signal.

Further, in the above-described scan circuit, either the output signal to be output from the user pin during the normal operation or the second output signal output from the scan flip-flop during the scan operation. It is preferable to have an output multiplexer that selectively outputs one of them to the user pin.

Further, in the above-described scan circuit, either the input signal input to the user pin during the normal operation or the first output signal output from the scan flip-flop during the scan operation. An input multiplexer that selectively outputs one to an internal circuit controlled by an input signal input to the user pin during normal operation, an output signal to be output from the user pin during normal operation, or the output signal to be output from the user pin during scan operation. It is preferable to have an output multiplexer that selectively outputs one of the second output signals output from the scan flip-flop to the user pin.

[0023]

In the scan circuit of the present invention, when the scan circuit and the user pin are combined to form the scan circuit, the user pin also used as the scan pin is used as the scan pin during the scan operation, thereby having an input, for example. A scan provided separately from the original function of the circuit to prevent the original function of normal operation such as input control for user pins and output observation for user pins with outputs from being unable to be fulfilled. The additional flip-flop is added as a part of the scan chain.

Since the added scan flip-flop can set data from scan-in, it is set to the scan flip-flop instead of the user pin which cannot be used for input control by being used also as the scan pin. Input control can be performed by data. Also, since the output signal of the internal circuit can be latched and shifted and output from the scan out, it is output from the scan out instead of the user pin that cannot perform output observation by being used also as the scan pin. Output observation can be performed by an internal signal.

Therefore, according to the scan circuit of the present invention, the output signal output from the user pin during the normal operation is latched by the additional scan flip-flop during the scan operation, shifted, and output from the scan out. The internal circuit controlled by the input signal input to the user pin during the normal operation is controlled by the data set in the additional scan flip-flop during the scan operation. Therefore, the scan pin and the user pin can be used in common without lowering the failure detection rate.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a scan circuit according to the present invention will be described in detail with reference to a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a configuration circuit diagram of an embodiment of a circuit using the scan circuit of the present invention. Circuit 10 in the illustrated example
Has combination circuits 12 and 14 and a scan circuit 16, and the scan circuit 16 includes scan flip-flops 18a, 18b, 18c,
It has 18d, 18e, and 18f. The configuration of the scan flip-flop 18 is not particularly limited, but the one shown in FIG. 13 can be used, for example.

Here, the input terminal 0 of the first-stage scanning flip-flop 18a is fixed to the power source, and the scan-in is input to the input terminal 1. The output terminal 0 is input to the combinational circuit 12, and the output terminal 1 is input to the input terminal 1 of the scan flip-flop 18b in the next stage.

Scan flip-flops 18b, 18
The output signals of the combinational circuit 12 are input to the input terminals 0 of the c, 18d, and 18e, respectively, and the input terminal 1 receives the scan flip-flops 18a, 18b, 18 of the preceding stage, respectively.
The output terminals 1 of c and 18d are input. The output terminals 0 are input to the combinational circuit 14, and the output terminals 1
Are the next-stage scan flip-flops 18c,
It is inputted to the input terminals 1 of 18d, 18e and 18f.

Scan flip-flop 18 at the final stage
The output signal of the combinational circuit 14 is input to the input terminal 0 of f, and the scan flip-flop 1 of the previous stage is input to the input terminal 1.
The output terminal 1 of 8e is input. Also, its output terminal 0
Is opened, and the scan-out is output from the output terminal 1.

In this circuit 10, the scan circuit 16
For this purpose, scan pins such as scan test, scan enable, scan in and scan out, and scan clock are used. The scan test is to switch between normal operation and scan operation of the circuit.
For example, the normal operation is selected when 0, and the scan operation is selected when 1. In addition, the scan test is a dedicated pin,
Alternatively, it is provided as one of the test modes selected by the test pin.

The scan enable is input to the selection input terminals of all the scan flip-flops 18 and selects the signal input to the input terminal 0 or the input terminal 1 of the scan flip-flops 18. For example, when the value is 0, the signal input to the input terminal 0 is selected, and when the value is 1, the signal input to the input terminal 1 is selected. It is preferable that the scan enable is enabled only when the scan operation is selected by the scan test.

Scan-in and scan-out are inputs and outputs of the scan chain, respectively. The scan clock is input to the clock input terminals of all the scan flip-flops 18. A dedicated pin may be provided as the scan clock, or the system clock of the circuit may be used.

Here, a specific method of realizing the scan circuit of the present invention will be described. In the scan circuit of the present invention, scan pins such as scan-in, scan-out and scan-enable are input pins, output pins,
It is also used as all kinds of user pins such as 3S output pins or IO pins. At this time, for example, when the scan-in is also used as the output pin or the 3S output pin, when the scan-out is also used as the input pin, and when the scan enable is also used as the output pin or the 3S output pin, the user pin is changed to the IO pin. Need to change to.

Next, all the flip-flops in the circuit are changed to scan flip-flops by inserting multiplexers immediately before all the flip-flops in the circuit, and further, the user pin also used as the scan pin. However, when the original function before being combined, for example, input control and output observation cannot be performed, a scan flip-flop including a multiplexer and a D-type flip-flop is additionally inserted. The additionally inserted scan flip-flop may be inserted at any position in the scan chain.

When the user pin also used as the scan pin has an input, the input signal input to the user pin during the normal operation and the input signal input to the internal circuit during the scan operation, that is, the additional scan signal. When an input multiplexer for switching the output signal of the flip-flop is additionally inserted and the user pin that is also used as the scanout has an output, the output signal output from the user pin during normal operation and the output from the scanout during scan operation An output multiplexer for switching between the output signal to be generated, that is, the output signal of the scan flip-flop at the final stage of the scan chain is additionally inserted. In addition,
These multiplexers are controlled by the scan test.

At this time, a power supply or ground is connected to the input terminal 0 of the added scan flip-flop when the user pin also serving as the scan pin is an input pin. The output signal output from the pin is input. On the other hand, at the input terminal 1 of the multiplexer, if the scan flip-flop to be added is inserted in the first stage of the scan chain, scan-in is input, and if it is inserted in a position other than the first stage, the previous stage forming the scan chain is input. The output terminal of the scan flip-flop is input.

The output terminal of the added scan flip-flop is an input pin when the added scan flip-flop is inserted in the final stage of the scan chain and the user pin also used as the scan-out is an input pin. , Is input from the input pin to the output buffer of the changed IO pin, and is input to the input terminal 1 of the output multiplexer when the input pin is other than the input pin. The output end of the scan flip-flop to be added is input to the input end 1 of the scan flip-flop at the next stage of the scan chain when inserted at a position other than the final stage.

The scan circuit of the present invention is constructed in this way. In the scan circuit 16 in the illustrated example, by adding scan flip-flops 18a and 18f in the scan chain, in addition to the original circuit function, these scan flip-flops 18 are added.
The user pins that are also used as scan pins are substituted for a and 18f.

That is, the circuit controlled by the user pin during the normal operation is controlled by the signal output from the output terminal 0 of the added scan flip-flop 18a during the scan operation. Further, the signal output from the user pin during the normal operation is input to the input terminal 0 of the added scan flip-flop 18f during the scan operation, is shifted by the scan chain, and is output.

As described above, according to the scan circuit of the present invention, by the scan flip-flop added,
Input control and output observation can be performed instead of user pins that are also used as scan pins, so that scan-in, scan-out, and scan-enable can be used as all types of user pins without degrading the fault coverage. You can

Next, the operation of the scan circuit of the present invention will be described assuming that scan-in and scan-out are also used as the user output pin and the user input pin, respectively.

In the scan circuit 16 of the illustrated example, the signal output from the output terminal 0 of the scan flip-flop 18a is set by the signal input from scan-in when the scan enable is 1. The combinational circuit 12, instead of the input signal input from the user input pin during the normal operation, outputs the output signal output from the output terminal 0 of the scan flip-flop 18a thus set during the scan operation and It is controlled by an input signal input from a user input pin other than.

The output signals output from the combinational circuit 12 are the scan flip-flops 18 in accordance with the scan clock when the scan enable is 0.
b, 18c, 18d and 18e are latched, and when the scan enable is 1, they are shifted every time the scan clock is input and sequentially output from the scan out.

Scan flip-flops 18b, 18
The output signals output from the output terminals 0 of c, 18d, and 18e are sequentially set by shifting the signal input from the scan-in each time the scan clock is input when the scan enable is 1. . The combinational circuit 14 has the output terminal 0 of the scan flip-flops 18b, 18c, 18d and 18e set in this way.
It is controlled by the output signal output from.

The output signal output from the user output pin in the normal operation is latched by the scan flip-flop 18f by the scan clock when the scan enable is 0 during the scan operation, and is scanned when the scan enable is 1. It is shifted by the clock and output from the scan out. Further, the output signals output from the other combination circuits 14 are output from the user output pin.

As described above, according to the scan circuit of the present invention, the observability of the output signal output from the user pin during the normal operation is maintained by being shifted and output by the scan circuit during the scan operation. Since the internal circuit controlled by the input signal input to the user pin during the normal operation is controlled by the output signal of the scan flip-flop during the scan operation,
The scan pin and the user pin can be used in common without lowering the failure detection rate.

The scan circuit of the present invention basically operates as described above. Next, using the scan circuit of the present invention,
A method of using a scan pin and a user pin together will be illustrated.

FIGS. 2A and 2B are configuration circuit diagrams of an example of a circuit before and after the combined use of the scan-in and the output pin, respectively. When both scan-in and output pin are used, output pin 28 is changed to IO pin 30,
A scan flip-flop including the multiplexer 32 and the D-type flip-flop 34 is added to the scan chain. Input / output control of the IO pin 30 is performed by a scan test. Output pin 28 during normal operation
The output signal output from is input to the input end 0 of the multiplexer 32 and the input end of the output buffer 36 of the IO pin 30, and the output end of the input buffer 38 of the IO pin 30 is input to the input end 1 of the multiplexer 32. . Scan enable is input to the selection input terminal of the multiplexer 32, and its output terminal is input to the data input terminal D of the D-type flip-flop 34.

In the circuit of FIG. 2B, the scan test is set to 0 during normal operation. At this time, IO pin 30
The output buffer 36 is set to the active state, and the output signal output from the output pin 28 during the normal operation is output from the IO pin 30. That is, the circuit operates exactly like the circuit of FIG.

On the other hand, the scan test is set to 1 during the scan operation. At this time, the output buffer 3 of the IO pin 30
6 is made inactive, and IO pin 30 is used as scan-in. When the scan enable is 0, the output signal output from the output pin 28 in the normal operation is selectively output by the multiplexer 32 and latched in the D-type flip-flop 34. When the scan enable is 1, the output signal is sequentially shifted to scan out. Is output from.

As described above, since the output signal output from the output pin during the normal operation is shifted and output by the scan circuit, its observability is maintained, so that the failure detection rate is not lowered. The scan-in and output pin can be combined.

Next, FIGS. 3A and 3B are configuration circuit diagrams of an example of a circuit before and after the combined use of the scan-in and the 3S output pin, respectively. The circuit of the illustrated example further has a control signal of the 3S output pin 40 in the circuit of FIG. Further, the input / output control of the IO pin 30 is performed by the scan test and the logical sum of the control signals of the 3S output pin 40.

In the circuit of FIG. 3B, during the normal operation, the output signal output from the 3S output pin 40 during the normal operation is output according to the control signal of the 3S output pin 40. That is, the circuit operates exactly like the circuit of FIG. On the other hand, the operation at the time of scanning is exactly the same as the case of using both the scan-in and the output pin 28 because the output buffer 36 of the IO pin 30 is made inactive by the scan test.

FIGS. 4A and 4B are configuration circuit diagrams of an example of a circuit before and after the combined use of scan-in and IO pins, respectively. The circuit of the illustrated example further includes an input multiplexer 42 for selecting and outputting an input signal to the internal circuit in the circuit of FIG. Multiplexer 42
An input signal input to the IO pin 30 during normal operation is input to the input terminal 0 of the input terminal 1, the output terminal Q of the D-type flip-flop 34 is input to the input terminal 1, and the scan test is input to the selected input terminal. The output end is IO pin 3 during normal operation.
It is input to an internal circuit controlled by an input signal input to 0.

In the circuit of FIG. 4B, during normal operation, the signal output from the IO pin 30 during normal operation is I.
The signal output according to the control signal of the O pin 30 and input to the IO pin 30 during normal operation is the multiplexer 42.
Are selectively output by the internal circuit controlled by an input signal input to the IO pin 30 during normal operation. That is, the circuit operates exactly like the circuit of FIG.

On the other hand, during the scan operation, the output buffer 36 of the IO pin 30 is made inactive, and the IO pin 30 is used as scan-in. That is, the output signal output from the IO pin 30 during normal operation is latched by the D-type flip-flop 34, sequentially shifted, and output from the scan-out. When the scan enable is 1, the signal input from the scan-in is selectively output by the multiplexer 32, latched by the D-type flip-flop 34, selectively output by the multiplexer 42, and input to the IO pin 30 during normal operation. Input to an internal circuit controlled by the input signal.

As described above, the output signal output from the IO pin during the normal operation maintains its observability by being shifted and output by the scan circuit, and the output signal is input by the input signal to the IO pin during the normal operation. Since the controlled internal circuit is controlled by the output signal of the D-type flip-flop 34, the scan-in can be used as the IO pin without lowering the failure detection rate.

FIGS. 5A and 5B are configuration circuit diagrams of an example of a circuit before and after the combined use of the scan-out and the input pin, respectively. When the scan-out is also used as the input pin, the input pin 44 is changed to the IO pin 30, and the multiplexer 32 and the D-type flip-flop 3 are used.
4 and an input multiplexer 42 for selectively outputting an input signal to the internal circuit are added. Input / output control of the IO pin 30 is performed by an inversion signal of the scan test. The input end 0 of the multiplexer 32 is fixed to the power supply, the output end Q of the scan flip-flop 34 at the preceding stage is input to the input end 1, and the output end is input to the data input end D of the D-type flip-flop 34. D-type flip-flop 34
The output terminal Q is input to the output buffer 36 of the IO pin 30 and the input terminal 1 of the multiplexer 42. The input buffer 0 of the IO pin 30 is connected to the input terminal 0 of the multiplexer 42.
8 output terminals are input, a scan input is input to a selection input terminal, and an output terminal is input to an internal circuit controlled by an input signal input to the input pin 44 during normal operation.

In the circuit of FIG. 5B, the output buffer 36 of the IO pin 30 is inactive during the normal operation, and the input signal input to the input pin 44 during the normal operation is selectively output by the multiplexer 42. , Is input to an internal circuit controlled by an input signal input to the input pin 44 during normal operation. That is, the circuit operates exactly like the circuit of FIG.

On the other hand, during the scan operation, the output buffer 36 of the IO pin 30 is activated, and the IO pin 30 is used as the scan out. When the scan enable is 1, the signal input from the scan-in is selectively output by the multiplexer 32, latched by the D-type flip-flop 34, and sequentially shifted to I.
Output from O pin 30 and multiplexer 4
2 is selected and output by the input pin 44 during normal operation.
Is input to an internal circuit controlled by an input signal input to.

As described above, since the internal circuit controlled by the input signal input to the input pin during the normal operation is controlled by the output signal of the D-type flip-flop 34, the scan is performed without lowering the failure detection rate. The output and the input pin can be combined.

FIGS. 6 (a) and 6 (b) are schematic circuit diagrams of an example of a circuit before and after the combined use of the scanout and the 3S output pin. When the scan out and the 3S output pin are combined, the multiplexer 32 and D
The type flip-flop 34 and the output multiplexer 46 for selectively outputting the output signal to the 3S output pin 40 are added. The output signal output from the 3S output pin 40 during normal operation is input to the input terminals 0 of the multiplexers 32 and 46. The output end Q of the final stage scanning flip-flop 34 is input to the input end 1 of the multiplexer 32, and the output end thereof is input to the data input end D of the D-type flip-flop 34. The output terminal Q of the D flip-flop 34 is input to the input terminal 1 of the multiplexer 46, and the output terminal of the multiplexer 46 is input to the input terminal of the output buffer 36 of the 3S output pin 40. The input / output control of the 3S output pin 40 is performed by the logical product of the inverted signal of the scan test and the control signal of the 3S output pin 40.

In the circuit of FIG. 6B, during normal operation, the signal output from the 3S output pin 40 during normal operation is selectively output by the multiplexer 46 and output according to the control signal of the 3S output pin 40. . That is, FIG.
It operates in exactly the same way as the circuit of (a).

On the other hand, during the scanning operation, the 3S output pin 4
The output buffer 36 of 0 is activated and 3S
The output pin 40 is used as a scan out. When the scan enable is 0, the signal output from the 3S output pin 40 in the normal operation is selectively output by the multiplexer 32 and latched in the D-type flip-flop 34. When the scan enable is 1, the signal is sequentially shifted to scan out. Is output from.

As described above, since the output signal output from the 3S output pin during the normal operation is shifted and output by the scan circuit, its observability is maintained, so that the failure detection rate is not lowered. , The scan-out and the 3S output pin can be combined.

If the control signal of the 3S output pin 40 can be easily controlled from the user input pin, the multiplexer 32 and the D-type flip-flop 34 are not necessarily provided. That is, in normal operation, the 3S output pin 40
When the scan test is set to 0, the output signal output from is output according to the control signal of the 3S output pin 40, so that the observability can be maintained. In this case, for example, only the output multiplexer 46 needs to be added.

FIGS. 7A and 7B are configuration circuit diagrams of an example of a circuit before and after the combined use of the scan-out and the IO pin, respectively. The circuit of the illustrated example further has an input multiplexer 42 for selecting and outputting an input signal to the internal circuit in the circuit of FIG. Multiplexer 4
An input signal input to the IO pin 30 at the time of normal operation is input to the input terminal 0 of 2 and an output terminal Q of the D-type flip-flop 34 is input to the input terminal 1 and a scan test is performed to the selected input terminal. The input end is input to the internal circuit controlled by the input signal input to the IO pin 30 during the normal operation.

In the circuit of FIG. 7B, during the normal operation, the output signal output from the IO pin 30 during the normal operation is selectively output by the multiplexer 46 and output according to the control signal of the IO pin 30. IO during normal operation
The input signal input to the pin 30 is selectively output by the multiplexer 42 and input to the internal circuit controlled by the input signal input to the IO pin 30 during normal operation. That is, the circuit operates exactly like the circuit of FIG.

On the other hand, during the scan operation, the output buffer 36 of the IO pin 30 is activated and the IO pin 3
0 is used as scan out. That is, when the scan enable is 0, the output signal output from the IO pin 30 in the normal operation is selectively output by the multiplexer 32 and latched in the D-type flip-flop 34.
It is selectively output by the multiplexer 46 and output from the scan out. When scan enable is 1,
The signal input from the scan-in is the multiplexer 3
2 is selected and output, is latched by the D-type flip-flop 34 and sequentially shifted, is selectively output by the multiplexer 42, and is input to the internal circuit controlled by the input signal input to the IO pin 30 during normal operation.

As described above, the output signal output from the IO pin during the normal operation is kept observable by being shifted and output by the scan circuit, and the output signal is input by the input signal to the IO pin during the normal operation. Since the controlled internal circuit is controlled by the output signal of the D-type flip-flop, it does not reduce the failure detection rate,
The scan-out and IO pin can be combined.

FIGS. 8A and 8B are configuration circuit diagrams of an example of a circuit before and after the combined use of the scan enable and the input pin, respectively. When both the scan enable and the input pin are used, the multiplexer 32 and D
The type flip-flop 34 and the input multiplexer 42 for selectively outputting the input signal to the internal circuit are added.
The input terminal 0 of the multiplexer 32 is fixed to the power supply, the output terminal Q of the preceding-stage scanning flip-flop 34 is input to the input terminal 1, and the logical product of the scan test and the scan enable is input to the selection input terminal. The output terminal is input to the data input terminal D of the D-type flip-flop 34. D
The output terminal Q of the type flip-flop 34 is the input terminal 1 of the multiplexer 32 of the next-stage scanning flip-flop.
Is input to the input terminal 1 of the multiplexer 42. An input signal input to the input pin 44 during normal operation is input to the input terminal 0 of the multiplexer 42, a scan test is input to the selection input terminal, and an output terminal is input to the input pin 44 during normal operation. It is input to an internal circuit controlled by a signal.

In the circuit of FIG. 8B, during the normal operation, the input signal input to the input pin 44 during the normal operation is selected and output by the multiplexer 42, and according to the input signal input to the input pin 44 during the normal operation. It is input to the internal circuit to be controlled. That is, the circuit operates exactly like the circuit of FIG.

On the other hand, during the scan operation, the input pin 44 is used as a scan enable. That is, when the scan test is 1, the scan enable is valid. When the scan enable is 1, the signal input from the scan-in is selectively output by the multiplexer 32, latched by the D-type flip-flop 34 and sequentially shifted, and selectively output by the multiplexer 42, and is input and output by the input pin 44 during normal operation. Is input to an internal circuit controlled by an input signal input to.

As described above, since the internal circuit controlled by the input signal input to the input pin during the normal operation is controlled by the output signal of the D-type flip-flop, the scan enable can be performed without lowering the failure detection rate. Can also be used as an input pin.

FIGS. 9A and 9B are configuration circuit diagrams of an example of a circuit before and after the combined use of the scan enable and the output pin. When both the scan enable and the output pin are used, the output pin 28 is the IO pin 30.
And a multiplexer 32 and a D-type flip-flop 34 are added. Input / output control of the IO pin 30 is performed by a scan test. The output signal output from the output pin 28 during normal operation is the multiplexer 32.
Is input to the input end of the output buffer 36 of the IO pin 30, and the output end of the input buffer 38 of the IO pin 30 is ANDed with the scan test and input to the selection input end of the multiplexer 32.

In the circuit of FIG. 9B, the output buffer 36 of the IO pin 30 is activated during the normal operation, and the output pin 2 from the IO pin 30 is output during the normal operation.
The output signal output from 8 is output. That is, FIG.
It operates in exactly the same way as the circuit of (a).

On the other hand, during the scan operation, the output buffer 36 of the IO pin 30 is deactivated and the IO pin 30 is used as a scan enable. That is, when the scan test is 1, the scan enable is valid. When the scan enable is 0, the output signal output from the output pin 28 during the normal operation is selectively output by the multiplexer 32 to be output to the D-type flip-flop 3.
When the scan enable is 1, it is sequentially shifted and output from the scan out.

As described above, since the output signal output from the output pin during the normal operation is shifted and output by the scan circuit, its observability is maintained.
The scan enable can be used as the output pin without lowering the failure detection rate.

FIGS. 10A and 10B are configuration circuit diagrams of an example of a circuit before and after the combined use of the scan enable and the 3S output pin. The circuit shown is
In the circuit of FIG. 9, a control signal for the 3S output pin 40 is further included. The input / output control of the IO pin 30 is performed by the scan test and the logical sum of the control signals of the 3S output pin 40.

In the circuit of FIG. 10B, during the normal operation, the output signal output from the 3S output pin 40 during the normal operation is output according to the control signal of the 3S output pin 40. That is, the circuit operates exactly like the circuit of FIG.
On the other hand, regarding the operation at the time of scanning, since the output buffer 36 of the IO pin 30 is made inactive by the scan test, the scan enable and the output pin 28 are
This is exactly the same as the case of using both and.

FIGS. 11 (a) and 11 (b) are schematic circuit diagrams of an example of a circuit before and after the combined use of the scan enable and the IO pin. The circuit shown in FIG.
The 0 circuit further includes an input multiplexer 42 that selectively outputs an input signal to the internal circuit. The input terminal 0 of the multiplexer 42 is connected to the IO pin 30 during normal operation.
To the input pin 1, the output end Q of the D-type flip-flop 34 is input to the input end 1, the scan test is input to the selection input end, and the output end is input to the IO pin 30 during normal operation. Input to an internal circuit controlled by the input signal.

In the circuit of FIG. 11B, during normal operation, the signal output from the IO pin 30 during normal operation is I.
The input signal that is output according to the control signal of the O pin 30 and that is input to the IO pin 30 during normal operation is selected and output by the multiplexer 42, and is input to the IO pin 30 during normal operation.
Is input to an internal circuit controlled by an input signal input to. That is, it operates in exactly the same way as the circuit of FIG.

On the other hand, during the scan operation, the output buffer 36 of the IO pin 30 is made inactive, and the IO pin 30 is used as the scan enable. That is, when the scan test is 1, the scan enable is valid. When the scan enable is 0, the output signal output from the IO pin 30 in the normal operation is latched by the D-type flip-flop 34, and when the scan enable is 1, the output signal is sequentially shifted and output from the scan out.
When the scan enable is 1, the signal input from the scan-in is selectively output by the multiplexer 32 and latched by the D-type flip-flop 34, selectively output by the multiplexer 42, and is IO-outputd during normal operation.
It is input to the internal circuit controlled by the input signal input to the pin 30.

As described above, the output signal output from the IO pin during the normal operation maintains its observability by being shifted and output by the scan circuit, and the output signal is input by the input signal to the IO pin during the normal operation. Since the controlled internal circuit is controlled by the output signal of the D-type flip-flop, it does not reduce the failure detection rate,
The scan enable and IO pin can be combined.

[0086]

As described above in detail, in the scan circuit of the present invention, a scan flip-flop is additionally inserted in the scan chain, and the added scan flip-flop allows the user to also use the scan pin. Instead of pins, it controls the input and output of internal circuits. In the scan circuit of the present invention, the controllability and observability of the user pin that is also used as the scan pin are maintained, so that the scan pin can be used as all kinds of user pins without lowering the failure detection rate. Therefore, according to the scan circuit of the present invention, by increasing the scan pins,
Since the number of pins of the LSI chip does not increase, it is particularly effective for LSI chips with a pin number neck, and by increasing the number of scan chains, the number of test vector steps is reduced and the test time is reduced. Since it can be reduced, it is particularly effective for creating test vectors for large-scale circuits.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a circuit using a scan circuit of the present invention.

2A and 2B are configuration circuit diagrams of an embodiment of a circuit before the combined use of the scan-in and the output pin and after the combined use of the scan circuit of the present invention.

3A and 3B are configuration circuit diagrams of an embodiment of a circuit before the combined use of the scan-in and 3S output pins and after the combined use of the scan circuit of the present invention.

FIGS. 4A and 4B are configuration circuit diagrams of an embodiment of a circuit before the combined use of the scan-in and IO pins and after the combined use of the scan circuit of the present invention.

5A and 5B are configuration circuit diagrams of an embodiment of a circuit before the combined use of the scan-out and the input pin and after the combined use of the scan circuit of the present invention.

6A and 6B are configuration circuit diagrams of an embodiment of a circuit before the combined use of the scan-out and 3S output pins and after the combined use of the scan circuit of the present invention.

7A and 7B are configuration circuit diagrams of an embodiment of a circuit before the combined use of the scan-out and IO pins and after the combined use of the scan circuit of the present invention.

8A and 8B are configuration circuit diagrams of an embodiment of a circuit before the combined use of the scan enable and the input pin and after the combined use of the scan circuit of the present invention.

9A and 9B are configuration circuit diagrams of an embodiment of a circuit before the combined use of the scan enable and the output pin and after the combined use of the scan circuit of the present invention.

10A and 10B are configuration circuit diagrams of an embodiment of a circuit before the combined use of the scan enable and the 3S output pin and after the combined use of the scan circuit of the present invention.

11A and 11B are configuration circuit diagrams of an embodiment of a circuit before the combined use of the scan enable and the IO pin and after the combined use of the scan circuit of the present invention.

FIG. 12 is a block diagram of an example of a circuit using a scan circuit.

FIG. 13 is a configuration circuit diagram of an example of a scan flip-flop.

14 (a) and 14 (b) are configuration circuit diagrams of an example of a circuit before and after being used as a scan-in and an input pin, respectively.

15 (a) and 15 (b) are configuration circuit diagrams of an example of a circuit before and after being used as a scanout and an output pin, respectively.

[Explanation of symbols]

 10, 24 circuit 12, 14 combination circuit 16, 26 scan circuit 18 scan flip-flop 20, 32, 42, 46, 50 multiplexer 22, 34, 48 D-type flip-flop 28 output pin 30 IO (input / output) pin 36 output Buffer 38 Input buffer 40 3S (three-state) output buffer 44 Input pin

Claims (1)

[Claims] 1. A scan pin which is also used as a user pin,
It has a scan chain in which a plurality of scan flip-flops controlled by the scan pins are connected in series, and a scan flip-flop additionally inserted in the scan chain. The internal circuit is controlled by the input signal input to the input terminal, the output signal output from the internal circuit is observed by the output signal output from the user pin, and the scan additionally inserted during the scan operation. The first output signal output from the flip-flop for
A scan circuit which controls the internal circuit and observes an output signal output from the internal circuit by a second output signal output from the additionally inserted scan flip-flop.