JPH098230A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To reduce the manufacturing cost of a semiconductor integrated circuit device mounted with a differential amplifier circuit. CONSTITUTION: In a semiconductor integrated circuit device mounted with a differential amplifier circuit, a variable capacitance C whose capacitance value is controlled by the control potential applied to the external terminals for control potential is added to the resistance element R for load of the differential amplifier circuit. The variable capacitance C is constituted of a depletion area 14 whose expansion width is controlled by the control potential and the resistance element R for load is constituted of a polycrystalline silicon film 8 formed on a semiconductor area 3 across which the control potential is applied with an insulating film 7 in between. In addition, the resistance element R is constituted of a second semiconductor area of a second conductivity formed on the main surface of a first semiconductor area 3 of a first conductivity across which the control potential is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a differential amplifier circuit mounted thereon.

[0002]

2. Description of the Related Art As a semiconductor integrated circuit device used for optical communication, for example, a semiconductor integrated circuit device used for interfacing with an E / O converter is equipped with a differential amplifier circuit. Waveform distortion and ringing are likely to occur in the output signal output from the output terminal of the differential amplifier circuit due to the influence of the output external terminal (bonding pad) and the package. Since the waveform distortion and ringing of the output signal determine the performance of the system, it is necessary to supply the system with a semiconductor integrated circuit device in which the waveform distortion and ringing of the output signal are minimized.

However, it is difficult to accurately reflect the influence of the output external terminal and the package on the circuit simulation, and it is extremely difficult to predict the waveform distortion and ringing of the output signal at the trial production stage. Therefore, after measuring the characteristics of the semiconductor integrated circuit device, this measurement data is fed back to the design, and the semiconductor integrated circuit device is recreated repeatedly.

[0004]

SUMMARY OF THE INVENTION The semiconductor integrated circuit device described above.
Is the output signal output from the output terminal of the differential amplifier circuit.
In order to minimize the waveform distortion and ringing that occur in the
Repeated design and trial production. For this reason,
From product to product shipment (TAT:TurnAround
Time) becomes longer and the manufacturing cost of the semiconductor integrated circuit device increases.
There was a problem of increase.

An object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor integrated circuit device equipped with a differential amplifier circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In a semiconductor integrated circuit device having a differential amplifier circuit mounted thereon, the capacitance value is controlled by a control potential applied to a load resistance element of the differential amplifier circuit by a control potential external terminal (bonding pad). Variable capacity is added.

[0009]

According to the above-mentioned means, the frequency band of the differential amplifier circuit can be adjusted from the outside by the control potential applied to the control potential external terminal, so that the output external terminal (bonding pad) or the package can be adjusted. Due to the influence, it is possible to control the waveform distortion and ringing that occur in the output signal output from the output terminal of the differential amplifier circuit. As a result, the repetition of designing and prototyping can be eliminated, and the time required from the design of semiconductor integrated circuit devices to product shipment (TA
Since T) can be shortened, the manufacturing cost of the semiconductor integrated circuit device on which the differential amplifier circuit is mounted can be reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below together with the embodiments in which the present invention is applied to a semiconductor integrated circuit device.

In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) A semiconductor integrated circuit device which is Embodiment 1 of the present invention has a multiplexer circuit 30 mounted thereon as shown in FIG. 1 (block diagram). A semiconductor integrated circuit device equipped with this multiplexer circuit 30 has an E /
Used to interface with O-converter.

The multiplexer circuit 30 includes a data input circuit 32A, a data input circuit 32B, a data input circuit 32C, a data input circuit 32D, a multiplexing circuit 33A, a multiplexing circuit 33B, a multiplexing circuit 33C, and a data output circuit 3.
4, a clock input circuit 35 and an internal circuit 36.

A data signal applied to the data input external terminal 31A is supplied to the data input circuit 32A,
The data input circuit 32B has a data input external terminal 3
1B is supplied with the data signal, the data input circuit 32C is supplied with the data signal applied to the data input external terminal 31C, and the data input circuit 32D is supplied with the data signal.
Is supplied with the data signal applied to the data input external terminal 31D. The clock signal applied to the clock input external terminal 37 is supplied to the clock input circuit 35.

The data output circuit 34 is composed of a differential amplifier circuit 20, as shown in FIG. 2 (equivalent circuit diagram).
That is, the semiconductor integrated circuit device mounts the differential amplifier circuit 20. The differential amplifier circuit 20 is composed of two load resistance elements R and two bipolar transistors Tr. Two
One end side of each of the load resistance elements R is connected to the external terminal (bonding pad) 23 for the reference power source, and the other end side of each of the two load resistance elements R is a collector region of each of the two bipolar transistors Tr. Connected to.

The emitter regions of the two bipolar transistors Tr are connected to the external terminals (bonding pads) 24 for the operating power supply, and the base region of one of the bipolar transistors Tr is the input terminal 2 of the differential amplifier circuit 20.
The base region of the other bipolar transistor Tr is connected to the input terminal 21B of the differential amplifier circuit 20. Operational amplifier circuit 2 between one load resistance element R and one bipolar transistor Tr collector region
The 0 output terminal 22A is connected to the output external terminal (bonding pad) 38 shown in FIG.

The reference power source external terminal 23 has, for example, 0
The potential of [V] is applied, and the external terminal for the operating power supply 24
For example, a potential of −3 to −5 [V] is applied. The multiplexer circuit 3 is connected to the input terminal 21A of the differential amplifier circuit 20.
A data signal is applied from 3C, and the differential amplifier circuit 20
A data signal is applied to the input terminal 21B from the multiplexing circuit 33C.

As shown in FIG. 3 (plan view of the main part) and FIG. 4 (cross-sectional view taken along the line AA shown in FIG. 3), the one load resistance element R is provided on the semiconductor substrate 1. It is formed on the main surface of the first active region. The first active region of the semiconductor substrate 1 is surrounded by the insulating film 1B, the field insulating film 4, and the insulating film 6 buried in the isolation groove 5, and is electrically isolated from other active regions. .

The semiconductor substrate 1 is a so-called S in which a semiconductor layer 1C is laminated on the main surface of a supporting substrate 1A with an insulating film 1B interposed.
OI composed (S emiconductor O n I nsulator) structure. The support substrate 1A is formed of, for example, a p-type semiconductor substrate made of single crystal silicon. The insulating film 1B is formed of, for example, a silicon oxide film. The semiconductor layer 1C is obtained by growing an epitaxial layer on the main surface of a semiconductor substrate made of, for example, single crystal silicon.
It is composed of layers.

An n-type semiconductor region (n-type well region) 3 is formed on the main surface of the first active region of the semiconductor substrate 1, and an n + -type semiconductor region is provided between the n-type semiconductor region 3 and the insulating film 1B. Two
Is formed.

The one load resistance element R is composed of, for example, a polycrystalline silicon film 8 into which impurities are introduced for the purpose of controlling the resistance value. The polycrystalline silicon film 8 is the insulating film 7
Is formed on the main surface of n-type semiconductor region 3. The upper surface and the side surface of the polycrystalline silicon film 8 are covered with an insulating film 9, and the wiring 1 is provided on one end side of the polycrystalline silicon film 8 through a connection hole 12A formed in each of the insulating film 11, the insulating film 10, and the insulating film 8.
3A is electrically connected, and the insulating film 11,
Connection hole 12B formed in each of insulating film 10 and insulating film 9
The wiring 13B is electrically connected through. Wiring 13
Each of A and the wiring 13B is formed of, for example, a metal film.

Although not shown, the other load resistance element R is an insulating film 1B, a field insulating film 4, and a separation groove 5.
It is formed on the main surface of the second active region of the semiconductor substrate 1 whose periphery is defined by the respective insulating films 6 embedded therein. The other load resistance element R is the above-mentioned one load resistance element R.
The configuration is the same as

In the first active region of the semiconductor substrate 1, the wiring 13C is electrically connected to the n-type semiconductor region 3 through the connection holes 12C formed in the insulating film 11 and the insulating film 10, respectively. This wiring 13C is the above-mentioned wiring 13A.
Is formed in the same step as above and is electrically connected to a control potential external terminal (bonding pad) 25A to which the first control potential is applied.

In the second active region of the semiconductor substrate 1, the n-type semiconductor region (3) has an insulating film (11) and an insulating film.
The wiring is electrically connected through the connection holes formed in each of (10). This wiring is formed in the same step as the wiring 13C described above, and is electrically connected to the control potential external terminal (bonding pad: 25B) to which the second control potential is applied.

A variable capacitance C is added to the one load resistance element R. The variable capacitor C is composed of a depletion region (depletion layer) 14 formed on the main surface of the n-type semiconductor region 3 below the polycrystalline silicon film 8 in the first active region of the semiconductor substrate 1. The depletion region 14 is formed at the potential applied to the polycrystalline silicon film 8 and spreads (depth) at the first control potential applied from the control potential external terminal 25A to the n-type semiconductor region 3 through the wiring 13C. Direction width) is controlled. That is, as shown in FIG. 2, the variable capacitance C added to one load resistance element R of the differential amplifier circuit 20 has a capacitance value controlled by the first control potential applied to the control potential external terminal 25A. To be done. In this way, the variable capacitance C whose capacitance value is controlled by the first control potential applied to the control potential external terminal 25A.
Is added to one of the load resistance elements R, the frequency band of the differential amplifier circuit 20 can be adjusted from the outside with the first control potential applied to the control potential external terminal 25A. It is possible to control the waveform distortion and ringing that occur in the output signal output from the output terminal 22A of the operational amplifier circuit 20 under the influence of the terminal 38 and the package.

A variable capacitance C is added to the other load resistance element R as in the case of the one load resistance element R. The variable capacitor C is composed of a depletion region (14) formed on the main surface of the n-type semiconductor region (3) under the polycrystalline silicon film (8) in the second active region of the semiconductor substrate 1. This depletion region
(14) is formed by the potential applied to the polycrystalline silicon film (8) and spreads by the second control potential applied to the n-type semiconductor region (3) from the control potential external terminal (25B) through the wiring. The width (width in the depth direction) is controlled. That is, the variable capacitance C added to the other load resistance element R of the differential amplifier circuit 20.
As shown in FIG. 2, the capacitance value is controlled by the second control potential applied to the control potential external terminal 25B. In this way, by adding the variable capacitance C whose capacitance value is controlled by the second control potential applied to the control potential external terminal 25B to the other load resistance element R, the control potential external terminal 25 is formed.
Since the frequency band of the differential amplifier circuit 20 can be externally adjusted by the second control potential applied to B, it is output from the output terminal 22A of the differential amplifier circuit under the influence of the external output terminal 38 and the package. It is possible to control the waveform distortion and ringing that occur in the output signal.

One of the bipolar transistors Tr
(Not shown) is formed on the main surface of the third active region of the semiconductor substrate 1 whose periphery is defined by the insulating film 1B, the field insulating film 4, and the insulating film 6 buried in the isolation trench 5. To be done. The one bipolar transistor Tr is, for example, an npn-type transistor in which an n-type emitter region, a p-type base region, and an n-type collector region are sequentially arranged from the main surface of the third active region of the semiconductor substrate 1 in the depth direction. Composed of.

The other bipolar transistor Tr
(Not shown) is formed on the main surface of the fourth active region of the semiconductor substrate 1 whose periphery is defined by the insulating film 1B, the field insulating film 4, and the insulating film 6 buried in the isolation trench 5. To be done. The other bipolar transistor Tr is of npn type like the one bipolar transistor Tr described above.

As described above, according to this embodiment, the following operational effects can be obtained.

(1) In the differential amplifier circuit 20, one load resistance element R has a variable capacitance C whose capacitance value is controlled by a first control potential applied to a control potential external terminal (bonding pad) 25A. , Or one load resistance element R
To the control potential external terminal (bonding pad) 25B
By adding the variable capacitor C whose capacitance value is controlled by the second control potential applied to the control potential external terminal 25A.
Control potential or external terminal 25 for control potential applied to the
Since the frequency band of the differential amplifier circuit 20 can be adjusted from the outside by the second control potential applied to B, it is output from the output terminal 22A of the differential amplifier circuit 20 due to the output external terminal 38 and the package. It is possible to control the waveform distortion and ringing that occur in the output signal. As a result, the repetition of designing and prototyping can be eliminated, and the time required from the design of semiconductor integrated circuit devices to product shipment (T
Since (AT) can be shortened, the manufacturing cost of the semiconductor integrated circuit device can be reduced.

By adjusting the frequency band of the differential amplifier circuit 20 from the outside by the first control potential applied to the control potential external terminal 25A or the second control potential applied to the control potential external terminal 25B. Even if element characteristics vary in the manufacturing process of the semiconductor integrated circuit device, the characteristics of the output signal output from the output terminal 22A of the differential amplifier circuit 20 can be made the same.

(2) By configuring one variable capacitance C in the depletion region 14 whose spread width is controlled by the first control potential applied to the control potential external terminal 25A, the capacitance value at the first control potential is set. It is possible to add the variable capacitance C whose C is controlled to one of the load resistance elements R.

Further, the other variable capacitor C is constituted by the depletion region 14 whose spreading width is controlled by the second control potential applied to the control potential external terminal 25B, so that the capacitance value is controlled by the second control potential. The controlled variable capacitance C can be added to the other load resistance element R.

(3) By constructing one of the load resistance elements R by the polycrystalline silicon film 8 formed on the n-type semiconductor region 3 to which the first control potential is applied, with the insulating film 7 interposed therebetween. A variable capacitance C whose capacitance value is controlled by the width of the depletion region 14 can be added to one of the load resistance elements R.

Further, the other load resistance element R is provided on the n-type semiconductor region (3) to which the second control potential is applied, on the insulating film (7).
By using the polycrystalline silicon film (8) formed with the interposition therebetween, the variable capacitance C whose capacitance value is controlled by the width of the depletion region 14 can be added to the other load resistance element R. .

(4) A variable capacitance C whose capacitance value is controlled by the first control potential applied to the control potential external terminal 25A is added to one load resistance element R of the differential amplifier circuit 20,
By adding a variable capacitance C whose capacitance value is controlled by the second control potential applied to the control potential external terminal 24B to the other load resistance element R of the differential amplification circuit 20, for example, the differential amplification circuit It is possible to control the waveform distortion and ringing that occur in the positive-phase output signal output from the output terminal 22A of the differential amplifier 20 and, for example, the output terminal 2 of the differential amplifier circuit 20.
It is possible to control the waveform distortion and ringing that occur in the negative phase output signal output from 2B.

(Embodiment 2) A semiconductor integrated circuit device according to a second embodiment of the present invention is equipped with a multiplexer circuit 30 shown in FIG. The data output circuit 34 of the multiplexer circuit 30 is composed of the differential amplifier circuit 20 shown in FIG.

The differential amplifier circuit 20 is composed of two load resistance elements R and two bipolar transistors Tr. Each of the two bipolar transistors Tr is configured similarly to the above-described first embodiment.

As shown in FIG. 5 (plan view of the main part) and FIG. 6 (cross-sectional view taken along the line BB shown in FIG. 5), the one resistance element R for load is of the semiconductor substrate 1. It is formed on the main surface of the first active region. The first active region of the semiconductor substrate 1 is surrounded by the insulating film 1B, the field insulating film 4, and the insulating film 6 buried in the isolation groove 5, and is electrically isolated from other active regions. .

An n-type semiconductor region (n-type well region) 3 is formed on the main surface of the first active region of the semiconductor substrate 1, and the insulating film 11 and the insulating film 10 are formed in the n-type semiconductor region 3. The wiring 13F is electrically connected through the formed connection hole 12F. The wiring 13F is electrically connected to a control potential external terminal (bonding pad) 25A to which the first control potential is applied.

The one load resistance element R is, for example, n
P-type semiconductor region 15 formed on the main surface of the type semiconductor region 3
It consists of. A connection hole 12D formed in each of the insulating film 11 and the insulating film 10 on one end side of the p-type semiconductor region 15
A wiring 13D is electrically connected through the connection hole 1 and a connection hole 1 formed in each of the insulating film 12 and the insulating film 11 on the other end side.
The wiring 13E is electrically connected through 2E.

Although not shown, the other load resistance element R is an insulating film 1B, a field insulating film 4, and a separation groove 5.
It is formed on the main surface of the second active region of the semiconductor substrate 1, the periphery of which is defined by the insulating films 6 embedded therein. An n-type semiconductor region is formed on the main surface of the second active region of the semiconductor substrate 1.
(3) is formed, and the second control potential is applied to the n-type semiconductor region (3) from the control potential external terminal (bonding pad: 25B).

A variable capacitance C is added to the one load resistance element R. The variable capacitance C is composed of a depletion region 14 formed in the pn junction between the p-type semiconductor region 15 and the n-type semiconductor region 3 in the first active region of the semiconductor substrate 1. The spread width (width in the depth direction) of the depletion region 14 is controlled by the first control potential applied to the n-type semiconductor region 3 from the control potential external terminal 25A through the wiring 13F. That is, as shown in FIG. 2, the variable capacitance C added to one load resistance element R of the differential amplifier circuit 20 has a capacitance value controlled by the first control potential applied to the control potential external terminal 25A. To be done. In this way, by adding the variable capacitance C whose capacitance value is controlled by the first control potential applied to the control potential external terminal 25A to one of the load resistance elements R, the voltage is applied to the control potential external terminal 25A. First done
The frequency band of the differential amplifier circuit 20 can be adjusted from the outside with the control potential, and the output external terminal (bonding pad)
It is possible to control the waveform distortion and ringing that occur in the output signal output from the output terminal 22A of the differential amplifier circuit 20 due to the influence of 38 and the package.

A variable resistance element C is added to the other load resistance element R, similarly to the one load resistance element R. The variable resistance element R is composed of a depletion region 14 formed at a pn junction between the p-type semiconductor region (15) and the n-type semiconductor region (3) in the second active region of the semiconductor substrate 1. . The depletion region 14 is an external terminal for control potential.
The spread width (width in the depth direction) is controlled by the second control potential applied from (25B) to the n-type semiconductor region (3) through the wiring. That is, the variable capacitance C added to the other load resistance element R of the differential amplifier circuit 20 is, as shown in FIG.
The capacitance value is controlled by the second control potential applied to the control potential external terminal 25B. In this way, by adding the variable capacitance C whose capacitance value is controlled by the second control potential applied to the control potential external terminal 25B to one of the load resistance elements R, it is applied to the control potential external terminal 25B. The second control potential can adjust the frequency band of the differential amplifier circuit 20 from the outside, and the waveform distortion or the like generated in the output signal output from the output external terminal 38 due to the influence of the output external terminal 38 or the package. The ringing can be controlled.

As described above, according to this embodiment, the same operational effects as those of the above-mentioned embodiments can be obtained.

As described above, the invention made by the present inventor is:
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0047]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

The manufacturing cost of the semiconductor integrated circuit device on which the differential amplifier circuit is mounted can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiplexer circuit mounted in a semiconductor integrated circuit device that is Embodiment 1 of the present invention.

FIG. 2 is an equivalent circuit diagram of a differential amplifier circuit that constitutes a data input circuit of the multiplexer circuit.

FIG. 3 is a plan view of a main part of the semiconductor integrated circuit device.

4 is a cross-sectional view taken along the line AA shown in FIG.

FIG. 5 is a plan view of a main portion of a semiconductor integrated circuit device that is Embodiment 2 of the present invention.

6 is a cross-sectional view taken along the line BB shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor base, 1A ... Support substrate, 1B ... Insulating film, 1C
... semiconductor layer, 2 ... n + type semiconductor region, 3 ... n type semiconductor region, 4 ... field insulating film, 5 ... isolation groove, 6 ... insulating film,
7 ... Insulating film, 8 ... Polycrystalline silicon film, 9 ... Insulating film, 10 ... Insulating film, 11 ... Insulating film, 12A, 12B, 12C, 12
D, 12E, 12F ... Connection hole, 13A, 13B, 13
C, 13D, 13E, 13F ... Wiring, 14 ... Depletion region,
15 ... P-type semiconductor region, 20 ... Differential amplifier circuit, 21A,
21B ... input terminal, 22A, 22B ... output terminal, 23 ...
External terminal for reference power source, 24 ... External terminal for operating power source, 25
A, 25B ... External terminal for control potential, 30 ... Multiplexer circuit, 34 ... Data output circuit.

Claims (4)

[Claims] 1. A semiconductor integrated circuit device mounting a differential amplifier circuit, wherein a load resistance element of the differential amplifier circuit comprises:
A semiconductor integrated circuit device comprising a variable capacitance whose capacitance value is controlled by a control potential applied to an external terminal for control potential. 2. The semiconductor integrated circuit device according to claim 1, wherein the variable capacitor is composed of a depletion region whose spread width is controlled by a control potential. 3. The load resistance element is composed of a polycrystalline silicon film formed with an insulating film interposed on a semiconductor region to which a control potential is applied. Semiconductor integrated circuit device. 4. The load resistance element is composed of a second conductivity type second semiconductor region formed on a main surface of a first conductivity type first semiconductor region to which a control potential is applied. The semiconductor integrated circuit device according to claim 1.