JPH0981528A - Multiprocessor system, method and device for interrupt control used in the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a processor having the lightest load execute the interrupt handling. SOLUTION: Memory access counters 4 to 6 count frequencies in cache mishit memory access of processors 1 to 3, respectively. A comparator 22 compares counted numerical values of memory access counters 4 to 6 and outputs a processor select signal 24 which instructs selection of the processor corresponding to the memory access counter whose counted numerical value is smallest. An interrupt controller 29 controls various interrupt signals in a set priority order to output an interrupt signal 32. An interrupt selector 21 distributes this interrupt signal to the processor indicated by the processor select signal 24. This invention takes frequencies in memory access of processor units which are continuously changed with time, as the determinant of interrupt handling processor selection in this manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control method for a multiprocessor system having a plurality of processors,
In particular, the present invention relates to a method for automatically realizing optimum interrupt distribution control by changing the interrupt processing processor on the basis of the number of cache miss hit memory accesses for each processor.

[0002]

2. Description of the Related Art In many conventional multiprocessor systems, interrupt distribution has been realized by the following method. A method in which a specific processor centrally processes I / O interrupts, a method in which the interrupt priority is programmed by software (OS, etc.), and a method in which the interrupt destination is changed based on the number of interrupt waits in the interrupt queue , A method of changing the interrupt processing processor according to the priority of the execution process of each processor, a method of changing the interrupt processing processor by a round-robin arbitration method, and a method combining a plurality of the above methods.

For example, in Japanese Patent Laid-Open No. 4-328665 (hereinafter, referred to as prior art 1), an interrupt arbitration is performed by using a parameter indicating a load condition of a processor as a first interrupt priority PPR, and this arbitration is performed. When a processor is not decided by, the processor is selected according to the second interrupt priority RRPR which additionally cyclically changes, whereby the input / output interrupt is distributed to each processor. And its interrupt arbitration device ". That is, this prior art discloses a method in which the above method and the above method are combined among the above methods.

Further, in Japanese Patent Laid-Open No. 61-110241 (hereinafter referred to as prior art 2), the load of interrupt processing is distributed by setting an interrupt destination to a plurality of arbitrary processors, and an overhead due to unnecessary interrupts. A "multiprocessor interrupt control device" for reducing the above has been disclosed.

[0005]

In the above-mentioned conventional interrupt control method, in a method in which a specific processor concentrates input / output interrupt processing, the input / output processing concentrates on one processor, so that the system A performance bottleneck occurs in I / O interrupt processing. As the number of multiprocessors increases, the load on the interrupt processing processor increases at an accelerating rate, which hinders improvement in system performance.

In the method of designating the interrupt destination by software, real-time load distribution becomes difficult as compared with hardware control. Further, it consumes extra system resources that are not originally needed to perform load monitoring. This drawback applies to the above schemes and schemes as well.

Since the system based on the round-robin arbitration system does not reflect the load state of the system, the interrupt processing is evenly allocated to the processor with a high load, and the optimum interrupt distribution control is Hard to say.

Further, the above-described methods (1) to (3) cannot be combined to solve the individual problems associated with the above methods (1) to (3). In other words, the combination of a plurality of methods has its own problems. Therefore, the prior art 1 has the individual problems of the combined system.

Prior art 2 only discloses a technique for distributing the load of interrupt processing, and does not disclose or suggest any concrete means for "optimally" distributing the load of interrupt processing. Absent.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiprocessor system and an interrupt control method capable of causing a processor with the lightest load to execute interrupt processing in order to solve the above problems.

Another object of the present invention is to provide a multiprocessor system and an interrupt control method capable of effectively utilizing processor resources and improving throughput.

Still another object of the present invention is to provide a multiprocessor system and an interrupt control method capable of executing interrupt processing having a strong real-time property at high speed and improving the response of the system.

[0013]

According to the present invention, there is provided a multiprocessor system including first to Nth processors including first to Nth (N is an integer of 2 or more) cache memories, respectively. , The first to Nth memory access counters that count the number of cache miss hit memory accesses of the first to Nth processors and the first to Nth memory access counters are compared, and the lowest count value is obtained. A comparator that outputs a processor select signal that instructs the selection of a processor corresponding to the memory access counter, an interrupt controller that outputs various interrupt signals by controlling various interrupt signals in the set priority order, and an interrupt signal. With an interrupt selector for allocating to the processor designated by the processor select signal. The number of memory accesses continue varying the processor unit, a multiprocessor system is obtained, characterized in that the determining factor of the interrupt processing processor selection.

In the above multiprocessor system,
Further, it is desirable to include a timer for resetting the first to Nth memory access counters every time a predetermined time has elapsed.

Further, according to the present invention, an interrupt control used in a multiprocessor system including first to Nth processors including first to Nth (N is an integer of 2 or more) cache memories, respectively. In the device, the first
To the Nth memory access counter that counts the number of cache miss hit memory accesses of the Nth to Nth processors, and the memory access counter having the lowest count value by comparing the count values of the first to Nth memory access counters A comparator that outputs a processor select signal for instructing the selection of a processor corresponding to, an interrupt controller that outputs various interrupt signals by controlling various interrupt signals in the set priority order, and an interrupt signal An interrupt selector for allocating to a processor designated by a select signal, and the number of memory accesses per processor that changes continuously in time is used as a deciding factor for selecting an interrupt processing processor. An interrupt controller is obtained.

In the above interrupt control device, further, the first
It is preferable to include a timer for resetting the Nth to Nth memory access counters every time a fixed time elapses.

According to the present invention, in an interrupt control method of a multiprocessor system including a plurality of processors each including a cache memory, the steps of counting the number of cache miss hit memory accesses in a constant time unit for each processor, An interrupt control method of a multiprocessor system including a step of evaluating a processor load state based on a count value and a step of deciding an input / output interrupt destination of a processor based on the result of the evaluation is obtained.

Further, according to the present invention, in an interrupt control method of a multiprocessor system having a plurality of processors each including a cache memory, a step of measuring a load state of the cache memory and an interrupt based on the measurement result. Controlling the selector to cause the processor with the lightest load to execute the interrupt processing, thereby providing an interrupt control method for a multiprocessor system.

[0019]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the configuration of a multiprocessor system according to an embodiment of the present invention. The illustrated multiprocessor system is a tightly coupled symmetric multiprocessor system in which first to third processors 1, 2, 3 are connected to a main memory 17 via a memory bus 10. Here, “symmetric” means that a plurality of processors have the same “function”. That is, no access restriction or control restriction is applied to a specific device. In the case of a symmetric multiprocessor system, the "performance" of the processor is not particularly limited, but normally, a plurality of processors having the same performance are provided.

The first to third processors 1 to 3 respectively include the first to third cache memories 14, 15 and 1.
Including 6. First to third memory bus arbiters 7, 8 and 9 are connected to the first to third processors 1 to 3, respectively. Also, the first to third processors 1 to 3
First to third memory access counters 4, 5 and 6 are connected to 3, respectively. The first to third memory access counters 4 to 6 are connected to the comparator 22 and the timer 23. The comparator 22 is connected to the timer 23. The comparator 22 is connected to the interrupt selector 21, and the interrupt selector 21 is connected to the first to third processors 1 to 3. The interrupt selector 21 is also connected to the interrupt controller 27, and the interrupt controller 27 includes the first to fourth interrupt controllers.
Are connected to the input / output control devices 28, 29, 30, 31.

Here, the first to third memory access counters 4, 5, and 6, the comparator 22, the timer 23, the interrupt selector 21, and the interrupt controller 27 constitute an interrupt control device. It

The need for memory access arises in the first to third processors 1 to 3, and the first to third processors respectively
As a result of searching the data in the cache memories 14 to 16, it is determined that the necessary data does not exist in the first to third cache memories 14 to 16. In such a case, the first to third processors 1 to 3 access the main memory 17. In order to access the main memory 17, the first to third processors 1 to 3 are respectively provided with the respective first to third bus request signals 1
1, 12 and 13 are assigned to the first to third memory arbiters 7 to 9
Issue to The first to third memory arbiters 7-9 are
The first to third processors 1 to 3 respectively
Through to determine the usage right for the memory bus 10 while adjusting the third bus request signals 11 to 13.

At the same time, the first to third memory access counters 4 to 6 monitor the first to third bus request signals 11 to 13, respectively, and the first to third bus request signals 11 to 13 respectively. Whenever occurs, the first to third count values are incremented by one. The first to third count values in the first to third memory access counters 4 to 6 are input to the comparator 22 and evaluated there. The evaluation criterion here indicates that the processor corresponding to the memory access counter having the smallest numerical value among the first to third count numerical values is the processor having the smallest work load at that time. Each time the timing pulse 25 is received from the timer 23, the comparator 22 performs the load evaluation, and outputs the processor select signal 24 indicating the processor number of the processor with the lightest work load to the interrupt selector 21.
Tell. At the same time when the timing pulse 25 is generated, the timer 23 sends a count reset signal 26 to the first to third memory access counters 4 to 6 to set the first to third count numerical values to an initial value, that is, " Reset to 0 ".

On the other hand, the first to fourth input / output control devices 28
31 to 31 issue an interrupt signal for an interrupt processing request to the interrupt controller 27 as required. The interrupt controller 27 sends out a main interrupt signal 32 to the interrupt selector 21 according to a pre-programmed interrupt priority processing procedure, and at the same time, an internal interrupt factor register (Fig. (Not shown)
Set. In response to the processor select signal 24 output from the comparator 22, the interrupt selector 21 outputs the main interrupt signal 32 output from the interrupt controller 27 to one of the first to third processors 1 to 3 ( 1) for the processor indicated by the processor select signal 24)
To any one of the third processor interrupt signals 18 to 20
Distribute through one.

In order to realize the accurate interrupt processing of the processor, the interrupt selector 21 of the processor, once setting any one of the first to third processor interrupt signals 18 to 20 to the active state, After the completion of the interrupt factor reading process from the interrupt factor register, the process of changing the interrupt destination is performed according to the instruction of the next processor select signal 24. The processor receiving any of the first to third processor interrupt signals 18 to 20 reads the interrupt factor held in the interrupt factor register in the interrupt controller 27 and executes appropriate interrupt processing. .

FIG. 2 shows an example of the interrupt control operation of the multiprocessor system of FIG. Here, the first to third processors 1 to 3 are referred to as a processor A, a processor B, and a processor C, respectively. The first to third bus request signals 11 to 13 are called a processor A bus request, a processor B bus request, and a processor C bus request, respectively. The first to third memory access counters 4 to 6 are called a memory access counter A, a memory access counter C, and a memory access counter C, respectively. The timing pulse 25 and the counter reset signal 26 output from the timer 23 are collectively called a timer pulse. Further, the processor A interrupts the first to third processor interrupt signals 18 to 20, respectively.
Called processor B interrupt and processor C interrupt.

First, it is assumed that the comparator 22 outputs a signal for instructing the selection of the processor A as the processor select signal 24. This is the first period T1 from the timer 22 to the first time point t1 when the next timer pulse is generated,
The comparator 22 continues to output the processor select signal 24 instructing the selection of the processor A. Therefore, during the first period T1, the main interrupt signal 32 output from the interrupt controller 27 is distributed to the processor A as the processor A interrupt by the interrupt selector 21.

In response to the timer pulse generated at the first time point t1, the comparator 22 causes the memory access counters A ...
Compare the count values of C. In this example, since the count value of the memory access counter A is “3”, the count value of the memory access counter B is “5”, and the count value of the memory access counter C is “1”, the smallest count value is shown. Is a memory access counter C. Therefore, the comparator 22 outputs a signal instructing the selection of the processor C as the processor select signal 24. At the same time, the count values of the memory access counters A to C are reset to the initial value "0". During the second period T2 from the first time point t1 to the second time point t2 when the next timer pulse is generated, the comparator 22 continues to output the processor select signal 24 instructing the selection of the processor C. Therefore, during the second period T2, the main interrupt signal 32 output from the interrupt controller 27 is distributed to the processor C as the processor C interrupt by the interrupt selector 21.

In response to the timer pulse generated at the second time point t2, the comparator 22 causes the memory access counters A ...
Compare the count values of C. In this example, since the count value of the memory access counter A is "7", the count value of the memory access counter B is "1", and the count value of the memory access counter C is "2", the smallest count value is shown. Is a memory access counter B. Therefore, the comparator 22 outputs a signal instructing the selection of the processor B as the processor select signal 24. At the same time, the count values of the memory access counters A to C are reset to the initial value "0". During the third period T3 from the second time point t2 to the third time point (not shown) when the next timer pulse is generated, the comparator 22 outputs the processor select signal 2 for instructing the selection of the processor B.
Continue to output 4. Therefore, this third period T3,
Main interrupt signal 3 output from interrupt controller 27
2 is distributed to the processor B as the processor B interrupt by the interrupt selector 21.

It is needless to say that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, it goes without saying that the number of processors is not limited to three.

[0032]

As described above, according to the present invention, the memory load state, which is an index representing the processor load, is measured,
By controlling the interrupt selector based on the measurement results and causing the processor with the lightest load to execute interrupt processing, not only can throughput be improved by effective use of processor resources in a multiprocessor system, but also interrupt processing with strong real-time characteristics. It is possible to improve the response of the system by executing the at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing an interrupt control operation of the multiprocessor system shown in FIG.

[Explanation of symbols]

 1,2,3 Processor 4,5,6 Memory Access Counter 7,8,9 Memory Bus Arbiter 10 Memory Bus 14,15,16 Cache Memory 17 Main Memory 21 Interrupt Selector 22 Comparator 23 Timer 27 Interrupt Controller 28 , 29, 30, 31 Input / output control device

Claims (6)

[Claims] 1. A multiprocessor system including first to Nth processors each including a first to Nth (N is an integer of 2 or more) cache memory, wherein each of the first to Nth processors is provided. The first to Nth memory access counters that count the number of cache-miss memory accesses and the count values of the first to Nth memory access counters are compared, and the processor corresponding to the memory access counter having the lowest count value is compared. A comparator that outputs a processor select signal for instructing selection, an interrupt controller that outputs various interrupt signals by controlling various interrupt signals in the set priority order, and the interrupt signal by the processor select signal. It has an interrupt selector for allocating to the designated processor and changes continuously in time. Multiprocessor system, characterized in that the number of memory accesses of the processor unit, a determining factor of the interrupt processing processor selection. 2. The multiprocessor system according to claim 1, further comprising a timer for resetting the first to Nth memory access counters every elapse of a predetermined time. 3. An interrupt control device used in a multiprocessor system including first to Nth processors including first to Nth (N is an integer of 2 or more) cache memories, respectively. The first to Nth memory access counters for counting the number of cache miss hit memory accesses of the first to Nth processors are compared with the count values of the first to Nth memory access counters, and the highest count value is obtained. A comparator that outputs a processor select signal that instructs selection of a processor corresponding to a low memory access counter, an interrupt controller that outputs various interrupt signals by controlling various interrupt signals in the order of set priority, and the interrupt controller. An interrupt selector for allocating an interrupt signal to the processor designated by the processor select signal, Between to memory access count continuously varying processor unit, an interrupt controller, characterized in that the determining factor of the interrupt processing processor selection. 4. The interrupt control device according to claim 3, further comprising a timer for resetting the first to Nth memory access counters every time a predetermined time elapses. 5. In an interrupt control method of a multiprocessor system having a plurality of processors each including a cache memory, a step of counting the number of times of cache mishit memory access in a fixed time unit for each processor, and based on the count value An interrupt control method for a multiprocessor system, comprising: a step of evaluating a processor load state; and a step of determining an input / output interrupt destination of a processor according to a result of the evaluation. 6. An interrupt control method for a multiprocessor system having a plurality of processors each including a cache memory, the step of measuring a load state of the cache memory, and controlling the interrupt selector based on the measurement result, And a step of causing a lightest-loaded processor to execute an interrupt process.