JPH0946042A - Circuit forming method for printed wiring board - Google Patents
Circuit forming method for printed wiring boardInfo
- Publication number
- JPH0946042A JPH0946042A JP21811995A JP21811995A JPH0946042A JP H0946042 A JPH0946042 A JP H0946042A JP 21811995 A JP21811995 A JP 21811995A JP 21811995 A JP21811995 A JP 21811995A JP H0946042 A JPH0946042 A JP H0946042A
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- circuit
- wiring board
- printed wiring
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】
【課題】サブトラクティブ法による高密度回路形成上の
最大障害であるエッチングすべき膜厚の問題を解決し、
ヴィアホール等をもつ両面板或いは多層板に低コストで
高精度な回路を形成可能とする。
【解決手段】プリント配線板における回路形成方法で、
絶縁層3を間にして片面に第1導電層1を、他面に第2
導電層2をもつ積層基板Aに、片面の第2導電層2と絶
縁層3とを貫通するが他面の第1導電層1を貫通せぬ有
底のヴィアホール用孔部4を形成し、次に孔部4内面と
第2導電層2面上とにだけメッキを施した後、第2導電
層2と上面のメッキ膜5、および第1導電層1を各々エ
ッチングして、両面に各々回路6,7をもつプリント配
線板Bを形成する。或いは更に第2絶縁層と第3導電層
を積層し、上記と同様の有底の第2の孔部の形成と、第
3導電層側からだけのメッキを施した後にエッチングし
て、新たな回路を形成する。
(57) 【Abstract】 PROBLEM TO BE SOLVED: To solve the problem of film thickness to be etched, which is the biggest obstacle in forming a high density circuit by the subtractive method.
A low-cost and high-precision circuit can be formed on a double-sided plate having a via hole or the like or a multilayer plate. A circuit forming method for a printed wiring board,
The first conductive layer 1 is provided on one side and the second conductive layer is provided on the other side with the insulating layer 3 interposed therebetween.
In the laminated substrate A having the conductive layer 2, a via hole hole 4 having a bottom is formed which penetrates the second conductive layer 2 and the insulating layer 3 on one surface but does not penetrate the first conductive layer 1 on the other surface. Then, after plating only the inner surface of the hole 4 and the surface of the second conductive layer 2, the second conductive layer 2 and the plated film 5 on the upper surface, and the first conductive layer 1 are each etched to form both surfaces. A printed wiring board B having circuits 6 and 7 is formed. Alternatively, a second insulating layer and a third conductive layer are further laminated, a second bottomed hole portion similar to the above is formed, plating is performed only from the third conductive layer side, and then etching is performed to obtain a new layer. Form a circuit.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、プリント配線板に
おける回路の形成方法に関し、特に高密度のプリント回
路をサブトラクティブ法で形成する方法に係るものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a circuit on a printed wiring board, and more particularly to a method for forming a high density printed circuit by a subtractive method.
【0002】[0002]
【0003】プリント配線板における回路の形成方法に
は、大きく分けてサブトラクティブ法とアディティブ法
とがある。サブトラクティブ法は、予め絶縁層面に貼り
合わせた導電層としての銅箔をエッチング等によって回
路を形成する方法であり、アディティブ法は絶縁層に回
路を直接にメッキする方法である。サブトラクティブ法
は技術が比較的簡易で、コストが安いため最も汎用的に
用いられている。Circuit forming methods on a printed wiring board are roughly classified into a subtractive method and an additive method. The subtractive method is a method of forming a circuit by etching a copper foil as a conductive layer which is previously attached to the insulating layer surface, and the additive method is a method of directly plating the circuit on the insulating layer. The subtractive method is the most general-purpose because it has a relatively simple technology and is inexpensive.
【0004】上記サブトラクティブ法で、表・裏各面に
回路をもつプリント配線板を形成しようとする場合に
は、図7ないし図10で示す如く、絶縁層3の表・裏両
面に導電層(銅箔)1,2をもつ積層基板Aに、まずド
リルその他でスルホール用の孔部4を形成し、この孔部
4と表・裏面の導電層1,2上に同時にメッキ膜5,5
を形成した後、両面の導電層1,2をエッチングするこ
とにより、回路6,7を形成してプリント配線板Bとす
るのが従来一般的であった。When a printed wiring board having circuits on the front and back surfaces is formed by the subtractive method, as shown in FIGS. 7 to 10, conductive layers are formed on both the front and back surfaces of the insulating layer 3. First, a through hole 4 is formed by a drill or the like on a laminated substrate A having (copper foils) 1 and 2, and plated films 5 and 5 are simultaneously formed on the hole 4 and the conductive layers 1 and 2 on the front and back surfaces.
It has been customary in the past to form the printed wiring board B by forming the circuits 6 and 7 by etching the conductive layers 1 and 2 on both sides after forming the.
【0005】そして最近は、ドリルの代わりにレーザー
等を用いて片面からスルホールまたはヴィアホール(V
ia hole,バイアホールともいう)を形成した後
にメッキし、同じくエッチング等により回路を形成する
技術が普及しているが、このときも積層基板の表・裏両
面にメッキするのが通常であった。Recently, instead of a drill, a laser or the like is used, and a through hole or a via hole (V
Although a technique of forming a circuit after forming an ia hole (also referred to as a via hole) and then forming a circuit by the same method is widely used, it was usual to plate both the front and back surfaces of the laminated substrate at this time as well. .
【0006】また、プリント配線板で回路を形成する方
法において、レーザー技術が用いられているが、それは
上記の如く主としてスルホールやヴィアホール等の孔あ
け用としてである。レーザーとしては、炭酸ガスレーザ
ー、YAGレーザー、エキシマ・レーザー等があるが、
プリント配線板で回路板の加工に用いられるのはエキシ
マ・レーザーか、YAGレーザー、または炭酸ガスレー
ザーを改良したインパクト・レーザー等である。Further, a laser technique is used in a method of forming a circuit on a printed wiring board, which is mainly for drilling a through hole or a via hole as described above. Examples of lasers include carbon dioxide lasers, YAG lasers, excimer lasers, etc.
An excimer laser, a YAG laser, or an impact laser which is an improved carbon dioxide laser is used for processing a circuit board in a printed wiring board.
【0007】プリント配線板の回路形成にエキシマ・レ
ーザーを応用することに関しては、例えば特開平5−1
36650号公報、特開平5−152744号公報、特
開平5−152748号公報等に開示されている。同じ
くインパクト・レーザーを応用することについては、例
えばJ.M.Morrisonなど著の“A Larg
e Format Modified TEA CO2
Laser Based Process for
Cost Effective Via Genera
tion”(1994 Inernational C
onferecne on Multichip Mo
dules,1994年4月13〜15日,p.36
9)に記載されている。Regarding the application of the excimer laser to the circuit formation of a printed wiring board, for example, Japanese Laid-Open Patent Publication No. 5-1
It is disclosed in Japanese Patent No. 36650, Japanese Patent Application Laid-Open No. 5-152744, Japanese Patent Application Laid-Open No. 5-152748, and the like. Similarly, for applying the impact laser, see, for example, J. M. "A Larg" by Morrison and others
e Format Modified TEA CO 2
Laser Based Process for
Cost Effective Via Genera
“Tion” (1994 International C
onferecne on Multichip Mo
dules, April 13-15, 1994, p. 36
9).
【0008】更にYAGレーザーとそのプリント回路板
への応用については、例えばM.Owen著の“New
Laser Technology for Dri
lling Through− and Blind−
vias in Copper Clad Rein
forced Circuit Boards”(Pr
oc.IPC Technical Conferen
ce,1995年4月30日〜5月4日、p.19−1
−1〜19−1−10)に開示されている。Regarding the YAG laser and its application to a printed circuit board, see, for example, M.G. "New by Owen"
Laser Technology for Dri
Ling Through-and Blind-
vias in Copper Clad Rein
Forced Circuit Boards ”(Pr
oc. IPC Technical Conference
ce, April 30-May 4, 1995, p. 19-1
-1 to 19-1-10).
【0009】[0009]
【発明が解決しょうとする課題】ところで、プリント配
線板の高密度化への要求はさらに高まりつつあり、表面
のパターンをファイン化することがきわめて重要になっ
ている。例えば従来、ライン幅、スペース幅が各125
μmであった回路は、それぞれ100μm、更には50
μmへと増々ファイン化している。By the way, the demand for higher density of the printed wiring board is further increasing, and it is very important to make the surface pattern fine. For example, conventionally, the line width and the space width are each 125.
Circuits that were μm are 100 μm and 50
It is becoming finer to μm.
【0010】サブトラクティブ法において回路の高密度
化を達成するために、従来よりレジストやエッチング液
の改良が進められているが、高密度化達成を可能とする
上で最も大きな要因は導電層(銅箔)やメッキ膜の厚み
である。即ち、片面板の場合は単に導電層としての銅箔
を薄くすればよいが、両面板になると上記の如くスルー
ホールやヴィアホールへのメッキのために、導電層(銅
箔)上にメッキ膜が加算され、膜厚が必然的に大きくな
る。回路形成用のエッチッング時にエッチングすべき膜
厚が大きいと、回路パターンの精度が悪くなってしま
い、これが高密度化の大きな障害であり、問題点であっ
た。In order to achieve high density of the circuit in the subtractive method, improvement of the resist and the etching solution has been conventionally advanced, but the most important factor in achieving high density is the conductive layer ( Copper foil) and the thickness of the plating film. That is, in the case of a single-sided plate, the copper foil as the conductive layer may simply be thinned, but in the case of a double-sided plate, the plating film is formed on the conductive layer (copper foil) for plating through holes and via holes as described above. Is added, and the film thickness inevitably increases. If the film thickness to be etched at the time of etching for forming a circuit is large, the accuracy of the circuit pattern is deteriorated, which is a great obstacle to high density and is a problem.
【0011】本発明が解決しようとする課題は、スルー
ホールやヴィアホールをもつ両面板あるいは多層板に、
サブトラクティブ法にて回路の高密度化を図る上で最大
の障害であるエッチングすべき膜厚が大きいという問題
を解決することであり、本発明はこれにより低コストで
高精度な回路を形成することを目的としている。The problem to be solved by the present invention is to provide a double-sided plate or a multi-layered plate having through holes and via holes,
The present invention is to solve the problem that the film thickness to be etched is large, which is the biggest obstacle in increasing the density of the circuit by the subtractive method, and the present invention thereby forms a highly accurate circuit at low cost. Is intended.
【0012】[0012]
【課題を解決するための手段】本発明に係るプリント配
線板における回路形成方法の主要部は、絶縁層3を間に
して片面に第1導電層1を、他面に第2導電層2をもつ
積層基板A(図1参照)に、片面の第2導電層2と絶縁
層3とを貫通するが他面の第1導電層1を貫通せぬ有底
のヴィアホール用孔部4を形成し(図3参照)、次に孔
部4内面と第2導電層2面上とにだけメッキ5を施した
後(図4参照)、第2導電層2と上面のメッキ膜5、お
よび第1導電層1を各々エッチングすることにより、両
面に各々回路6,7を形成して(図5参照)、プリント
配線板Bを形成するものである。The main part of the method for forming a circuit in a printed wiring board according to the present invention is that a first conductive layer 1 is provided on one side and a second conductive layer 2 is provided on the other side with an insulating layer 3 in between. In the laminated substrate A (see FIG. 1) having a bottomed via hole hole 4 that penetrates the second conductive layer 2 and the insulating layer 3 on one surface but does not penetrate the first conductive layer 1 on the other surface. (See FIG. 3), and after plating 5 only on the inner surface of the hole 4 and on the surface of the second conductive layer 2 (see FIG. 4), the second conductive layer 2 and the plated film 5 on the upper surface, and By etching each of the conductive layers 1, circuits 6 and 7 are formed on both surfaces (see FIG. 5) to form the printed wiring board B.
【0013】上記の如く形成したプリント配線板Bは、
それ自体で成品でもあるが、更にそれに加えて、新たに
第2絶縁層8と第3導電層9を積層し、該第3導電層9
と第2の絶縁層8を貫通するが先の第2導電層2を貫通
せぬ有底の第2のヴィアホール用孔部10を形成し、次
に該孔部10内面と第3導電層9面上とにだけメッキを
施した後、第3導電層3と上面のメッキ膜11をエッチ
ングすることにより、新たな回路12を形成するように
してもよい(図6参照)。これは同様にして更に多層化
してもよいことは勿論である。The printed wiring board B formed as described above is
Although the product itself is a product, in addition to that, a second insulating layer 8 and a third conductive layer 9 are newly stacked to form the third conductive layer 9
And a bottomed second via hole hole 10 that penetrates the second insulating layer 8 but does not penetrate the second conductive layer 2, and then forms the inner surface of the hole 10 and the third conductive layer. Alternatively, a new circuit 12 may be formed by plating only the 9th surface and then etching the third conductive layer 3 and the plating film 11 on the upper surface (see FIG. 6). Needless to say, this may be further multilayered in the same manner.
【0014】上記構成において、絶縁層3は無機繊維ま
たは有機繊維製の補強材を含むものが望ましいが、含ま
なくともよい。第1・第2・第3の各導電層1,2,9
は、薄い銅箔が望ましいが、各面に銅または銅合金メッ
キを施したものでもよい。有底のヴィアホール用孔部
4,10の形成は、機械的、化学的、または光学的等の
各種の手段が用いられるが、精度上から特にレーザーを
用いることが望ましい。In the above structure, the insulating layer 3 preferably contains a reinforcing material made of an inorganic fiber or an organic fiber, but may not contain it. First, second and third conductive layers 1, 2, 9
Is preferably a thin copper foil, but each surface may be plated with copper or a copper alloy. Various methods such as mechanical, chemical, or optical are used to form the bottomed via hole portions 4 and 10, and it is particularly preferable to use a laser in terms of accuracy.
【0015】[0015]
【発明の実態の形態】上記本発明において、絶縁層3を
間にして片面に第1導電層1を、他面に第2導電層2を
もつ積層基板Aの第1導電層1および第2導電層2は、
金属特に銅箔とすることが望ましいが、銅合金のメッキ
膜であってもよい。According to the present invention, the first conductive layer 1 and the second conductive layer 1 of the laminated substrate A having the first conductive layer 1 on one surface and the second conductive layer 2 on the other surface with the insulating layer 3 interposed therebetween are provided. The conductive layer 2 is
A metal, particularly a copper foil is preferable, but a copper alloy plated film may be used.
【0016】上記絶縁層3に含まれる樹脂は、熱硬化性
樹脂、熱可塑性樹脂のいずれも用いることができる。熱
硬化性樹脂の中では、エポキシ樹脂、ポリイミド樹脂、
ビスマレイミドトリアジン樹脂、ポリシアヌレート樹
脂、ポリシラン樹脂、ポリベンツイミダゾール樹脂など
を用いることができる。As the resin contained in the insulating layer 3, either a thermosetting resin or a thermoplastic resin can be used. Among thermosetting resins, epoxy resin, polyimide resin,
Bismaleimide triazine resin, polycyanurate resin, polysilane resin, polybenzimidazole resin, etc. can be used.
【0017】該絶縁層3には有機繊維または無機繊維製
の補強材を含むことができるし、含まなくともよい。補
強材を含む場合の無機繊維としては例えばガラス繊維、
有機繊維としては例えばアラミド繊維、テフロン繊維、
ポリエーテルエーテルケトン繊維、ポリベンツイミダゾ
ール繊維等にすればよい。中でもアラミド繊維、テフロ
ン繊維は優れたレーザー加工性、電気特性を有しており
望ましい。とりわけアラミド繊維の中でもコポリパラフ
ェニレン3、4’オキシジフェニルテレフタラミド繊維
は低いイオン不純物と低い吸湿率のため最適である。The insulating layer 3 may or may not contain a reinforcing material made of an organic fiber or an inorganic fiber. As the inorganic fiber when including a reinforcing material, for example, glass fiber,
Examples of organic fibers include aramid fiber, Teflon fiber,
Polyether ether ketone fiber, polybenzimidazole fiber, or the like may be used. Of these, aramid fiber and Teflon fiber are desirable because they have excellent laser processability and electrical characteristics. Among the aramid fibers, copolyparaphenylene 3,4′oxydiphenyl terephthalamide fiber is particularly suitable because of low ionic impurities and low moisture absorption.
【0018】絶縁層3に補強材を含まぬ場合に、該絶縁
層3はフィルム、シート状のものであってもよく、その
材料としては例えばポリエステル、ポリイミド、ポリエ
ーテルエーテルケトン、ポリアミド、とりわけアラミ
ド、特にポリパラフェニレンテレフタラミドであること
が望ましい。また該絶縁層3の厚みは数μmないし数1
00μmが最適であるが、典型的な厚みは20〜100
μmである。When the insulating layer 3 does not contain a reinforcing material, the insulating layer 3 may be in the form of a film or sheet, and examples of the material include polyester, polyimide, polyetheretherketone, polyamide, and especially aramid. In particular, polyparaphenylene terephthalamide is preferable. The thickness of the insulating layer 3 is several μm to several 1
00 μm is optimal, but typical thickness is 20-100
μm.
【0019】上記第1導電層1と第2導電層2とそれら
の間にある絶縁層3をもつ積層基板Aに、第1導電層1
と絶縁層3とを貫通するが第2導電層2を貫通せぬ有底
のヴィアホール用孔部5を形成する。ここで該孔部5を
形成する方法としては、機械的、化学的、または光学的
など各種の手段が用いられる。特にレーザーを用いた開
口は、簡便で精度が高いため最適である。The first conductive layer 1 is formed on the laminated substrate A having the first conductive layer 1, the second conductive layer 2 and the insulating layer 3 between them.
And a bottomed via-hole 5 which penetrates the insulating layer 3 but does not penetrate the second conductive layer 2. Here, as a method of forming the holes 5, various means such as mechanical, chemical, or optical are used. In particular, an opening using a laser is optimal because it is simple and highly accurate.
【0020】レーザーとしては、炭酸ガスレーザー、Y
AGレーザー、エキシマ・レーザーのいずれも用いるこ
とができるが、孔部4,10の内面を滑らかにし、荒ら
さずに加工するため、炭酸ガスレーザーの一種であるイ
ンパクト・レーザー、YAGレーザー、エキシマレーザ
ーなどが望ましい。As the laser, carbon dioxide laser, Y
Either an AG laser or an excimer laser can be used, but since the inner surfaces of the holes 4 and 10 are smoothed and processed without roughening, an impact laser, which is a kind of carbon dioxide laser, a YAG laser, an excimer laser, etc. Is desirable.
【0021】このレーザー加工では、レーザー光はある
面積に絞って第2導電層2の上から照射すればよい。照
射部分を限定するには、マスク・イメージ法、コンタク
ト・マスク法、コンフォーマル・マスク法等のマスキン
グを使うことができる。In this laser processing, the laser beam may be focused on a certain area and irradiated from above the second conductive layer 2. Masking such as a mask image method, a contact mask method, and a conformal mask method can be used to limit the irradiated portion.
【0022】上記により有底のヴィアホール用孔部4が
形成された積層基板Aに対し、その片面である孔部4が
開口された第2導電層2の側から、孔部4内面と第2導
電層2にメッキが施される。他面である第1導電層1へ
はメッキを施さない。ここでのメッキ材料としては銅が
主成分のものが好ましい。なお、片面の第2導電層2側
面にだけメッキし、他面の第1導電層1面にメッキせぬ
ようにするには、他面の第1導電層1面にマスキングす
ればよいが、それに限らず両面に各導電層をもつ2枚の
積層基板Aを、第1導電層1面同士で背中合せに貼り合
わせ、表出した各第2導電層2面にメッキを施した後に
剥離するようにしてもよい。With respect to the laminated substrate A in which the bottomed via hole hole 4 is formed as described above, from one side of the second conductive layer 2 where the hole part 4 is opened, the inner surface of the hole part 4 and the second conductive layer 2 are formed. 2 The conductive layer 2 is plated. The first conductive layer 1, which is the other surface, is not plated. The plating material used here is preferably copper as a main component. In order to plate only the side surface of the second conductive layer 2 on one surface and not plate the surface of the first conductive layer 1 on the other surface, it is sufficient to mask the surface of the first conductive layer 1 on the other surface. Not limited to this, two laminated substrates A having conductive layers on both sides are stuck back to back on the first conductive layer 1 side, and the exposed second conductive layer 2 sides are plated and then peeled off. You may
【0023】またここでのメッキは、ヴィアホールとし
ての孔部4に導通をとるのが目的であるから、メッキ膜
5の厚みは通常のスルーホールメッキより薄くてよく、
その厚みは数μから数10μm程度とすればよい。典型
的な厚みは8ないし15μmである。またこのメッキは
無電解メッキでも電解メッキでも良く、あるいはこれら
を組み合わせたものでもよい。Further, since the purpose of the plating here is to conduct electricity to the hole portion 4 as a via hole, the thickness of the plating film 5 may be thinner than that of the usual through-hole plating.
The thickness may be several μm to several tens of μm. Typical thickness is 8 to 15 μm. The plating may be electroless plating, electrolytic plating, or a combination thereof.
【0024】上記メッキ処理の後に、片面の第2導電層
2とその上面のメッキ膜5、および他面の第1導電層1
を、通常のサブトラクティブ法でエッチングする。これ
により、積層基板Aの表・裏両面に各々回路6,7が形
成されて、両面回路のプリント配線板Bが完成すること
になる。After the above plating treatment, the second conductive layer 2 on one surface and the plating film 5 on the upper surface thereof, and the first conductive layer 1 on the other surface.
Are etched by the usual subtractive method. As a result, the circuits 6 and 7 are formed on both the front and back surfaces of the laminated substrate A, and the printed wiring board B having a double-sided circuit is completed.
【0025】本発明は、上記によりプリント配線板Bが
得られ、それ自体で成品であるが、上記プリント配線板
Bの上に、更に樹脂・プリプレグ等を塗工または積層し
て多層化したいわゆるビルドアップ基板にも適用するこ
とができる。その場合にも、有低の第2のヴィアホール
用孔部10の形成およびメッキ処理は、積層した第2絶
縁層8上の第3導電層9側だけで行われる。その後に第
3導電層9側がエッチングされて、該側に新たな回路1
2が形成されることになる(図6参照)。According to the present invention, the printed wiring board B is obtained by the above, and is a product itself. However, a so-called multi-layered structure is formed by further coating or laminating resin, prepreg or the like on the printed wiring board B. It can also be applied to build-up boards. Also in that case, the formation of the second via hole hole 10 having a height and the plating treatment are performed only on the third conductive layer 9 side on the laminated second insulating layer 8. After that, the third conductive layer 9 side is etched, and a new circuit 1 is formed on that side.
2 will be formed (see FIG. 6).
【0026】上記の如く、本発明に係るプリント配線板
における回路形成方法では、両側に導電層1,2をもつ
両面基板でも、その片側面にだけメッキを施し他側面に
はメッキを施さない。しかもそのメッキは、ヴィアホー
ルとしての孔部4,10に導通をとるのが目的であるか
ら、そのメッキ膜5,11の厚みも極めて薄いものでよ
い。As described above, in the method for forming a circuit in the printed wiring board according to the present invention, even a double-sided board having the conductive layers 1 and 2 on both sides is plated only on one side and not on the other side. Moreover, since the purpose of the plating is to establish conduction with the holes 4 and 10 as via holes, the thickness of the plated films 5 and 11 may be extremely thin.
【0027】そのため、本発明でのサブトラクティブ法
による回路形成方法は、回路形成用のエッチング時に、
エッチングすべき膜厚は片面の第2導電層2あるいは第
3導電層3の側では、その銅箔とその上の極めて薄いメ
ッキ膜5,11であり、他面の第1導電層1側ではその
銅箔をエッチングするだけでよい。したがって本発明で
は、サブトラクティブ法で高密度化達成の最大の障害で
あったエッチングすべき膜厚が薄くなっており、高精度
な回路パターンを描くことができる。Therefore, in the circuit forming method by the subtractive method of the present invention, during the etching for forming the circuit,
On the side of the second conductive layer 2 or the third conductive layer 3 on one side, the film thickness to be etched is the copper foil and the extremely thin plating films 5 and 11 on the side, and on the side of the first conductive layer 1 on the other side. All that is required is to etch the copper foil. Therefore, in the present invention, the film thickness to be etched, which is the biggest obstacle to attaining high density by the subtractive method, is thin, and a highly accurate circuit pattern can be drawn.
【0028】[0028]
【実施例1】まず、絶縁層3の樹脂成分がエポキシ樹脂
で、補強材としてアラミド繊維(コポリパラフェニレン
・3,4’オキシジフェニレンテレフタラミド)を加え
た積層基板A(厚み約0.1mm)の表裏両面に、第1
導電層1と第2導電層2として各々銅箔(厚み約18μ
m)を貼付したものを形成する(図1参照)。Example 1 First, a laminated substrate A (thickness: about 0. 0) in which the resin component of the insulating layer 3 is an epoxy resin and aramid fiber (copolyparaphenylene.3,4'oxydiphenylene terephthalamide) is added as a reinforcing material. 1mm) on both sides
Copper foil (thickness about 18 μm) is used as the conductive layer 1 and the second conductive layer 2.
m) is attached (see FIG. 1).
【0029】次に、その片面である第2導電層2の銅箔
をエッチングして、内径約0.1mmの開口を設けた後
に(図2参照)、その上からKrFエキシマレーザーを
照射することにより、絶縁層3を貫くが反対面の第1導
電層1は貫かない有底のヴィアホール用孔部4を形成す
る(図3参照)。Then, the copper foil of the second conductive layer 2 on one side is etched to form an opening having an inner diameter of about 0.1 mm (see FIG. 2), and then a KrF excimer laser is irradiated from above. As a result, a bottomed via-hole portion 4 that penetrates the insulating layer 3 but does not penetrate the first conductive layer 1 on the opposite surface is formed (see FIG. 3).
【0030】続いて、片面の孔部4を開口した第2導電
層2の側から、該孔部4内面にヴィアホールとして導通
をとるための通常の硫酸銅メッキを施す(図4参照)。
この銅メッキは無電解メッキで行った。これで孔部4内
面と第2導電層2面上とに、銅メッキ膜5(厚さ約20
μm)が形成された。この際、他面である第1導電層1
面には、ドライフィルムでマスキングしておき、メッキ
が付着しないようにしておく。Then, from the side of the second conductive layer 2 where the hole 4 on one surface is opened, the inner surface of the hole 4 is subjected to normal copper sulfate plating for conducting as a via hole (see FIG. 4).
This copper plating was performed by electroless plating. As a result, the copper plating film 5 (having a thickness of about 20
μm) was formed. At this time, the first conductive layer 1 which is the other surface
The surface is masked with a dry film to prevent the plating from adhering.
【0031】その後、上記片面の第2導電層2の銅箔上
の銅メッキ膜5と、他面の第1導電層1の銅箔とに各々
電着法によりレジストをコーティングし(厚さ約8μ
m)、塩化第2鉄により回路形成用のエッチングを行っ
て、最小ライン/スペース50μm/50μmの回路
6,7のパターンを形成した(図5参照)。このように
して、10枚の試験基板(大きさ250mm×250m
m)を得た。Thereafter, the copper plating film 5 on the copper foil of the second conductive layer 2 on one side and the copper foil of the first conductive layer 1 on the other side are each coated with a resist by an electrodeposition method (thickness: approx. 8μ
m), etching for forming a circuit was performed using ferric chloride to form patterns of circuits 6 and 7 having a minimum line / space of 50 μm / 50 μm (see FIG. 5). In this way, 10 test substrates (size 250 mm x 250 m
m) was obtained.
【0032】上記で得られた各試験基板のショート個所
を測定したところ、1枚当たり片面の第2導電層2側で
のショート個所は平均10.5個で、他面の第1導電層
1側でのショート個所は平均0.2個であった。When the short-circuited portions of each of the test substrates obtained above were measured, the average number of short-circuited portions on one side of the second conductive layer 2 was 10.5, and the short-circuited portions on the other side of the first conductive layer 1 were measured. The number of shorts on the side was 0.2 on average.
【0033】これにより、両面に導電層1,2をもつ両
面基板では、その片面(ここでは第2導電層2面)にだ
けメッキを施し、それを回路形成用エッチングして回路
形成する本発明が、ライン/スペース50μm/50μ
mのファインパターン形成に適していることが実証され
た。Thus, in the double-sided substrate having the conductive layers 1 and 2 on both sides, plating is applied only to one side (here, the second conductive layer 2 side), and the circuit is formed by etching it for circuit formation. But line / space 50μm / 50μ
It was proved that it is suitable for forming a fine pattern of m.
【0034】尚、上記は第1導電層1と第2導電層2を
もつ両面基板に回路形成したプリント基板Bについての
データーであるが、更に樹脂・プリプレグ等を塗工また
は積層して銅箔を貼付した第3導電層3をもつ多層のビ
ルドアップ基板のプリント配線板(図6参照)について
も、同様の試験を行ったところ、表面の第3導電層3側
に形成した回路でのショート個所は平均10.6個であ
った。The above is the data about the printed circuit board B in which the circuit is formed on the double-sided circuit board having the first conductive layer 1 and the second conductive layer 2. The copper foil is coated or laminated with resin or prepreg. The same test was performed on a printed wiring board (see FIG. 6) of a multi-layered build-up board having the third conductive layer 3 attached thereto, and a short circuit occurred in the circuit formed on the surface of the third conductive layer 3 side. The number of points was 10.6 on average.
【0035】[0035]
【比較例1】実施例1と同様の方法で、積層基板A(厚
み約0.1mm)の表裏各面に第1導電層と第2導電層
として各々銅箔(厚み約18μm)を貼付し、それに有
底の孔部を形成した後、今度はその表裏両面(第1導電
層面と第2導電層面)に、上記と同じ銅メッキ(厚さ約
20μm)を施し、その後同様の方法で両面に50μm
/50μmのライン/スペースでパターニングを行っ
た。Comparative Example 1 In the same manner as in Example 1, a copper foil (thickness: about 18 μm) was attached as a first conductive layer and a second conductive layer on each surface of the laminated substrate A (thickness: about 0.1 mm). After forming a bottomed hole in it, this time, the same copper plating (thickness about 20 μm) as above is applied to both front and back surfaces (first conductive layer surface and second conductive layer surface), and then both surfaces are processed by the same method. 50 μm
Patterning was performed with a line / space of / 50 μm.
【0036】これで得られた試験基板のショート個所を
測定すると、1枚当たり片面の第2導電層側でショート
個所が平均10.7個、他面の第1導電層側でショート
個所が平均11.5個所であった。その結果、従来のよ
うに積層基板の両面にメッキする場合には、ファインパ
ターンの形成は困難であることが実証された。When the short-circuited portions of the test board thus obtained were measured, the average number of short-circuited portions was 10.7 on the one side of the second conductive layer and the average of the short-circuited points on the other side of the first conductive layer. There were 11.5 places. As a result, it has been proved that it is difficult to form a fine pattern when plating is performed on both sides of a laminated substrate as in the conventional case.
【0037】[0037]
【発明の効果】以上で明かな如く、本発明に係るプリン
ト配線板の回路形成方法は、技術が比較的簡易でコスト
が安いサブトラクティブ法でありながら、高密度のプリ
ント回路を形成することができる。As is apparent from the above, the circuit forming method for a printed wiring board according to the present invention is capable of forming a high-density printed circuit even though the technique is a subtractive method which is relatively simple and inexpensive. it can.
【0038】即ち、従来のサブトラクティブ法では、両
面に銅箔等の導電層がある両面基板に回路形成する場合
に、ヴィアホール等への導通用メッキのために表・裏両
面で回路形成時にエッチングすべき膜厚は、各導電層で
ある銅箔とメッキ膜との和になっていた。そのため、エ
ッチングすべき膜厚が厚い以上、形成される回路パター
ンの精度は悪くなり、近時のファインパターン・高密度
回路の要請に応えられなかった。That is, in the conventional subtractive method, when a circuit is formed on a double-sided board having a conductive layer such as a copper foil on both sides, the circuit is formed on both the front and back sides for conductive plating in via holes. The film thickness to be etched was the sum of the copper foil as the conductive layer and the plated film. Therefore, if the film thickness to be etched is thicker, the accuracy of the circuit pattern to be formed becomes worse, and it has not been possible to meet the recent demand for a fine pattern / high density circuit.
【0039】これに対して本発明は、エッチングにより
回路形成するサブトラクティブ法でありながら、両側に
導電層をもつ両面基板においても、その片側の導通層面
にだけメッキを施し、他面にはメッキを施さないように
し、かつそのメッキ膜もヴィアホールとしての孔部に導
通をとるための極めて薄いものにしてある。そのため
に、回路形成用のエッチングでエッチングすべき膜厚
は、片面では導通層の銅箔と極く薄いメッキ膜、他面は
導通層の銅箔だけでよいことになる。On the other hand, the present invention is a subtractive method of forming a circuit by etching, but even in a double-sided board having conductive layers on both sides, plating is applied only to the conductive layer surface on one side and the other surface is plated. In addition, the plating film is made extremely thin for conducting to the hole portion as the via hole. Therefore, the film thickness to be etched by the circuit-forming etching only needs to be a conductive layer copper foil and a very thin plated film on one side, and a conductive layer copper foil on the other side.
【0040】したがって本発明によれば、サブトラクテ
ィブ法で高密度化達成の最大の障害であったエッチング
すべき膜厚を薄くすることができて、スルーホールやヴ
ィアホールをもつ両面板や多層板にも、低コストなサブ
トラクティブ法により、高密度な回路パターンを形成す
ることができ、パターンの高精度を図ることができるの
で、近時のファインパターン・高密度回路の要請に充分
に応えることができるようになる。Therefore, according to the present invention, it is possible to reduce the film thickness to be etched, which is the biggest obstacle for achieving the high density by the subtractive method, and it is possible to form a double-sided plate or a multi-layered plate having through holes or via holes. In addition, it is possible to form a high-density circuit pattern by the low-cost subtractive method, and it is possible to achieve high precision of the pattern, so it is possible to sufficiently meet the recent demands for fine patterns and high-density circuits. Will be able to.
【図1】本発明の実施例で用いた積層基板の一部拡大縦
断側面図である。FIG. 1 is a partially enlarged vertical side view of a laminated substrate used in an example of the present invention.
【図2】図1で示した積層基板の片面の導電層の一部に
開口した状態の一部拡大縦断側面図である。FIG. 2 is a partially enlarged vertical cross-sectional side view showing a state in which an opening is formed in a part of a conductive layer on one surface of the laminated substrate shown in FIG.
【図3】図2で示した積層基板にヴィアホール用の孔部
を形成した状態の一部拡大縦断側面図である。FIG. 3 is a partially enlarged vertical sectional side view showing a state in which a via hole is formed in the laminated substrate shown in FIG.
【図4】図3で示した積層基板の片面にだけメッキを施
した状態の一部拡大縦断側面図である。FIG. 4 is a partially enlarged vertical side view showing a state in which only one surface of the laminated substrate shown in FIG. 3 is plated.
【図5】図4で示した積層基板にエッチングで回路を形
成したプリント配線板を示す一部拡大縦断側面図であ
る。5 is a partially enlarged vertical side view showing a printed wiring board in which a circuit is formed on the laminated substrate shown in FIG. 4 by etching.
【図6】本発明をビルドアップ法による多層板に適用し
た場合のプリント配線板を示す一部拡大縦断側面図であ
る。FIG. 6 is a partially enlarged vertical sectional side view showing a printed wiring board when the present invention is applied to a multilayer board by a build-up method.
【図7】従来のサブトラクティブ法の実施例で用いた積
層基板の一部拡大縦断側面図である。FIG. 7 is a partially enlarged vertical side view of a laminated substrate used in an example of a conventional subtractive method.
【図8】図7で示した積層基板にスルーホール用の孔部
を形成した状態の一部拡大縦断側面図である。FIG. 8 is a partially enlarged vertical side view showing a state in which a through hole is formed in the laminated substrate shown in FIG.
【図9】図8で示した積層基板の両面にメッキを施した
状態の一部拡大縦断側面図である。9 is a partially enlarged vertical cross-sectional side view showing a state in which both surfaces of the laminated substrate shown in FIG. 8 are plated.
【図10】図9で示した積層基板にエッチングで回路を
形成したプリント配線板を示す一部拡大縦断側面図であ
る。10 is a partially enlarged vertical side view showing a printed wiring board in which a circuit is formed by etching on the laminated substrate shown in FIG.
A−積層基板 6−回路 B−プリント配線板 7−回路 1−第1導電層 8−第2絶縁層 2−第2導電層 9−第3導電層 3−絶縁層 10−孔部 4−孔部 11−回路 5−メッキ膜 A-Layered substrate 6-Circuit B-Printed wiring board 7-Circuit 1-First conductive layer 8-Second insulating layer 2-Second conductive layer 9-Third conductive layer 3-Insulating layer 10-Hole part 4-Hole Part 11-circuit 5-plating film
Claims (12)
をもつ積層基板に、片面の第2導電層と絶縁層とを貫通
するが他面の第1導電層を貫通せぬ有底のヴィアホール
用孔部を形成し、次に上記孔部内面と第2導電層面上と
にだけメッキを施した後、該第2導電層と上面のメッキ
膜、および第1導電層を各々エッチングして、両面に各
々回路を形成するようにしたことを特徴とする、プリン
ト配線板における回路形成方法。1. A laminated substrate having a first conductive layer and a second conductive layer with an insulating layer interposed between the second conductive layer on one side and the insulating layer, but the first conductive layer on the other side. After forming a bottomed via-hole hole, and then plating only the inner surface of the hole and the surface of the second conductive layer, the second conductive layer and the plated film on the upper surface, and the first conductive layer A method for forming a circuit in a printed wiring board, characterized in that each of them is etched to form a circuit on each side.
をもつ積層基板に、片面の第2導電層と絶縁層とを貫通
するが他面の第1導電層を貫通せぬ有底のヴィアホール
用孔部を形成し、次に上記孔部内面と第2導電層面上と
にだけメッキを施した後、上記第2導電層と上面のメッ
キ膜、および第1導電層を各々エッチングして、両面に
各々回路を形成し、かつ上記第2導電層側に更に第2絶
縁層と第3導電層を積層し、該第3導電層と第2絶縁層
を貫通するが先の第2導電層2を貫通せぬ有底の第2の
ヴィアホール用孔部を形成し、次に該第2の孔部内面と
第3導電層面上とにだけメッキを施した後、該第3導電
層と上面のメッキ膜をエッチングして、新たな回路を形
成するようにしたことを特徴とする、プリント配線板に
おける回路形成方法。2. A laminated substrate having a first conductive layer and a second conductive layer with an insulating layer interposed between the second conductive layer on one side and the insulating layer but the first conductive layer on the other side. A bottomed via-hole hole is formed, and then plating is performed only on the inner surface of the hole and the surface of the second conductive layer, and then the second conductive layer and the plated film on the upper surface, and the first conductive layer. Are respectively etched to form circuits on both sides, and a second insulating layer and a third conductive layer are further laminated on the second conductive layer side, and the third conductive layer and the second insulating layer are penetrated. After forming a bottomed second via hole hole that does not penetrate the previous second conductive layer 2 and then plating only the inner surface of the second hole and the surface of the third conductive layer, A method of forming a circuit in a printed wiring board, characterized in that the third conductive layer and the plating film on the upper surface are etched to form a new circuit. .
銅からなる、請求項1または2に記載のプリント配線板
における回路形成方法。3. The method for forming a circuit in a printed wiring board according to claim 1, wherein at least one of the conductive layer and the plated film is made of copper.
た、請求項1または2に記載のプリント配線板における
回路形成方法。4. The method for forming a circuit in a printed wiring board according to claim 1, wherein the holes are formed by laser processing.
求項4に記載のプリント配線板における回路形成方法。5. The method for forming a circuit in a printed wiring board according to claim 4, wherein the laser is an excimer laser.
求項4に記載のプリント配線板における回路形成方法。6. The method for forming a circuit in a printed wiring board according to claim 4, wherein the laser is an impact laser.
に記載のプリント配線板における回路形成方法。7. The laser is a YAG laser.
A method for forming a circuit in a printed wiring board according to.
記載のプリント配線板における回路形成方法。8. The method for forming a circuit in a printed wiring board according to claim 1, wherein the insulating layer contains a reinforcing material.
含む請求項8に記載のプリント配線板における回路形成
方法。9. The method for forming a circuit in a printed wiring board according to claim 8, wherein the insulating layer contains a reinforcing material made of an inorganic or organic fiber.
記載のプリント配線板における回路形成方法。10. The method for forming a circuit in a printed wiring board according to claim 9, wherein the insulating layer contains aramid fiber.
記載のプリント配線板における回路形成方法。11. The method for forming a circuit in a printed wiring board according to claim 9, wherein the insulating layer contains Teflon fiber.
は2に記載のプリント配線板における回路形成方法。12. The method for forming a circuit in a printed wiring board according to claim 1, wherein the insulating layer does not contain a reinforcing material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21811995A JPH0946042A (en) | 1995-08-02 | 1995-08-02 | Circuit forming method for printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21811995A JPH0946042A (en) | 1995-08-02 | 1995-08-02 | Circuit forming method for printed wiring board |
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Publication Number | Publication Date |
---|---|
JPH0946042A true JPH0946042A (en) | 1997-02-14 |
Family
ID=16714931
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP21811995A Pending JPH0946042A (en) | 1995-08-02 | 1995-08-02 | Circuit forming method for printed wiring board |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000003572A1 (en) * | 1998-07-08 | 2000-01-20 | Ibiden Co., Ltd. | Printed wiring board and method for producing the same |
WO2002015652A1 (en) * | 2000-08-10 | 2002-02-21 | Sony Chemicals Corp. | Flexible wiring board for front-back connection |
JP2006245122A (en) * | 2005-03-01 | 2006-09-14 | Dainippon Printing Co Ltd | Wiring member and method of manufacturing wiring member |
JP2007158856A (en) * | 2005-12-06 | 2007-06-21 | Fujitsu Ltd | Board and board module |
KR101534856B1 (en) * | 2008-12-29 | 2015-07-07 | 엘지이노텍 주식회사 | Printed circuit board and method for fabricating the same |
CN104902700A (en) * | 2014-03-05 | 2015-09-09 | 深南电路有限公司 | Internal-layer thick-copper circuit board processing method and internal-layer thick-copper circuit board |
-
1995
- 1995-08-02 JP JP21811995A patent/JPH0946042A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000003572A1 (en) * | 1998-07-08 | 2000-01-20 | Ibiden Co., Ltd. | Printed wiring board and method for producing the same |
US6715204B1 (en) | 1998-07-08 | 2004-04-06 | Ibiden Co., Ltd. | Printed wiring board and method for producing the same |
WO2002015652A1 (en) * | 2000-08-10 | 2002-02-21 | Sony Chemicals Corp. | Flexible wiring board for front-back connection |
US7285727B2 (en) | 2000-08-10 | 2007-10-23 | Sony Corporation | Flexible wiring boards for double-side connection |
JP2006245122A (en) * | 2005-03-01 | 2006-09-14 | Dainippon Printing Co Ltd | Wiring member and method of manufacturing wiring member |
JP2007158856A (en) * | 2005-12-06 | 2007-06-21 | Fujitsu Ltd | Board and board module |
KR101534856B1 (en) * | 2008-12-29 | 2015-07-07 | 엘지이노텍 주식회사 | Printed circuit board and method for fabricating the same |
CN104902700A (en) * | 2014-03-05 | 2015-09-09 | 深南电路有限公司 | Internal-layer thick-copper circuit board processing method and internal-layer thick-copper circuit board |
CN104902700B (en) * | 2014-03-05 | 2018-06-26 | 深南电路有限公司 | The processing method of inner-layer thick copper circuit board and inner-layer thick copper circuit board |
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