JPH0945813A - Surface mount electronic part and manufacture thereof - Google Patents
Surface mount electronic part and manufacture thereofInfo
- Publication number
- JPH0945813A JPH0945813A JP21416695A JP21416695A JPH0945813A JP H0945813 A JPH0945813 A JP H0945813A JP 21416695 A JP21416695 A JP 21416695A JP 21416695 A JP21416695 A JP 21416695A JP H0945813 A JPH0945813 A JP H0945813A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- plate
- intermediate insulating
- insulating
- surface mount
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明はセラミックパッケー
ジに半導体ペレットのような電子部品チップが封入され
た構造の表面実装型電子部品及びその製造方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type electronic component having a structure in which an electronic component chip such as a semiconductor pellet is enclosed in a ceramic package and a method for manufacturing the same.
【0002】[0002]
【従来の技術】この種のチップ型電子部品の従来構造
を、図13及び図14を参照して説明する。図13の電
子部品1は、リード2aの端部に半導体ペレット3を半
田付けし、該ペレット3の上面からボンディングワイヤ
4で他方のリード2bの一端と接続する。次いで、リー
ド2a,2bの一部と半導体ペレット3、ボンディング
ワイヤ4とを樹脂5で封止する。次に、リードフレーム
からリード2a,2bの不要部分を切り離し、最後に、
図に示すように樹脂5の隅角部を巻き込むようにリード
2a,2bを裏面側に折曲げて所定の電子部品1を完成
させる。2. Description of the Related Art A conventional structure of this type of chip-type electronic component will be described with reference to FIGS. In the electronic component 1 of FIG. 13, the semiconductor pellet 3 is soldered to the end of the lead 2a, and the upper surface of the pellet 3 is connected to one end of the other lead 2b by the bonding wire 4. Then, a part of the leads 2a and 2b, the semiconductor pellet 3, and the bonding wire 4 are sealed with a resin 5. Next, the unnecessary portions of the leads 2a and 2b are separated from the lead frame, and finally,
As shown in the figure, the leads 2a and 2b are bent to the back side so that the corners of the resin 5 are rolled up, and the predetermined electronic component 1 is completed.
【0003】図14のチップ型電子部品の構造は、例え
ば、特開昭61−22638号に示されているように、
セラミックパッケージ10内に半導体ペレット3を封入
した構造のものである。半導体ペレット3は前記パッケ
ージ10の底面の基板11に半田付けされ、半導体ペレ
ット3の上面からボンディングワイヤ4にてメタライズ
部12に接続される。このメタライズ部12は、セラミ
ックパッケージ10の側面を貫通して側方の外面に達
し、基板11の裏面側の一部までその隅角部を巻き込む
ように形成されている。また、セラミックパッケージ1
0の上面は、低融点ガラス13によりセラミック製の蓋
体14が固着されて閉塞されている。上記図13及び図
14に示した構造のものは、いずれも表面実装型電子部
品として使用されている。The structure of the chip type electronic component shown in FIG. 14 is, for example, as disclosed in Japanese Patent Laid-Open No. 61-22638.
The structure is such that the semiconductor pellet 3 is enclosed in a ceramic package 10. The semiconductor pellet 3 is soldered to the substrate 11 on the bottom surface of the package 10 and is connected to the metallized portion 12 by the bonding wire 4 from the upper surface of the semiconductor pellet 3. The metallized portion 12 is formed so as to penetrate the side surface of the ceramic package 10 to reach the outer surface on the side, and to wrap up its corner portion to a part of the back surface side of the substrate 11. Also, ceramic package 1
The upper surface of 0 is closed by a ceramic lid 14 fixed by a low melting point glass 13. Each of the structures shown in FIGS. 13 and 14 is used as a surface mount electronic component.
【0004】[0004]
【発明が解決しようとする課題】ところで、図13に示
した電子部品には次のような解決すべき課題がある。 樹脂封止型であるため、信頼性に若干の難がある。 板状のリード2a,2bの厚みが比較的薄いので機械
的強度が弱い。 電極の一方がワイヤボンディングであるため、大電流
向きではない。 ボンディングワイヤ4の断線が生じ易い。 また、図14に示す構造の電子部品には次のような解決
すべき課題がある。 セラミック製の基板11の両面及び側面にもメタライ
ズ部12が形成されてい るので、前記パッケージ10が高価になってしまう。 ワイヤボンディング工程が多い。 電子部品の高さ(厚さ方向の寸法)が大きくなってし
まう。By the way, the electronic component shown in FIG. 13 has the following problems to be solved. Since it is a resin-sealed type, there is some difficulty in reliability. Since the plate-shaped leads 2a and 2b are relatively thin, their mechanical strength is weak. Since one of the electrodes is wire-bonded, it is not suitable for large currents. Breakage of the bonding wire 4 is likely to occur. Further, the electronic component having the structure shown in FIG. 14 has the following problems to be solved. Since the metallized portions 12 are formed on both sides and side surfaces of the ceramic substrate 11, the package 10 becomes expensive. There are many wire bonding processes. The height (size in the thickness direction) of the electronic component becomes large.
【0005】[0005]
【発明の目的】本発明は、上記のような各課題を解決す
るためになされたもので、ワイヤボンディングを一切使
用せず、高信頼性を期待でき、セラミックパッケージへ
の構成を単純にして低コストを図り、大電流向けの表面
実装型電子部品及びその製造方法を提供することを目的
とするものである。SUMMARY OF THE INVENTION The present invention has been made in order to solve each of the problems described above, does not use wire bonding at all, and can be expected to have high reliability. It is an object of the present invention to provide a surface mount type electronic component for large current and a method for manufacturing the same at low cost.
【0006】[0006]
【課題を解決するための手段】本発明の表面実装型電子
部品は、主面の略中央部に貫通孔を設けた中間絶縁板
と、該絶縁板の貫通孔に収納される半導体ペレットのよ
うな電子部品チップと、前記中間絶縁板の両主面側にそ
れぞれ固着され、前記電子部品チップに接するか若しく
は半田付けされるように設けられた導電層を有する一対
の外側絶縁板とを備え、該導電層は外側絶縁板の端部ま
で延在され、該外側絶縁板の両端には、前記電子部品の
各電極と電気的に接続される金属電極が形成されている
ことを特徴とするものである。SUMMARY OF THE INVENTION A surface mount type electronic component of the present invention comprises an intermediate insulating plate having a through hole at a substantially central portion of a main surface, and a semiconductor pellet housed in the through hole of the insulating plate. An electronic component chip and a pair of outer insulating plates each having a conductive layer that is fixed to both main surface sides of the intermediate insulating plate and is in contact with or soldered to the electronic component chip, The conductive layer extends to an end portion of the outer insulating plate, and metal electrodes electrically connected to respective electrodes of the electronic component are formed at both ends of the outer insulating plate. Is.
【0007】また、表面実装型電子部品の製造方法は、
中間絶縁板の1単位が、複数個平面方向に一体的に形成
された中間絶縁集合板と、一方の主面は、導電層が略中
央部から一方の端部まで延在し、他方の主面は、両端に
導電層が複数個平面方向に一体的に形成された外側絶縁
集合板と、両主面に半田層によって金属電極が形成され
た電子部品チップとを用意し、前記外側絶縁集合板の一
方の主面に中間絶縁集合板を載置する工程と、次いで、
該中間絶縁集合板の各貫通孔内に電子部品チップを収納
する工程と、次いで、もう1枚の外側絶縁集合板の一方
の主面を前記中間絶縁集合板に対向させて積層し、それ
ら外側絶縁集合板と中間絶縁集合板との間を固着する工
程と、次いで、それらを各一単位毎の部品に切断分離す
る工程と、分離された各部品の両端を半田ディップして
金属電極を形成する工程と、を含むことを特徴とするも
のである。Further, a method of manufacturing a surface mount type electronic component is as follows.
One unit of the intermediate insulating plate has a plurality of intermediate insulating aggregate plates integrally formed in the plane direction, and one main surface has a conductive layer extending from a substantially central portion to one end portion and the other main surface. For the surface, an outer insulating assembly plate having a plurality of conductive layers integrally formed in the planar direction at both ends, and an electronic component chip having metal electrodes formed by solder layers on both main surfaces are prepared. Placing the intermediate insulating aggregate plate on one main surface of the plate, and then,
A step of accommodating electronic component chips in each through hole of the intermediate insulating aggregate plate, and then stacking the other outer insulating aggregate plate with one main surface thereof facing the intermediate insulating aggregate plate, A step of fixing between the insulating aggregate plate and the intermediate insulating aggregate plate, then a step of cutting and separating them into parts for each unit, and forming a metal electrode by solder dipping both ends of the separated parts And a step of performing.
【0008】[0008]
【発明の実施の形態】以下に、本発明の実施の形態を図
を参照して詳細に説明する。図1は本発明の表面実装型
電子部品の組立図であり、図2はその完成状態を示す斜
視図、図3はその断面図、図4はその平面図である。こ
れらの図において、表面実装型電子部品20は、略中央
部に貫通孔21が形成された中間絶縁板22を有し、こ
の中間絶縁板22の貫通孔21は、例えばダイオード構
造に形成された半導体ペレット23が収容される。上記
中間絶縁板22の平面図を第7図に、そのX−X線に沿
う断面図を図8に示す。なお、貫通孔21の形状及び大
きさは収容される半導体ペレット23の形状及び大きさ
によって決定される。要は、貫通孔21に収容される半
導体ペレット23の位置決めができれば、その形状及び
大きさは問わない。Embodiments of the present invention will be described below in detail with reference to the drawings. 1 is an assembly view of a surface mount electronic component of the present invention, FIG. 2 is a perspective view showing its completed state, FIG. 3 is its sectional view, and FIG. 4 is its plan view. In these drawings, the surface-mounted electronic component 20 has an intermediate insulating plate 22 having a through hole 21 formed in a substantially central portion thereof, and the through hole 21 of the intermediate insulating plate 22 is formed in, for example, a diode structure. The semiconductor pellet 23 is accommodated. FIG. 7 shows a plan view of the intermediate insulating plate 22 and FIG. 8 shows a sectional view taken along line XX thereof. The shape and size of the through holes 21 are determined by the shape and size of the semiconductor pellets 23 accommodated therein. In short, the shape and size of the semiconductor pellets 23 accommodated in the through holes 21 are not limited as long as the semiconductor pellets 23 can be positioned.
【0009】上記の中間絶縁板22の両側には外側絶縁
板24,25が接着される。これらの外側絶縁板24,
25は同一部品であり、表裏左右を反対にして図示のよ
うに対向させて使用する。図5、図6に一方の外側絶縁
板24、図9、図10に他方の外側絶縁板25の平面図
及び側面図をそれぞれ示す。これらの図から明らかのよ
うに、外側絶縁板24、25の長手方向両端部に一定の
幅の導電層26aが形成されている。すなわち、図5に
現われている表面側をA面とし、裏面側をB面とする
と、A面側には幅方向に一方の端部から他方の端部に向
かって斜線部の幅広の導電層26bがメタライズ処理に
より形成されている。他方、B面側には上記のように幅
方向両端に導電層26aが形成されている。もう1つの
外側絶縁板25は上記の外側絶縁板24と表、裏面逆に
なり、かつ、幅広の導電層26bは、図9に示すように
幅方向に対称に形成されているが、これは同一部品であ
り、表、裏と方向を変えて使用するようにしたものであ
る。Outside insulating plates 24 and 25 are bonded to both sides of the intermediate insulating plate 22. These outer insulation plates 24,
Reference numeral 25 is the same part, and the front and back sides are opposite to each other and used as shown in the figure. 5 and 6 show a plan view and a side view of one outer insulating plate 24, and FIGS. 9 and 10 show a plan view and a side view of the other outer insulating plate 25, respectively. As is apparent from these figures, conductive layers 26a having a constant width are formed on both ends of the outer insulating plates 24 and 25 in the longitudinal direction. That is, assuming that the front surface side shown in FIG. 5 is the A surface and the back surface side is the B surface, the A conductive layer has a wide conductive layer with a diagonal line portion from one end to the other in the width direction. 26b is formed by a metallizing process. On the other hand, the conductive layers 26a are formed on the B surface side at both ends in the width direction as described above. The other outer insulating plate 25 is opposite to the above outer insulating plate 24 in the front and back surfaces, and the wide conductive layer 26b is formed symmetrically in the width direction as shown in FIG. It is the same part, and it is used by changing the direction of the front and back.
【0010】以上の中間絶縁板22、外側絶縁板24,
25が重ね合わせられ、中間絶縁板22の貫通孔21内
には、半導体ペレット23のような電子部品チップが収
容され、各絶縁板22,24,25の間は接着剤、例え
ばポリイミド系接着剤、あるいは低融点ガラスにより接
着される。そして、上記積層体の幅方向両端は、半田デ
ップされ図3の完成品のように、アノード電極27、カ
ソード電極28が形成される。このようにして完成され
た表面実装型電子部品20が図2に斜視図で示してあ
る。The above intermediate insulating plate 22, outer insulating plate 24,
25 are stacked, an electronic component chip such as a semiconductor pellet 23 is housed in the through hole 21 of the intermediate insulating plate 22, and an adhesive agent, for example, a polyimide adhesive agent, is provided between the insulating plates 22, 24, 25. Or, it is adhered by low melting point glass. Then, both ends in the width direction of the laminated body are solder-dipped, and an anode electrode 27 and a cathode electrode 28 are formed as in the completed product of FIG. The surface mount electronic component 20 thus completed is shown in a perspective view in FIG.
【0011】[0011]
【実施例】上記のような表面実装型電子部品20は、一
括して多数量産され、最終工程で個々に切断されて一単
位として完成されるものであるが、次に、その実施例に
ついて説明する。図11は長さL1=14.5mm,幅
L2=13.5mm、板厚0.3mmのセラミック製の
絶縁集合板29の中に、上述した一単位の外側絶縁板2
4(25)が平面方向に複数個一体的に形成されたもの
である。図示のものは、一単位の外側絶縁板24(2
5)は、2.9mm×1.5mmで、これが合計45個
形成された外側絶縁集合板29である。この集合板29
の一方の面(A面)には、幅L3=0.5mmの導電層
26aがメタライズ処理により図示のように形成されて
いる。また、他方の面(B面)には、幅L4=1.0m
m、長さL5=2.05mmの導電層26bがそれぞれ
形成されている。EXAMPLE A large number of the surface mount electronic components 20 as described above are mass-produced in a lump, and are individually cut in the final step to be completed as one unit. Next, an example will be described. To do. FIG. 11 shows a ceramic insulating assembly plate 29 having a length L1 = 14.5 mm, a width L2 = 13.5 mm, and a plate thickness of 0.3 mm.
4 (25) are integrally formed in the plane direction. In the figure, one unit of the outer insulating plate 24 (2
5) is an outer insulating aggregate plate 29 having a total of 45 pieces of 2.9 mm × 1.5 mm. This assembly board 29
On one surface (A surface), a conductive layer 26a having a width L3 = 0.5 mm is formed by a metallizing process as illustrated. On the other surface (B surface), the width L4 = 1.0 m
Conductive layers 26b each having a length m and a length L5 = 2.05 mm are formed.
【0012】図12は、一単位が幅L6=1.5mm、
長さL7=2.9mm、厚さ0.4mmであって、その
略中央部に1mm角の貫通孔21を形成した中間絶縁集
合板30を示している。この一単位が外側絶縁板24
(25)と対応するように、平面的に合計45個形成さ
れいる。なお、この中間絶縁集合板30には、導電層は
形成されていない。In FIG. 12, one unit is width L6 = 1.5 mm,
The length L7 is 2.9 mm, the thickness is 0.4 mm, and the intermediate insulating aggregate plate 30 has a 1 mm square through-hole 21 formed in the approximate center thereof. This one unit is the outer insulating plate 24
A total of 45 pieces are formed in a plane so as to correspond to (25). No conductive layer is formed on the intermediate insulating aggregate plate 30.
【0013】次に、上記のように各構成の集合板を使用
した表面実装型電子部品の製造方法について説明する。
まず、外側絶縁集合板29の導電層26bが形成されて
いる側を上方にして、その上に、予めポリイミド系樹脂
又は低融点ガラスからなる接着剤を塗布した中間絶縁集
合板30を重ねる。次に、中間絶縁集合板30の各貫通
孔21に予め両主面に半田層によって金属電極が形成さ
れた半導体ペレット23を収容する。次いで、この中間
絶縁集合板30の上面に、導電層26bが形成されてい
る側が半導体ペレット23と当接するように外側絶縁集
合板29を重ね合わせる。この時、導電層26bの方向
が互いに逆方向になるように、2枚の外側絶縁集合板2
9を中間絶縁集合板30を挟んで重ね合わせる。上記の
状態で不活性ガス雰囲気中の加熱炉等に入れ、中間絶縁
集合板30に塗布した接着剤を溶融させた後、冷却して
それらを一体的に固化させる。この時に、半導体ペレッ
ト23の両主面に予め形成した半田層を溶融させて導電
層26bと固着させても良い。Next, a method of manufacturing a surface mount type electronic component using the above-described assembly plate will be described.
First, the side of the outer insulating aggregate plate 29 on which the conductive layer 26b is formed faces upward, and the intermediate insulating aggregate plate 30 to which the adhesive agent made of polyimide resin or low-melting glass is applied in advance is stacked on the side. Next, the semiconductor pellets 23 having the metal electrodes formed on the both main surfaces by the solder layers in advance are housed in the through holes 21 of the intermediate insulating aggregate plate 30. Next, the outer insulating aggregate plate 29 is superposed on the upper surface of the intermediate insulating aggregate plate 30 so that the side on which the conductive layer 26b is formed contacts the semiconductor pellet 23. At this time, the two outer insulating assembly plates 2 are arranged so that the conductive layers 26b are in opposite directions.
9 are superposed with the intermediate insulating aggregate plate 30 sandwiched therebetween. In the above-mentioned state, the adhesive applied to the intermediate insulating aggregate plate 30 is melted by putting it in a heating furnace in an inert gas atmosphere and then cooled to solidify them integrally. At this time, the solder layers previously formed on both main surfaces of the semiconductor pellet 23 may be melted and fixed to the conductive layer 26b.
【0014】次に、半導体ペレット23が収容された3
枚から成る積層体を一単位毎に切断する。この切断方法
は公知の方法で良く、例えばダイヤモンドブレードによ
る切断、若しくはワイヤソーによる切断等で個々に分割
する。次に、個々に分割された積層体における外側絶縁
板24,25の両端部の導電層26a,26bを半田デ
ィップし、図2に示すように、一方をアノード電極2
7、他方をカソード電極28となす。Next, the semiconductor pellet 23 containing 3
The laminated body made of sheets is cut into units. This cutting method may be a known method, for example, cutting with a diamond blade, cutting with a wire saw, or the like is performed to divide into individual pieces. Next, the conductive layers 26a and 26b at both ends of the outer insulating plates 24 and 25 in the individually divided laminated body are solder-dipped, and as shown in FIG.
7 and the other is the cathode electrode 28.
【0015】[0015]
【発明の効果】以上のように、本発明の表面実装型電子
部品及びその製造方法は上記のように構成したので、概
略以下のような効果を奏する。 セラミックパッケージを構成するため、環境条件に強
く高信頼性を期待できる。 リード線を有していないので、該リードの曲がり、折
れ等がない。 ボンディングワイヤを使用しないので、比較的大電流
用途にも適用できる。 上記により、断線のおそれがない。 作業工数が少なく低コストで製作できる。 電子部品全体の高さ(厚さ)を小さくできるので、こ
の部品を使用する際の実装密度を大きくできる。 チップコンデンサ、チップ抵抗等のライン装置が利用
できる。 パッケージングに紙テープが利用でき、このため包装
コストを低く抑えることができる。As described above, since the surface mount type electronic component and the method of manufacturing the same according to the present invention are configured as described above, the following advantageous effects can be obtained. Since it constitutes a ceramic package, it can be expected to have high reliability and strong environmental conditions. Since it has no lead wire, there is no bending or bending of the lead. Since no bonding wire is used, it can be applied to relatively large current applications. Due to the above, there is no risk of disconnection. It can be manufactured at low cost with less work man-hours. Since the height (thickness) of the entire electronic component can be reduced, the mounting density when using this component can be increased. Line devices such as chip capacitors and chip resistors can be used. Paper tape can be used for packaging, which keeps packaging costs low.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明の表面実装型電子部品の組立部品の斜視
図である。FIG. 1 is a perspective view of an assembly component of a surface mount type electronic component of the present invention.
【図2】本発明の表面実装型電子部品の完成品を示す斜
視図である。FIG. 2 is a perspective view showing a finished surface mount electronic component of the present invention.
【図3】上記表面実装型電子部品の中央縦断面図であ
る。FIG. 3 is a central vertical cross-sectional view of the surface mount electronic component.
【図4】上記表面実装型電子部品の平面図である。FIG. 4 is a plan view of the surface mount electronic component.
【図5】一単位の上記表面実装型電子部品における一方
の外側絶縁板の平面図である。FIG. 5 is a plan view of one outer insulating plate in one unit of the surface mount electronic component.
【図6】図5の外側絶縁板の側面図である。FIG. 6 is a side view of the outer insulating plate of FIG.
【図7】一単位の上記表面実装型電子部品における中間
絶縁板の平面図である。FIG. 7 is a plan view of an intermediate insulating plate in one unit of the surface mount electronic component.
【図8】図7におけるX−X線に沿う断面図である。FIG. 8 is a sectional view taken along line XX in FIG.
【図9】一単位の上記表面実装型電子部品における他方
の外側絶縁板の平面図である。FIG. 9 is a plan view of the other outer insulating plate in one unit of the surface mount electronic component.
【図10】図9の外側絶縁板の側面図である。FIG. 10 is a side view of the outer insulating plate of FIG.
【図11】本発明の表面実装型電子部品を製作する場合
に使用される外側絶縁集合板の平面図である。FIG. 11 is a plan view of an outer insulating collective plate used when manufacturing the surface mount electronic component of the present invention.
【図12】本発明の表面実装型電子部品を製作する場合
に使用される中間絶縁集合板の平面図である。FIG. 12 is a plan view of an intermediate insulating aggregate plate used when manufacturing the surface mount electronic component of the present invention.
【図13】従来のこの種の表面実装型電子部品の構造を
示す断面図である。FIG. 13 is a cross-sectional view showing the structure of a conventional surface mount electronic component of this type.
【図14】同じく従来のもう1つの構造を示す断面図で
ある。FIG. 14 is a sectional view showing another conventional structure.
20 表面実装型電子部品 21 貫通孔 22 中間絶縁板 23 半導体ペレット 24,25 外側絶縁板 26a,26b 導電層 27 アノード電極 28 カソード電極 29 外側絶縁集合板 30 中間絶縁集合板 20 Surface Mounted Electronic Components 21 Through Hole 22 Intermediate Insulating Plate 23 Semiconductor Pellets 24, 25 Outer Insulating Plates 26a, 26b Conductive Layer 27 Anode Electrode 28 Cathode Electrode 29 Outer Insulating Assembly Plate 30 Intermediate Insulating Assembly Plate
Claims (6)
縁板と、該絶縁板の貫通孔に収納される半導体ペレット
のような電子部品チップと、前記中間絶縁板の両主面側
にそれぞれ固着され、前記電子部品チップに接するか若
しくは半田付けされるように設けられた導電層を有する
一対の外側絶縁板とを備え、該導電層は外側絶縁板の端
部まで延在され、該外側絶縁板の両端には、前記電子部
品の各電極と電気的に接続される金属電極が形成されて
いることを特徴とする表面実装型電子部品。1. An intermediate insulating plate having a through hole in a substantially central portion of a main surface, an electronic component chip such as a semiconductor pellet housed in the through hole of the insulating plate, and both main surfaces of the intermediate insulating plate. A pair of outer insulating plates having conductive layers provided so as to be in contact with the electronic component chips or to be soldered to the electronic component chips, the conductive layers extending to the end portions of the outer insulating plates. A surface mount electronic component, wherein metal electrodes electrically connected to respective electrodes of the electronic component are formed at both ends of the outer insulating plate.
導電層が略中央部から一方の端まで延在し、他方の主面
は両端に細幅の導電層が形成されていることを特徴とす
る請求項1に記載の表面実装型電子部品。2. The outer electrode plate has one main surface having a wide conductive layer extending from a substantially central portion to one end, and the other main surface having a narrow conductive layer formed at both ends thereof. The surface mount electronic component according to claim 1, wherein
縁板の外側面の両端に設けられている導電層と、前記貫
通孔内に収容された電子部品チップに接する導電層とが
半田デップによって電気的に接続されていることを特徴
とする請求項1又は請求項2に記載の表面実装型電子部
品。3. A solder layer is provided between a conductive layer provided at both ends of an outer surface of an outer insulating plate facing each other through the intermediate insulating plate and a conductive layer in contact with an electronic component chip housed in the through hole. 3. The surface-mounted electronic component according to claim 1, wherein the surface-mounted electronic component is electrically connected by.
ことを特徴とする請求項1乃至請求項3のいずれかに記
載された表面実装型電子部品。4. The surface mount electronic component according to claim 1, wherein each of the insulating plates is made of a ceramic material.
に一体的に形成された中間絶縁集合板と、一方の主面
は、導電層が略中央部から一方の端部まで延在し、他方
の主面は、両端に導電層が複数個平面方向に一体的に形
成された外側絶縁集合板と、両主面に半田層によって金
属電極が形成された電子部品チップとを用意し、 前記外側絶縁集合板の一方の主面に中間絶縁集合板を載
置する工程と、次いで、該中間絶縁集合板の各貫通孔内
に電子部品チップを収納する工程と、次いで、もう1枚
の外側絶縁集合板の一方の主面を前記中間絶縁集合板に
対向させて積層し、それら外側絶縁集合板と中間絶縁集
合板との間を固着する工程と、次いで、それらを各一単
位毎の部品に切断分離する工程と、分離された各部品の
両端を半田ディップして金属電極を形成する工程と、を
含むことを特徴とする表面実装型電子部品の製造方法。5. A unit of the intermediate insulating plate, a plurality of intermediate insulating collective plates integrally formed in the plane direction, and one main surface, the conductive layer extends from substantially the central portion to one end portion. On the other main surface, an outer insulating aggregate plate having a plurality of conductive layers integrally formed on both ends in the planar direction, and an electronic component chip having metal electrodes formed by solder layers on both main surfaces are prepared. A step of placing the intermediate insulating aggregate plate on one main surface of the outer insulating aggregate plate, a step of accommodating electronic component chips in each through hole of the intermediate insulating aggregate plate, and then another sheet A step of laminating one of the main surfaces of the outer insulating aggregate plate so as to face the intermediate insulating aggregate plate, and fixing the outer insulating aggregate plate and the intermediate insulating aggregate plate together; The process of cutting and separating into separate parts, and dipping both ends of each separated part with a solder Surface mount electronic component manufacturing method characterized by comprising the steps of forming an electrode, the.
の固着を耐熱性接着剤でなしたことを特徴とする請求項
5に記載の表面実装型電子部品の製造方法。6. The method of manufacturing a surface mount electronic component according to claim 5, wherein the outer insulating aggregate plate and the intermediate insulating aggregate plate are fixed to each other with a heat resistant adhesive.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21416695A JP3447025B2 (en) | 1995-07-31 | 1995-07-31 | Surface mounted electronic component and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21416695A JP3447025B2 (en) | 1995-07-31 | 1995-07-31 | Surface mounted electronic component and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0945813A true JPH0945813A (en) | 1997-02-14 |
JP3447025B2 JP3447025B2 (en) | 2003-09-16 |
Family
ID=16651334
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21416695A Expired - Fee Related JP3447025B2 (en) | 1995-07-31 | 1995-07-31 | Surface mounted electronic component and method of manufacturing the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3447025B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002532876A (en) * | 1998-12-07 | 2002-10-02 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for enclosing electronic components in a casing |
JP2016152416A (en) * | 2015-02-17 | 2016-08-22 | 立昌先進科技股▲分▼有限公司 | Multi-function miniaturized surface-mount device and method for producing the same |
-
1995
- 1995-07-31 JP JP21416695A patent/JP3447025B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002532876A (en) * | 1998-12-07 | 2002-10-02 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for enclosing electronic components in a casing |
JP2016152416A (en) * | 2015-02-17 | 2016-08-22 | 立昌先進科技股▲分▼有限公司 | Multi-function miniaturized surface-mount device and method for producing the same |
Also Published As
Publication number | Publication date |
---|---|
JP3447025B2 (en) | 2003-09-16 |
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