JPH0936347A - Doubled-sided semiconductor device - Google Patents
Doubled-sided semiconductor deviceInfo
- Publication number
- JPH0936347A JPH0936347A JP17832595A JP17832595A JPH0936347A JP H0936347 A JPH0936347 A JP H0936347A JP 17832595 A JP17832595 A JP 17832595A JP 17832595 A JP17832595 A JP 17832595A JP H0936347 A JPH0936347 A JP H0936347A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- region
- short
- dedicated
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Thyristors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体基板の両主面間
に流れる電流の双方向対称特性を有する両面型半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double-sided semiconductor device having a bidirectional symmetrical characteristic of a current flowing between both main surfaces of a semiconductor substrate.
【0002】[0002]
【従来の技術】双方向対称特性を有する自己点弧の両面
型半導体装置は断面構造が対称となっている。図2は従
来の双方向二端子サイリスタの構造を示し、n- 層1を
はさむ p+ 層21、22の表面層にn+ 層3
1、32が線対称に形成されている。図示 され
ていないが、両主面にはn+ 層31の斜線で示した面と
p+ 層21の露出面 とに共通に接触する電極
と、n+ 層32の点線の斜線で示した面とp+ 層22の
露出面とに共通に接触する電極が設けられてい
る。2. Description of the Related Art A self-ignition double-sided semiconductor device having bidirectional symmetry has a symmetrical sectional structure. FIG. 2 shows a structure of a conventional bidirectional two-terminal thyristor, in which the n + layer 3 is provided on the surface layers of the p + layers 21 and 22 sandwiching the n − layer 1.
1 and 32 are formed in line symmetry. Although not shown in the figure, on both main surfaces, the electrodes commonly contacting the shaded surface of the n + layer 31 and the exposed surface of the p + layer 21, and the shaded surface of the n + layer 32 are shown. An electrode is provided in common contact with the exposed surface of the p + layer 22.
【0003】この半導体装置は、pエミッタ層21、n
ベース層1、pベース層22およびnエミッタ層32の
pnpn構造のサイリスタと、pエミッタ層22、nベ
ース 層1、pベース層21およびnエミッタ層
31のpnpn構造のサイリスタを逆 並列に備
えており、ブレークオーバ電圧以上の電圧を印加する
か、臨界オフ電圧 上昇率以上に急峻な立ち上が
りを有する電圧を印加することにより、双方向でオ
フ状態からオン状態へ移行させることができる。This semiconductor device has a p-emitter layer 21, n
The pnpn structure thyristor of the base layer 1, the p base layer 22 and the n emitter layer 32 and the pnpn structure thyristor of the p emitter layer 22, the n base layer 1, the p base layer 21 and the n emitter layer 31 are provided in antiparallel. Therefore, by applying a voltage that is equal to or higher than the breakover voltage or a voltage that has a steep rise above the critical off-voltage rise rate, bidirectional
It is possible to shift from the OFF state to the ON state.
【0004】[0004]
【発明が解決しようとする課題】図2のような半導体装
置の保持電流とサージ電流耐量とはトレードオフの関係
にある。すなわち、例えば、nエミッタ層との界面に接
するpベース層の不純物 濃度Cnpを高くする
と、保持電流IH は高くなるがサージ耐量が著しく低下
す る。サージ電流耐量は、サージ電流が集中す
ると低下する。自己復帰型の二端子 サイリスタ
では、保持電流とサージ耐量の双方の高いことが望まれ
る。The holding current and the surge current withstanding capability of the semiconductor device as shown in FIG. 2 have a trade-off relationship. That is, for example, if the impurity concentration Cnp of the p base layer in contact with the interface with the n emitter layer is increased, the holding current I H is increased but the surge resistance is significantly reduced. The surge current withstand level decreases when the surge current is concentrated. A self-reset type two-terminal thyristor is required to have both high holding current and surge withstand capability.
【0005】本願と同一の出願人の出願に係る特願平6
−155091号明細書には、サージ電流の集中を緩和
し、同じ保持電流でサージ耐量を大きくした両面型半導
体装 置として、図3に示すようにnエミッタ層
31および32をそれぞれくしの歯部 41、4
2を有するくし形に形成し、両面のくしの歯部41、4
2はn- 層1の 中心点に対して点対称であり、
かつ図4に示すように一方のくしの歯部41、4
2が他方のくしの歯部41、42の間隙に上下に重な
るように配置したものが記 載されている。[0005] Japanese Patent Application No. Hei.
No. 155,091 discloses a double-sided semiconductor device in which the concentration of surge current is relaxed and the surge withstand current is increased at the same holding current, as shown in FIG. 41, 4
Comb shape with 2 and comb teeth 41, 4 on both sides
2 is point symmetric with respect to the center point of the n − layer 1,
And as shown in FIG. 4, one of the comb teeth 41, 4
2 is arranged so as to vertically overlap with the gap between the teeth 41 and 42 of the other comb.
【0006】本発明の目的は、このようなくしの歯状の
エミッタ専用領域を有し、さらにサージ耐量と保持電流
との間のトレードオフの関係を改善した両面型半導体装
置を 提供することにある。It is an object of the present invention to provide a double-sided semiconductor device having such a tooth-shaped emitter-dedicated region and having an improved trade-off relationship between surge withstand current and holding current. .
【0007】[0007]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、半導体基板の両主面側に第一導電形の
ベース・エミッタ兼用領域およびその領域の表面層に形
成された第二導電形の エミッタ専用領域が露出
し、両面側のベース・エミッタ兼用領域およびエミッタ
専用領域の形状が基板の中心点に対し点対称で
あり、エミッタ専用領域の形状が くし形であ
り、一面側のエミッタ専用領域の歯の部分が他面側のエ
ミッタ専用領 域の歯の間隙部分に基板主面に垂
直方向で対向する両面型半導体装置において、
エミッタ専用領域の外周部に、ベース・エミッタ兼用領
域に達し、第一導電形層 によって充てんされた
短絡孔が設けられたものとする。一面側のエミッタ専用
領 域の歯の周縁部と他面側のエミッタ専用領域
の歯の周縁部が歯の部分の幅の10%以下の幅だけ基板
主面に垂直方向で重なり合うことも有効である。短絡孔
がくし形の歯の中心線の延長部に設けられたことが良
い。短絡孔が、エミッタ専用領 域の外周部のう
ちの半導体基板の外周に近い側の部分にのみ設けられた
ことも良 い。エミッタ専用領域の外周部のうち
の半導体基板の外周部に近い側の部分に近 接す
る部分のみ、ベース・エミッタ兼用領域の不純物濃度が
高くされ、短絡孔が その不純物濃度の高い領域
の内側でベース・エミッタ専用領域に達することも良
い。また、エミッタ専用領域の深さがその領域の
内周部において短絡孔の設けら れる外周部より
深くされたことが有効で、エミッタ専用領域の深さが外
周部より 内周部に向かうに従って深くされたこ
とも良い。In order to achieve the above object, the present invention is formed on both main surface sides of a semiconductor substrate in a base / emitter combined area of the first conductivity type and a surface layer of the area. The second-conductivity-type emitter-dedicated region is exposed, and the shapes of the base / emitter dual-use region and the emitter-dedicated region on both sides are point-symmetric with respect to the center point of the substrate, and the shape of the emitter-dedicated region is comb-shaped. In the double-sided semiconductor device, the teeth of the emitter-only area on one side face the gaps of the teeth of the emitter-only area on the other side in the direction perpendicular to the main surface of the substrate.
It is assumed that a short-circuit hole reaching the combined base / emitter region and filled with the first conductivity type layer is provided on the outer periphery of the emitter-dedicated region. It is also effective that the peripheral edge of the tooth in the emitter-only area on the one surface side and the peripheral edge of the tooth in the emitter-specific area on the other surface side overlap with the main surface of the substrate in the vertical direction by a width of 10% or less of the width of the tooth portion. is there. It is preferable that the short-circuit hole is provided at an extension of the center line of the comb-shaped tooth. It is also good that the short-circuit hole is provided only in a portion of the outer peripheral portion of the emitter-dedicated area near the outer periphery of the semiconductor substrate. The impurity concentration of the dual-purpose base / emitter region is increased only in the portion of the outer peripheral portion of the emitter-dedicated region that is close to the outer peripheral portion of the semiconductor substrate.・ It is good to reach the area dedicated to the emitter.
No. It is effective that the depth of the emitter-dedicated region is deeper than that of the outer periphery where the short-circuit hole is provided in the inner periphery of the region. The depth of the emitter-dedicated region becomes deeper from the outer periphery toward the inner periphery. It was good that it was done.
【0008】[0008]
【作用】くし型構造は、前記明細書に記載されている通
り、トランジスタで行われているように、周辺長を大き
くすることによって同一占有面積のエミッタ領域の電流
容量を大きくするのに役立つ。従ってサージ電
流に対しても、集中する電流が小 さくなり、電
流集中による耐量低下を緩和することができる。両面型
半導体装置 では、両面側に形成されるくし形構
造を重なり合わせないようにすることにより 、
点対称で形成される双方の層構造を生かすことができ
る。しかし、歯の部分の 周縁部が歯の幅の10
%以下で重なり合う程度ならば、有効な層構造面積を低
減 することが少なく、一方エミッタ領域の周辺
長がいくらか大きくなるので、サー ジ耐量の向
上に対しては有効にはたらくこともある。As described in the above-mentioned specification, the comb structure serves to increase the current capacity of the emitter regions having the same occupation area by increasing the peripheral length, as is done in the transistor. Therefore, even with respect to the surge current, the concentrated current becomes small, and it is possible to mitigate the reduction in withstand amount due to the current concentration. In a double-sided semiconductor device, by preventing the comb-shaped structures formed on both sides from overlapping,
Both layer structures formed with point symmetry can be utilized. However, the circumference of the tooth part is 10
%, The effective layer structure area is less reduced, while the peripheral length of the emitter region is somewhat increased, which may be effective in improving the surge resistance.
【0009】さらにサージ耐量を高めるには、電流の集
中の起こりやすいエミッタ専用領域の外周部、特にその
基板の外周部に近い側の部分からエミッタ専用領域直下
に延 びる部分のベース・エミッタ兼用領域への
注入効率をエミッタ短絡構造で低下さ せる。く
し型構造のエミッタ専用領域の歯の部分の最も奥行きの
深い中心線上に エミッタ短絡のための短絡孔を
設けることは、注入効率の低下に対する作用を強
める。このようなエミッタ短絡構造は、前記明細書に
記載されたエミッタ専用領 域の基板の外周に近
い側の部分の不純物濃度を高くする場合、あるいはエミ
ッタ 専用領域の内周部を外周部より深くする場
合にも併用することにより、サージ耐 量向上の
作用を一層増大する。In order to further increase the surge withstand capability, a base / emitter dual-use region of the outer peripheral portion of the emitter-dedicated region where current concentration is likely to occur, particularly the portion extending from the portion near the outer peripheral portion of the substrate to directly below the emitter-dedicated region. The injection efficiency into the emitter is reduced by the shorted emitter structure. Providing a short-circuit hole for emitter short-circuiting on the deepest center line of the tooth part of the emitter-only area of the comb structure has a strong effect on lowering the injection efficiency.
Meru. Such an emitter short-circuit structure is used when increasing the impurity concentration in the portion of the emitter-dedicated area close to the outer periphery of the substrate described in the above specification, or making the inner peripheral portion of the emitter-dedicated area deeper than the outer peripheral portion. When used together, the effect of improving surge withstand capability is further enhanced.
【0010】[0010]
【実施例】以下図2ないし図4と共通の部分に同一符号
を付した図を引用して本発明の実施例について述べる。
図4と同様の平面図の図1(a)で示した請求項3およ
び4に記載の本発明の一実施例の二端子サイリスタで
は、nエミッタ31、32の外周部のチップ外周
に近い側の部分に短絡孔5が設けられている。図1
(a)のA−A線断面図であ る図1(b)に示
すように、短絡孔5は、エミッタを貫通し、その下のp
+ 層2 1あるいは22に達し、p+ 層23によ
り充てんされている。サージ電圧の印加 された
とき、二端子サイリスタチップの外周からオンする。こ
のオン電流を短絡 孔5を通じて電極へ逃がすこ
とによりサージ電流耐量を向上させることができる
ので、nエミッタ31、32のチップ外周に近い外
周部に短絡孔5を設ける。短 絡孔5の位置は、
エミッタの縁部からエミッタ帯状パターン幅の1/2よ
り外周に近い部分にあることが望ましい。Embodiments of the present invention will be described below with reference to the drawings in which the same parts as those in FIGS.
In a two-terminal thyristor according to one embodiment of the present invention shown in FIG. 1 (a) of a plan view similar to FIG. 4, in the chip outer periphery of the n emitters 31 and 32,
The short-circuit hole 5 is provided in the portion on the side close to. FIG.
As shown in FIG. 1B, which is a cross-sectional view taken along the line AA of FIG. 1A, the short-circuit hole 5 penetrates the emitter, and the p
The + layer 21 or 22 is reached and filled with the p + layer 23. When a surge voltage is applied, it turns on from the outer periphery of the two-terminal thyristor chip. By releasing this on-current to the electrode through the short-circuit hole 5, the surge current withstand capability can be improved.
Therefore, the short-circuit hole 5 is provided in the outer peripheral portion of the n emitters 31 and 32 near the outer periphery of the chip. The position of the short contact hole 5 is
It is desirable to be located closer to the outer circumference than half the width of the emitter strip pattern from the edge of the emitter.
【0011】図5に示した別の実施例では、図1の実施
例における短絡孔5のうち、くし歯部41、42のチッ
プ外周に近い側のものを省いたが、これでも十分効果が
得ら れる。図6(a)、(b)に示した実施例
では、図1の実施例における短絡孔5の数を減らし、く
しの歯の基部の外周部に形成されるものは、各くしの歯
部41ある いは42の最も奥行きの長い中心線
上に1個ずつとした。その代わり、短絡孔5 の
直径dはくしの歯部41、42の幅wの1/3とした。
この実施例では、w= 300μmでd=100
μmである。最外側のくしの歯部41、42の外周部に
形成される短絡孔5の間隔は2w程度、すなわ
ち約600μmにした。In another embodiment shown in FIG. 5, among the short-circuit holes 5 in the embodiment of FIG. 1, those on the side closer to the tip outer circumference of the comb teeth 41, 42 are omitted, but this is also sufficiently effective. can get. In the embodiment shown in FIGS. 6A and 6B, the number of short-circuit holes 5 in the embodiment of FIG. 1 is reduced, and what is formed on the outer peripheral portion of the base of the comb tooth is the tooth portion of each comb. 41 or 42 on the center line with the longest depth. Instead, the diameter d of the short circuit hole 5 was set to 1/3 of the width w of the tooth portions 41 and 42 of the comb.
In this example, w = 300 μm and d = 100.
μm. The distance between the short-circuit holes 5 formed on the outer peripheral portions of the outermost comb teeth 41 and 42 was about 2 w, that is, about 600 μm.
【0012】図7に示す請求項5記載の本発明の実施例
では、n+ エミッタ層くしの歯部41、42のチップ外
周に近い外周部直下にp++層24を形成して、この部分
への nエミッタ層からpベース層への注入効率
を低め、外周部への電流集中を防いで おり、短
絡孔5はそれよりも内側のn+ 層31、32を貫通して
いる。In the embodiment of the present invention as set forth in claim 5 shown in FIG. 7, a p ++ layer 24 is formed immediately below the outer periphery of the tooth portions 41, 42 of the n + emitter layer near the outer periphery of the chip. The injection efficiency from the n-emitter layer to the p-base layer is reduced to prevent the current from concentrating in the outer peripheral portion, and the short-circuit hole 5 penetrates the n + layers 31 and 32 inside thereof.
【0013】図8に示す請求項6および7に記載の本発
明の実施例では、図にn+ 層のくしの歯部41の断面で
示すようにn+ エミッタ層の深さが中央部43で最も深
く、 その外側の部分44で次に深く、最外側部
45で最も浅くして外周部への電流集 中を防
ぎ、さらにその最外側部45に短絡孔5を開けることで
サージ耐量を高く している。図示しないが裏面
側のくしの歯部42においても同様である。In the embodiment of the present invention according to claims 6 and 7 shown in FIG. 8, the depth of the n + emitter layer is the central portion 43 as shown in the cross section of the comb tooth portion 41 of the n + layer in the figure. At the outermost portion, the next deepest portion at the outermost portion 44, and the shallowest portion at the outermost portion 45 to prevent current collection to the outer peripheral portion. It is high. Although not shown, the same applies to the comb teeth 42 on the back side.
【0014】図9に示す請求項1に記載の本発明の実施
例では、n+ エミッタ層のくしの歯部41、42チップ
外周に近い外周部のみでなく、すべての外周部に短絡孔
5を 開けてサージ耐量をさらに高めている。以
上の実施例では、エミッタ専用領域がn形であるが、p
形の場合の双方向二端子サイリスタにも同様に実施でき
ることが明らかである。In the embodiment of the present invention as set forth in claim 1 shown in FIG. 9, the short-circuit holes 5 are formed not only in the outer peripheral portions near the outer peripheral portions of the comb tooth portions 41, 42 of the n + emitter layer but also in all the outer peripheral portions. The surge resistance is further increased by opening the. In the above embodiment, the emitter-dedicated region is n-type, but p-type
It is clear that a two-way two-terminal thyristor in the case of the form can be implemented as well.
【0015】[0015]
【発明の効果】本発明によれば、エミッタ専用領域にく
し形構造を採用するほかに、エミッタ専用領域外周部で
のエミッタ短絡構造を併用することにより、サージ電流
の集中 が防止され、サージ耐量が向上するた
め、サージ耐量特性と保持電流特性のトレ ード
オフが改善された。これにより大きな保持電流でサージ
耐量の大きな両面型 半導体装置が得られ、また
両面型半導体装置のダイサイズを小さくすることがで
きた。さらに、電流集中の起こりやすいエミッタ
専用領域の外周部直下でベース ・エミッタ領域
の不純物濃度を高めて注入効率を落とすか、あるいはト
ランジス タ構造の電流増幅率を、内周部でエミ
ッタ専用領域を深くすることにより外周部 に比
して高めることも併用できるので、サージ耐量の一層の
向上が可能である。According to the present invention, in addition to adopting the comb-shaped structure in the emitter-dedicated region and also using the emitter short-circuit structure in the outer periphery of the emitter-dedicated region, the concentration of surge current is prevented and the surge withstand capability is improved. Therefore, the trade-off characteristics of surge withstanding characteristics and holding current characteristics are improved. As a result, a double-sided semiconductor device with a large holding current and a large surge resistance can be obtained, and the die size of the double-sided semiconductor device can be reduced.
Came. Immediately below the outer periphery of the emitter-dedicated region where current concentration is likely to occur, increase the impurity concentration in the base / emitter region to reduce the injection efficiency, or increase the current amplification factor of the transistor structure to make the emitter-dedicated region deeper in the inner periphery. By doing so, it is possible to use it together with the increase in the outer peripheral portion, so that the surge withstand capability can be further improved.
【図1】本発明の一実施例の双方向二端子サイリスタを
示し、(a)は半導体基板の平面図、(b)は(a)の
A−A線断面図1A and 1B show a bidirectional two-terminal thyristor according to an embodiment of the present invention, FIG. 1A is a plan view of a semiconductor substrate, and FIG. 1B is a sectional view taken along line AA of FIG.
【図2】従来の双方向二端子サイリスタの切断斜視図FIG. 2 is a cutaway perspective view of a conventional bidirectional two-terminal thyristor.
【図3】くし型構造のエミッタをもつ双方向二端子サイ
リスタの切断斜視図FIG. 3 is a cut-away perspective view of a bidirectional two-terminal thyristor having a comb-shaped emitter.
【図4】図3のサイリスタの半導体基板の平面図4 is a plan view of a semiconductor substrate of the thyristor of FIG.
【図5】本発明の異なる実施例の双方向二端子サイリス
タ半導体基板の平面図FIG. 5 is a plan view of a bidirectional two-terminal thyristor semiconductor substrate according to a different embodiment of the present invention.
【図6】本発明の異なる実施例の双方向二端子サイリス
タを示し、(a)が半導体基板の平面図、(b)が
(a)のB−B線断面図FIG. 6 shows a bidirectional two-terminal thyristor according to another embodiment of the present invention, in which (a) is a plan view of a semiconductor substrate and (b) is a sectional view taken along line BB of (a).
【図7】本発明の異なる実施例の双方向二端子サイリス
タ半導体基板の平面図FIG. 7 is a plan view of a bidirectional two-terminal thyristor semiconductor substrate according to another embodiment of the present invention.
【図8】本発明の異なる実施例の双方向二端子サイリス
タ半導体基板の断面図FIG. 8 is a sectional view of a bidirectional two-terminal thyristor semiconductor substrate according to another embodiment of the present invention.
【図9】本発明の異なる実施例の双方向二端子サイリス
タ半導体基板の平面図FIG. 9 is a plan view of a bidirectional two-terminal thyristor semiconductor substrate according to another embodiment of the present invention.
1 n- 層 21、22、23 p+ 層(ベース・エミッタ兼用領
域) 24 p++層 31、32 n+ 層(エミッタ専用領域) 41、42 くしの歯部 5 短絡孔1 n - layer 21, 22, 23 p + layer (base-emitter combined region) 24 p ++ layer 31 and 32 n + layer (emitter-only area) 41 comb teeth 5 shunt hole of
Claims (7)
ス・エミッタ兼用領域およびその領域の表面層に形成さ
れた第二導電形のエミッタ専用領域が露出し 、
両面側のベース・エミッタ兼用領域とエミッタ専用領域
との形状が基板の中心 点に対し点対称であり、
エミッタ専用領域の形状がくし形であり、一面側のエミ
ッタ専用領域の歯の部分が他面側のエミッタ専
用領域の歯の間隙部分に基板主面 に垂直方向で
対向する両面型半導体装置において、エミッタ専用領域
の外周部に 、ベース・エミッタ兼用領域に達
し、第一導電形層によって充てんされた短絡孔
が設けられたことを特徴とする両面型半導体装置。1. A base / emitter dual-use region of the first conductivity type and a second conductivity type emitter-dedicated region formed in a surface layer of the region are exposed on both main surface sides of a semiconductor substrate,
The shapes of the base / emitter combined area and the emitter-only area on both sides are point-symmetric with respect to the center point of the substrate.
In a double-sided semiconductor device where the emitter-dedicated region has a comb shape, and the teeth of the emitter-dedicated region on one side face the gap between the teeth of the emitter-dedicated region on the other side in the direction perpendicular to the main surface of the substrate. A short-circuit hole that reaches the combined base / emitter region and is filled with the first conductivity type layer on the outer periphery of the emitter-dedicated region.
A double-sided semiconductor device comprising:
他面側のエミッタ専用領域の歯の周縁部が歯の部分の幅
の10%以下の幅だけ基板主面に垂直方向で 重
なり合う請求項1記載の両面型半導体装置。2. A peripheral edge of a tooth of the emitter-dedicated area on one surface side and a peripheral edge of the tooth of an emitter-dedicated area on the other surface side overlap each other in a direction perpendicular to the main surface of the substrate by a width of 10% or less of the width of the tooth portion. The double-sided semiconductor device according to claim 1.
部に設けられた請求項1あるいは2記載の両面型半導体
装置。3. The double-sided semiconductor device according to claim 1, wherein the short-circuit hole is provided in an extension of the center line of the teeth of the comb-shaped base.
ちの半導体基板の外周に近い側の部分にのみ設けられた
請求項1ないし3のいずれかに記載の両面型 半
導体装置。4. A double-sided semiconductor device according to claim 1, wherein the short-circuit hole is provided only in a portion of the outer peripheral portion of the emitter-dedicated region near the outer periphery of the semiconductor substrate.
基板の外周に近い側の部分に近接する部分のみ、ベース
・エミッタ兼用領域の不純物濃度が高くされ 、
短絡孔がその不純物濃度の高い領域の内側でベース・エ
ミッタ兼用領域に達す る請求項1ないし4のい
ずれかに記載の両面型半導体装置。5. The impurity concentration of the dual-purpose base / emitter region is increased only in a portion of the outer peripheral portion of the emitter-dedicated region which is close to a portion closer to the outer periphery of the semiconductor substrate,
5. The double-sided semiconductor device according to claim 1, wherein the short-circuit hole reaches the combined base / emitter region inside the region having a high impurity concentration.
部において短絡孔の設けられる外周部より深くされた請
求項1ないし5記載の両面型半導体装置。6. A double-sided semiconductor device according to claim 1, wherein the depth of the region dedicated to the emitter is made deeper than the outer peripheral portion where the short-circuit hole is provided in the inner peripheral portion of the region.
部に向かうに従って深くされた請求項6記載の両面型半
導体装置。7. The double-sided semiconductor device according to claim 6, wherein the depth of the emitter-dedicated region is increased from the outer peripheral portion toward the inner peripheral portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17832595A JP3253493B2 (en) | 1995-07-14 | 1995-07-14 | Double-sided semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17832595A JP3253493B2 (en) | 1995-07-14 | 1995-07-14 | Double-sided semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0936347A true JPH0936347A (en) | 1997-02-07 |
JP3253493B2 JP3253493B2 (en) | 2002-02-04 |
Family
ID=16046519
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JP17832595A Expired - Fee Related JP3253493B2 (en) | 1995-07-14 | 1995-07-14 | Double-sided semiconductor device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102656670A (en) * | 2009-12-21 | 2012-09-05 | Nxp股份有限公司 | Semiconductor device with multilayer contact and method of manufacturing the same |
-
1995
- 1995-07-14 JP JP17832595A patent/JP3253493B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102656670A (en) * | 2009-12-21 | 2012-09-05 | Nxp股份有限公司 | Semiconductor device with multilayer contact and method of manufacturing the same |
US9331186B2 (en) | 2009-12-21 | 2016-05-03 | Nxp B.V. | Semiconductor device with multilayer contact and method of manufacturing the same |
US9466688B2 (en) | 2009-12-21 | 2016-10-11 | Nxp B.V. | Semiconductor device with multilayer contact and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JP3253493B2 (en) | 2002-02-04 |
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