JPH0936246A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and substrate bias circuits which can improve the operating speeds of substrates at active time and can reduce the power consumptions of the substrates standby time by controlling the threshold voltages of the substrates by changing the biases of the substrates between the active time and standby time. SOLUTION: The P-type silicon substrates 104a and 104b of an NMOS formed on an SOI substrate are set at grounding potentials at active time and potentials lower than the grounding potentials at standby time and the N-type silicon substrates 10a and 106b of a PMOS are set at power supply potentials at the active time and potentials higher than the power supply potentials at the standby time. Since the capacities of the silicon substrates are small, the power consumptions of bias circuits 110 and 110 can be reduced at the standby time.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device that operates at high speed in active mode and can reduce power consumption in standby mode by changing the threshold voltage of MOSFET between active mode and standby mode.

[0002]

2. Description of the Related Art In recent years, the market demand for low power consumption has been increasing mainly in the field of portable electronic information devices, and the power supply voltage of LSI has been reduced to meet the demand, but the power supply voltage of LSI is lowered. Accordingly, it is becoming difficult to achieve both high-speed operation when the LSI is active and low power consumption during standby. That is, the operating speed of the gate circuit composed of the MOSFETs that constitute the LSI is the power supply voltage VDD, the MOSFET
Of the power supply voltage Vt without changing the threshold voltage VT since it is proportional to (VDD-VT) ₂ approximately.
This is because if the DD is decreased, the operating speed is drastically decreased. To prevent this, the threshold voltage VT is also set to the power supply voltage V
This is because the subthreshold current flowing through the MOS transistor increases when it is decreased at the same time as DD, and power consumption increases during standby when the LSI is not operating. Needless to say, high-speed operation is required in the field of portable electronic information devices, but standby power consumption is a major factor that determines battery life, so
In the region where the power supply voltage VDD is 2 V or less, it is an important technical issue to satisfy both of them.

As a technique for achieving both high speed at the time of active and low power at the time of standby, by controlling the potential of the well, the threshold voltage of the MOSFET is lowered at the time of active to enable a high speed operation, and the threshold voltage is set at the time of standby. A technique for reducing power consumption by increasing the current in the subthreshold region has been proposed. For example, in Japanese Unexamined Patent Publication No. 4-302897, the substrate bias of a MOSFET forming a peripheral circuit portion of a dynamic semiconductor memory device (DRAM) is made different between active and standby, and an N-channel MOSFET (hereinafter referred to as NMOS A negative voltage equal to or lower than the ground voltage,
By applying a static voltage higher than the power supply voltage to the N-type well in which a P-channel MOSFET (hereinafter referred to as PMOS) is formed, the absolute value of the threshold voltage of the PMOS and NMOS is increased to reduce the power consumption during standby. The technology is disclosed.

The structure and operation of the prior art disclosed in Japanese Patent Laid-Open No. 4-302897 will be described below with reference to FIG.

In FIG. 6, a first circuit block and a second circuit block are formed on the surface of an N-type silicon substrate 301, and the first circuit block is N-shaped by a bias circuit 310 for the first circuit block. The potentials of the type well 306a and the second P-type well 304a are controlled, the N-type well 306a is surrounded by the first P-type well 302a formed in contact with the second P-type well 304a, and the N-type silicon substrate is formed. Similarly, the second circuit block is electrically separated from 301, and the second circuit block is the bias circuit 3 for the second circuit block.
11, the N-type well 306b and the second P-type well 30
4b is controlled so that the N-type well 306b has a second P
It is surrounded by the first P-type well 302b formed in contact with the mold well 304b and is electrically separated from the N-type silicon substrate 301. That is, when the first circuit block is in the active state, the first output terminal VA1 of the bias circuit 310 for the first circuit block connected to the N-type well 306a becomes the power supply voltage level and the N-type well 306a. The threshold voltage of the PMOS formed of the P type diffusion layer 307, the gate insulating film 308, and the polysilicon gate electrode 309 formed inside is stabilized to a small value in absolute value at the time of activation, and is simultaneously connected to the P type well 304a. The second output terminal VA2 becomes the ground level and the threshold voltage of the NMOS formed of the N-type diffusion layer 305, the gate insulating film 308, and the polysilicon gate electrode 308 formed in the second P-type well 304a is small when active. Stabilize to a value. When the first circuit block is in the standby state, the first output terminal VA1 of the bias circuit 310 for the first circuit block has a potential level higher than the power supply voltage and is formed in the N-type well 306a. The second threshold value which changes the threshold voltage of the PMOS to a value larger in absolute value than the active value and is connected to the P-type well 304a at the same time.
Output terminal VA2 has a potential level lower than the ground potential and the NMOS formed in the second P-type well 304a.
The threshold voltage of is changed to a value larger than the active value.

The threshold voltage values of the PMOS and NMOS are set small to enable high speed operation when active,
By setting the potentials of VA1 and VA2 during standby so that a threshold voltage with a sufficiently small subthreshold current can be obtained, both high-speed operation during active and low power consumption during standby can be achieved.

The same applies to the second circuit block. When the second circuit block is in the active state, the first output of the bias circuit 311 for the second circuit block connected to the N-type well 306b. The terminal VB1 becomes the power supply voltage level and stabilizes the threshold voltage of the P-channel MOSFET formed in the N-type well 306b to a small value in absolute value when active, and at the same time, the P-type well 30
The second output terminal VB2 connected to 4b becomes the ground level and the NMO formed in the second P-type well 304b.
The threshold voltage of S is stabilized to a small value when active.
When the second circuit block is in the standby state, the output terminal VB1 of the bias circuit 311 for the second circuit block is at a potential level higher than the power supply voltage and N
Changing the threshold voltage of the PMOS formed in the mold well 306b to a value larger in absolute value than the active value,
At the same time, the second output terminal VB2 connected to the P-type well 304b has a potential level lower than the ground potential, and the threshold voltage of the NMOS formed in the second P-type well 304a is higher than the active value. Change to a value.

Further, in the conventional example of FIG. 6, the N-type well 306a of the first circuit block is surrounded by the P-type well 302a having the same potential as the P-type well 304a, and the N-type silicon substrate 3 is formed.
01, and the N-type well 306b of the second circuit block is surrounded by the P-type well 302b having the same potential as the P-type well 304b.
Since it is electrically separated from 01, the threshold voltage control when the first circuit block is active and in the standby state and the threshold voltage control when the second circuit block is in the active and standby states can be independently performed. It also has the advantage.

However, in the conventional example of FIG. 6, the first P-type well 302a and the N-type well 306a or 30 are used.
Since 2b and 306b are in contact with each other in a large area and the junction capacitance is large, when the active state changes to the standby state, VA1,
Electric charges are supplied from VB1 to 306a and 306b to change the potential of the N-type well to a potential higher than the power supply voltage.
2, by extracting charges from VB2 from the first P-type wells 302a and 302b and the second P-type wells 304a and 304b, the threshold voltages of the PMOS and the NMOS are rapidly increased in absolute value to increase the subthreshold current. To reduce, the bias circuit 310 for the first circuit block and the bias circuit 3 for the second circuit block
Although it is necessary to increase the charge supply capability of 11, the bias circuits 310 and 311 continue to operate during the standby period, resulting in an increase in standby power consumption, and an expected reduction in standby power is achieved. There is a problem that you cannot do it. For example, the first circuit block,
In a large-scale integrated circuit in which 1 million transistors are mounted on the second circuit block according to the design rule of 0.35 μm, the junction capacitance between the N well 306a and the first P well 302a and the N well 306b and the first P well 302b is Since each of them is about 22,000 pF, it is necessary to reduce the junction capacitance to reduce the power consumption of the bias circuits 310 and 311 in order to truly reduce the power consumption during the standby period.

[0010]

In the conventional semiconductor device shown in FIG. 6, when a large-scale integrated circuit is constructed, the first P
Since the type well 302a or 302b and the N-type well 306a or 306b are in contact with each other in a large area and the matching capacitance is large, VA1, VB1 are generated when the active type changes to the standby state.
To 306a, 306b to change the potential of the N-type well to a potential higher than the power supply voltage.
B2 to the first P-type wells 302a and 302b and the second
In order to quickly increase the threshold voltages of the PMOS and NMOS in absolute value and reduce the subthreshold current by extracting charges from the P-type wells 304a and 304b, the bias circuit 3 for the first circuit block is used.
10 and the bias circuit 311 for the second circuit block need to have a large charge supply capability, which consumes power, resulting in an increase in power consumption during standby, and as expected, during standby. However, there is a problem that the power reduction cannot be achieved.

Therefore, an object of the present invention is to provide a semiconductor device capable of reliably reducing power consumption during standby.

[0012]

A first semiconductor device according to the present invention comprises a plurality of P-channel MOSFETs and a plurality of N-channel Ms formed on a silicon-on-insulator substrate.
An OSFET and a bias circuit are included. The bias circuit supplies a power supply voltage to the silicon base portion below the gate electrode of at least a part of the P-channel MOSFETs of the plurality of P-channel MOSFETs at the time of active, and the standby circuit at the time of standby. In addition to supplying a voltage higher than the power supply voltage, at least a part of the plurality of N-channel MOSFETs is supplied with a ground potential to the silicon base portion below the gate electrode of the N-channel MOSFET when active and is higher than the ground potential during standby. It is to supply a low voltage.

According to a second semiconductor device of the present invention, a plurality of functional circuit blocks including a plurality of P-channel MOSFETs and a plurality of N-channel MOSFETs formed on a silicon-on-insulator substrate, and at least one of the functional circuits. A power supply voltage is supplied to the silicon base portion below the gate electrode of the P-channel MOSFET in the block when active, a voltage higher than the power supply voltage is supplied during standby, and the N-channel MOSFE is supplied.
The silicon base portion below the gate electrode of T includes a bias circuit that supplies a ground potential when active and supplies a voltage lower than the ground potential during standby.

A preferred bias circuit for the first and second semiconductor devices is a pulse generating circuit for generating a continuous pulse when the signal at the input terminal is at a predetermined level, and one source / drain electrode and gate electrode at the ground terminal. A connected first P-channel MOSFET, an output terminal of the pulse generating circuit and the other source of the first P-channel MOSFET
A first capacitive element inserted between the drain electrode and the first source / drain electrode; a first capacitive element inserted between the source / drain electrode and the first P-channel; A second P-channel MOSFET connected to the other source / drain of the MOSFET and the other source / drain electrode thereof connected to the first output terminal, and a second P-channel MOSFET having one source / drain electrode and the gate electrode connected to the power supply terminal. One N-channel MOSFET, a second capacitance element inserted between the output terminal of the pulse generation circuit and the other source / drain of the first N-channel MOSFET, and one source / drain electrode and gate electrode Is connected to the other source / drain electrode of the first N-channel MOSFET, and the other source / drain electrode is the second source / drain electrode.
Second N-channel MOSFET connected to the output terminal of the
A charge pump circuit, an inverter circuit having an input terminal connected to the input terminal, a third electrode having a source electrode and a base electrode connected to the power supply terminal, and a gate electrode connected to an output terminal of the inverter circuit. Channel MOSFE
T and drain electrodes are the third P-channel MOSFET
A third N-channel MOSFE having a gate electrode connected to the output terminal of the inverter circuit and a source electrode and a substrate electrode connected to the first output terminal
A fourth N-channel MOSFET in which the T and drain electrodes are connected to the ground terminal, a gate electrode is connected to the drain of the third P-channel MOSFET, and a source electrode and a body electrode are connected to the first output terminal. A pull-up circuit, a fifth N-channel MOSFET having a source electrode and a base electrode connected to the ground terminal and a gate electrode connected to the input terminal, and a drain electrode connected to a drain electrode of the fifth N-channel MOSFET. A fourth P-channel MOSF having a gate electrode connected to the input terminal and a source electrode and a substrate electrode connected to the second output terminal
ET and a fifth P-channel MOSFET having a drain electrode connected to the power supply terminal, a gate electrode connected to the drain of the fifth N-channel MOSFET, and a source electrode and a body electrode connected to the second output terminal And a pull-down circuit that in this case,
First P-channel MOSFET and second P-channel M
The substrate electrode of the OSFET is connected to the power supply terminal, and the first N
Channel MOSFET and second N-channel MOSFE
More preferably, the base electrode of T is connected to the ground terminal.

Silicon-on-insulator (SO
I) Since the bottom surface of the silicon substrate of the MOSFET formed on the substrate is in contact with the thick insulating film and the side surfaces are in contact with the source / drain diffusion layer and the insulating film, the parasitic capacitance can be reduced, and thus the capacitance driven by the bias circuit. Can be reduced.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic sectional view schematically showing a first embodiment of the present invention. FIG. 2 is a plan view showing the device structure of the first circuit block in the present embodiment more concretely by taking a CMOS inverter as an example, FIG.
(B), (c) is the AA sectional view taken on the line of FIG. 2, the BB sectional view, and the CC sectional view.

This embodiment uses an SOI substrate based on SIMOX technology. That is, the silicon substrate 1
On the buried oxide film 102 formed on 01, the NMOS 11 and the PMOS 12, which belong to the first circuit block and are isolated by the silicon oxide film 103, and the NMOS 13 and the PMOS 14, which belong to the second circuit block, are formed.
The NMOS 11 of the first circuit block is self-aligned with the polysilicon gate electrode 109 formed on the P-type silicon substrate 104a (connected to the N-type diffusion layer 104ac) via the gate oxide film 108 as the substrate. Pair of N-type diffusion layers 1 forming source / drain electrodes formed on the substrate
05 is provided, and the PMO of the first circuit block 1 is provided.
S12 is a polysilicon gate electrode 109 formed on the N-type silicon substrate 106a (connected to the P-type diffusion layer 106ac) serving as a substrate via the gate oxide film 108 and a source / A pair of P-type diffusion layers 107 that form the drain electrode are provided. Similarly, the NMOS 13 of the second circuit block is a base P
A polysilicon gate electrode 109 formed via a gate oxide film 108 on a type silicon substrate 104b and a pair of N type diffusion layers 105 that are formed in self-alignment with the polysilicon gate electrode 109 to form source / drain electrodes are formed. And second
In the circuit block, the PMOS 14 is formed in a self-aligned manner with the polysilicon gate electrode 109 formed on the N-type silicon substrate 106b serving as a substrate via the gate oxide film 108 to form source / drain electrodes. A pair of P-type diffusion layers 107 are provided. The P-type silicon substrate 104a of the NMOS 11 of the first circuit block is connected to the second output terminal VA2 of the bias circuit 110 for the first circuit block, and the PMOS of the first circuit block is PMOS.
The N-type silicon substrate 106a of 12 is connected to the first output terminal VA1 of the bias circuit 110 for the first circuit block, and the P-type silicon substrate 104b of the NMOS 13 of the second circuit block is the second circuit block. Is connected to the second output terminal VB2 of the bias circuit 111 for
N-type silicon substrate 10 of PMOS 14 of the circuit block
6b is connected to the first output terminal VB1 of the bias circuit 111 for the second circuit block. Note that 404 is a wiring formed of an Al-Si alloy film or the like, and, for example, 404 (GND) is a ground wiring formed of an Al-Si alloy film. Ground wiring 404 (GND), power wiring 404 (V
DD) and the output signal line 404 (OUT) are connected to one N-type diffusion layer 105, one P-type diffusion layer 107, the other N-type diffusion layer 105, and the other P-type diffusion layer 107 through the contact holes 401, respectively. It is connected. The first output wiring 404 (VA1) is connected to the N-type diffusion layer 104ac through the contact hole 402, and the second output wiring (VA2).
Is connected to the P-type diffusion layer 106ac through the contact hole 403. The input signal line 404 (S1) is connected to the polysilicon gate electrode 109 via the contact hole 402. The input signal line 404 (S2) is an input signal line of a circuit (not shown).

Bias circuit 11 for the first circuit block
0 is output terminal VA1, VA2 according to input signal ACT1
Voltage changes, the power supply potential is output to VA1 when the first circuit block is in the active state, the ground potential is output to VA2, and the VA1 is higher than the power supply potential and the VA2 is lower than the ground potential in the standby state. Output the electric potential. As a result, when active, NMOS 11 and PMOS 1
Since the threshold voltage of 2 is small in absolute value, the first circuit block can operate at high speed, and the NMOS 1
As in the prior art example of FIG. 6, it is possible to reduce the power consumption in the first circuit block because the threshold voltages of 1 and the PMOS 12 increase in absolute value. Further, in the bias circuit 111 for the second circuit block, the voltage of the output terminals VB1 and VB2 is changed by the input signal ACT2, and when the second circuit block is in the active state, the power source potential is set to VB1 and VB1.
The ground potential is output to B2, and VB1 is output in the standby state.
A potential higher than the power supply potential and a potential lower than the ground potential are output to VB2. As a result, the high-speed operation of the second circuit block in the active state and the low power consumption in the standby state are achieved as in the conventional example of FIG.

In the present embodiment, the capacitance driven by the bias circuit 110 for the first circuit block or the bias circuit 111 for the second circuit block can be reduced as compared with the conventional example of FIG. Circuits 110,1
The power consumption of 11 can be reduced. In FIG. 1, PMOS1
The N-type silicon substrate 106a, which is the second substrate, is a very small region covered with the P-type diffusion layer 107 and the silicon oxide film 103 whose bottom faces are in contact with the thick buried silicon oxide film 102 and whose side faces form source / drain. Therefore, the parasitic capacitance can be reduced, and the bottom surface of the P-type silicon substrate 104a that is the base of the NMOS 11 is in contact with the thick buried silicon oxide film 102, and the side surface forms the source / drain. This is because the parasitic capacitance can be reduced because the region covered with the silicon oxide film 103 can be made extremely small. For example, assuming that 1 million transistors (however, the thickness of the silicon substrate is 100 nm) are mounted on each of the first circuit block and the second circuit block according to the design rule of 0.35 μm, VA1 of the bias circuit 110 is set. , VA2 and bias circuit 11
When the load capacities of VB1 and VB2 of No. 1 are calculated, they become 1,000 pF, respectively, which can be reduced to 1/20 or less compared with the estimated value of about 22,000 pF in the conventional example of FIG. Power consumption of the bias circuits 110 and 111 of FIG. 1 in this state can be reduced to 1/20 as compared with the bias circuits 310 and 311 of FIG.

FIG. 4A is a circuit diagram showing a first example of the bias circuit used in the present embodiment, and FIG. 4B is FIG.
It is a signal waveform diagram for demonstrating operation | movement of the bias circuit shown to (a).

This bias circuit generates a continuous pulse when the signal at the input terminal ACT is at a high level to generate the input signal A.
A pulse generation circuit 201 (comprising NOR gate 201-1 and inverter circuits 201-2 and 201-3) that stops generation of pulses when CT is at a low level, and a ground terminal GN.
A first PMOS 202 having one source / drain electrode and a gate electrode connected to D, and a first capacitor inserted between the output end of the pulse generation circuit 201 and the other source / drain electrode of the first PMOS 202. Element 206, one source / drain electrode and gate electrode of which is the first PMOS 2
A second PMOS 203 connected to the other source / drain electrode of 02 and the other source / drain electrode connected to the first output terminal VA1, and one source / drain electrode and gate electrode connected to the power supply terminal VDD. First NM
OS204, the output terminal of the pulse generation circuit 201 and the first N
The second capacitor element 207 inserted between the other source / drain electrode of the MOS 204 and one source / drain electrode and the gate electrode are connected to the other source / drain electrode of the first NMOS 204, and the other source / drain electrode is connected. A charge pump circuit including a second NMOS 205 connected to the drain electrode and the other source / drain electrode connected to the second output terminal VA2, an inverter circuit 205 having an input terminal connected to the input terminal ACT, and a source electrode A third PMOS 20 whose base electrode is connected to the power supply terminal VDD and whose gate electrode is connected to the output terminal of the inverter circuit 208.
9. The drain electrode is connected to the drain electrode of the third PMOS 209, the gate electrode is connected to the output terminal of the inverter circuit 208, and the source electrode and the base electrode are the first output terminal V.
The third NMOS 210 connected to A1 and the drain electrode are connected to the ground terminal GND, and the gate electrode is the third PM.
A fourth NMOS2 connected to the drain of the OS209 and having a source electrode and a body electrode connected to the first output terminal VA1.
13, a source electrode and a base electrode are connected to a ground terminal GND, and a gate electrode is an input terminal ACT.
Connected to the fifth NMOS 211, the drain electrode is connected to the drain electrode of the fifth NMOS 211, the gate electrode is connected to the input terminal ACT, the source electrode and the base electrode are connected to the second output terminal VA2
And a drain electrode connected to the power supply terminal VDD, a gate electrode connected to the drain of the fifth NMOS 212, a source electrode, and a body electrode connected to the second output terminal VA2, and a pull-down circuit including a fifth PMOS 214. ing. First PMOS 202 and second PMOS 203
Each of the base electrodes of the
The body electrodes of the NMOS 204 and the second NMOS 205 are connected to the ground terminal GND. Further, NOR gate 201-1 and inverter circuits 201-2, 201
-3 and 208 are composed of CMOS, and it is not necessary to supply a fixed potential to the base electrode of the transistor of this CMOS, but needless to say, it may be connected to the power supply terminal VDD for PMOS and the ground terminal GND for NMOS. Absent.

Next, referring to FIG. 4B, FIG.
The operation of the bias circuit will be described. Input terminal AC
When the signal of T is at high level (potential level of VDD), that is, in the active state, the potential at the output terminal A of the pulse generation circuit 201 is at low level (GND) and PMO.
A connection point B between the S202 and the PMOS 203 is a value between −VTP and VTP (shown as a GND level in the figure) when the threshold voltage of the PMOS is VTP (negative value), and the NMOS is NMOS.
A connection point C between the 204 and the NMOS 205 is VDD + VTN to VD when the threshold voltage of the NMOS is VTN (positive value).
Since the output terminal of the inverter circuit 208 is at the GND level, the PMOS 209 is in the ON state, the NMOS 210 is in the OFF state, and the drain of the PMOS 209 and NM.
The connection point D to the drain of the OS 210 is at the VDD level, and the NMOS 213 is in the ON state, so the first output terminal VA1 outputs the GND level. Also N
Since the gate electrodes of both the MOS211 and the PMOS212 are connected to the input terminal ACT, they are in the ON state and the OFF state, respectively, and the drain of the NMOS211 and the PM
The connection point E of the drain of the OS 212 is at the GND level, and since the PMOS 214 is in the on state, the second output terminal VA2 outputs the VDD level.

Next, when the signal at the input terminal ACT changes to low level (GND level) to enter the standby state,
A continuous pulse is generated at the output terminal A of the pulse generation circuit 201. When the potential at the point A reaches the VDD level by the first pulse, the potential at the connection point B changes to the first capacitive element 206.
It rises momentarily toward VDD level via PMO
Since it discharges through S202, it settles at the value of -VTP. Next, when the potential at the point A drops to the GND level, the potential at the connection point B is -VT via the first capacitive element 206.
Although it momentarily drops toward P-VDD, it is charged from the first output terminal VA1 having a large load capacitance through the PMOS 203 and settles to a certain value V1 lower than -VTP and higher than -VTP-VDD. At this time, the potential of VA1 settles to a voltage higher than V1 by −VTP because of the presence of the PMOS 203. The potential of the point A becomes VD by the next second pulse.
When the level becomes D level, the potential at the connection point B becomes the first level again.
It momentarily rises toward VDD-VTP through the capacitive element 206 of the
Settles in the value of. Next, when the potential at the point A drops to the GND level, the potential at the connection point B again becomes the first capacitive element 20.
Although it instantaneously drops toward −VTP−VDD via 6, it is charged from the first output terminal VA1 having a large load capacitance through the PMOS 203, and thus falls to a potential V2 lower than the previous potential V1. At this time, the VA1 potential is V2
Settles to a potential higher by -VTP. Thus, by continuously applying the pulse to the point A, the amplitude of the point B finally has a high level of -VTP and a low level of -VTP-V.
It stabilizes at DD, the potential of VA1 gradually decreases, and is higher than the low level at the point B by the absolute value of the threshold voltage of the PMOS 203 −
Stabilizes to 2VTP-VDD. Therefore -2VTP <VD
If D, a negative voltage lower than the GND level can be obtained at VA1. On the other hand, in standby mode, ACT is GN
Since it is at the D level, the potential at the output end of the inverter circuit 208 is at the VDD level during the standby period, and P
The MOS 209 is off and the NMOS 210 is on. Therefore, the potential of the connection point D decreases in accordance with the decrease in the potential of VA1. Therefore, even if the potential of VA1 decreases below the GND level, the potential difference between the source and the gate of the NMOS 213 increases and the NMOS 213 turns on to turn on the GND terminal. And VA
It prevents the generation of a current path between 1 and 2.

Similarly, the potential at the point A is V in the first pulse.
When reaching the DD level, the potential at the connection point C instantaneously rises toward 2VDD through the second capacitive element 207, but through the NMOS 205 the second load having a large load capacitance.
Of the output terminal VA2, the output voltage VA2 is set to a certain value V3 lower than 2VDD and higher than VDD-VTN (VTN is a positive value). At this time, the potential of VA2 settles at a potential lower than V3 by VTN because of the presence of the NMOS 205. Next, when the potential at the point A drops to the GND level, the potential at the connection point C instantaneously drops toward the V3-VDD level via the second capacitive element 207, but since it charges through the NMOS 204, it becomes the value of VDD-VTN. Calm down. When the potential at the point A reaches the VDD level in the next second pulse, the potential at the connection point C momentarily rises toward 2VDD-VTN via the second capacitive element 207, but the NMOS
The second output terminal V having a large load capacity through 205
Since it is discharged to A2, it settles at a potential V4 higher than the previous potential V3. At this time, the potential of VA2 is VT rather than V4.
Settle down to a potential that is N minutes lower. Next, when the potential at the point A drops to the GND level, the potential at the connection point C instantaneously drops again toward V4-VDD via the second capacitive element 207, but is charged through the NMOS 204 to reach the value of VDD-VTN. Calm down. In this way, by continuously applying the pulse to the point A, the amplitude of the point C finally has a high level of 2V.
At DD-VTN, the low level stabilizes at VDD + VTN,
The potential of VA2 rises sequentially and becomes NM from the high level at point C.
It stabilizes at 2VDD-2VTN, which is lower by the threshold voltage of OS205. Therefore, if 2VTN <VDD, VA2 becomes VD
A voltage higher than the D level can be obtained. On the other hand, in standby mode, ACT is at GND level, so NMOS
211 is off and PMOS 212 is on.
Therefore, the potential of the connection point E rises following the rise of the potential of VA2. Therefore, even if the potential of VA2 rises above the VDD level, the potential difference between the source and gate of the PMOS 214 increases, turning on the PMOS 214 and turning on the VDD terminal. It prevents the generation of a current path between VA2 and VA2.

Next, when the signal at the input terminal ACT changes to the high level (VDD level) again and becomes the active state, the pulse generating circuit 201 stops the generation of the pulse and the potential at the output terminal A is at the GND level. Fixed to the PM
The connection point B between the OS 202 and the PMOS 203 takes a value between VTP and -VTP (indicated as GND level in the figure) depending on the timing of pulse stop. Similarly, the connection point C between the NMOS 204 and the NMOS 205 is VDD-VTN to VD.
The value becomes a value between D + VTN (indicated by VDD level in the figure), and the output terminal of the inverter circuit 208 becomes GND level, so the NMOS 209 is turned on, but immediately after the ACT signal changes, the potential of VA1 is -2VTP-VDD. Therefore, the potential difference between the gate and the source of the NMOS 210 is VDD + 2VTP, and when this is higher than the threshold voltage VTN of the NMOS 210, the NMOS 210 is not turned off and both the PMOS 209 and the NMOS 210 are turned on, so that the connection point D is initially at the VDD level. And the GND level, but the level at the connection point D is NMOS.
If 213 can be turned on, the first output terminal VA1 starts to rise toward the GND level, and when VA1 rises, the NMOS 210 approaches the off state, so the potential at the connection point D rises and the potential at VA1 becomes GND. A feedback operation is performed to expedite the return to the level. In order to more stably and quickly change the potential of VA1 to the GND level, the equivalent resistance of the NMOS 210 in the ON state is much larger than the equivalent resistance of the PMOS 209 in the ON state, and the potential of the connection point D is close to the VDD level. It should be set so that it becomes a value. Similarly, NMO
Since the gate electrodes of both S211 and PMOS 212 are connected to the input terminal ACT, the NMOS 211 is turned on, but the PMOS 212 is not turned off, and the drain connection point E is at an intermediate level, but the connection point E level is PM.
If the OS 214 can be turned on, the second output terminal VA2 starts falling toward the VDD level, and VA
When the value of 2 drops, the PMOS 212 approaches the off state, so that the potential of the connection point E further drops and the feedback operation of speeding up the restoration of the potential of VA2 to the VDD level is performed. More stable and promptly change the potential of VA2 to V
In order to change to the DD level, the equivalent resistance in the ON state of the PMOS 212 may be set to be much larger than the equivalent resistance in the ON state of the NMOS 211, and the potential at the connection point E may be set to a value close to the GND level.

As described above, the present bias circuit quickly returns from standby to active.

In the bias circuit of FIG. 4A, the NMOS base electrode forming the pull-up circuit and the pull-down circuit is electrically separated from the GND terminal and connected to the source electrode, and the PMOS base electrode is VDD. Although it is used by being electrically separated from the terminal and connected to the source electrode, in the present embodiment, the silicon-on-insulator (SO
I) There is no particular problem because the PMOS and NMOS are formed on the substrate. In a well semiconductor bulk semiconductor device (such as the one disclosed in Japanese Patent Laid-Open No. 4-302897), the well isolation structure is complicated, and the parasitic capacitance is large, which impedes high-speed operation and reduces the power consumption of the bias circuit itself. Is superior in comparison with the disadvantage that it becomes large. Further, when the parasitic capacitance is large, the standby-active transition time becomes long, and there is a drawback that switching from the standby to the active is not performed promptly, but the present invention is effective from this point as well. In particular, the bias circuit according to the present embodiment is excellent in that the standby operation is quickly switched to the active state by the feedback operation described above.

The bias circuit is not limited to the one described above. For example, as shown in FIG. 5, as a pull-up circuit, a P in depletion mode is used.
The MOS 213A and the depletion mode NMOS 214A may be used as the pull-down circuit. This bias circuit has the advantage that the number of elements is small,
Since the depletion mode transistor is used, it can be used if the disadvantage of increasing the number of ion implantation steps for controlling the threshold is tolerated. It should be noted that all the MOSFETs that are not described as being in the depletion mode in the above description are in the enhancement mode.

As described above, the SOI having two circuit blocks
Although the semiconductor device has been described as an example, a plurality of circuit blocks can be provided with bias circuits so that they can be controlled independently. Active for each circuit block
It can be applied when the mode and the standby mode are different. Further, since it is preferable to keep the bias condition constant like some interrupt processing circuits of a microcomputer, the bias condition may be changed only for a specific circuit block in the SOI semiconductor device. Furthermore,
The bias condition may be determined on a transistor-by-transistor basis, for example, by changing the bias condition only on a transistor having large power consumption, instead of on a circuit block-by-circuit basis. Also in the bias circuit of FIG.
The body bias of 2,203,204,205 is fixed, and that of the transistors 210,212,213,214 is different between the standby state and the active state. It will be apparent from the above description that such a thing can be freely performed in the SOI semiconductor device.

Furthermore, not only SIMOX technology but also SOI
It will be apparent to those skilled in the art that substrates in general can be utilized.

[0032]

As described above, according to the present invention, the substrate bias of the MOSFET of the semiconductor device formed on the SOI substrate is changed as necessary between active and standby, so that power consumption can be reduced. However, compared to the well type, the parasitic capacitance due to element isolation is 1
Since it can be reduced to about / 20, there is an effect that the power consumption of the semiconductor device can be surely reduced.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a first embodiment of the present invention.

FIG. 2 is a plan view showing a device structure of a first circuit block in the first embodiment by taking a CMOS inverter as an example.

3 is a cross-sectional view taken along the line AA of FIG. 2 (FIG. 3A), BB
3 is a sectional view taken along line C-C (FIG. 3B).
(B)).

FIG. 4 shows a first bias circuit according to the first embodiment.
4A and 4B are signal waveform diagrams for explaining the operation of the circuit of FIG. 4A and FIG. 4B.

FIG. 5 is a circuit diagram showing a second example of a bias circuit.

FIG. 6 is a schematic sectional view showing a conventional example.

[Explanation of symbols]

11 N-Channel MOSFET of First Circuit Block 12 P-Channel MOSFET of First Circuit Block 13 N-Channel MOSFET 209 of Second Circuit Block 210 P-Channel MOSFET 210 N-Channel MOSFET 211 N-Channel MOSFET 212 P-Channel MOSFET 213 N-Channel MOSFET 213A P-channel MOSFET (depletion mode) 214 P-channel MOSFET 214A N-channel MOSFET 301 N-type silicon substrate 302a, 302b First P-type well 304a, 304b Second P-type well 305 N-type diffusion layer 306a, 306b N-type well 307 P-type diffusion layer 308 Gate oxide film 309 Polysilicon gate electrode 310 Bias circuit for first circuit block 311 Second Bias circuit for path block 14 P-channel MOSFET 101 of second circuit block 101 Silicon substrate 102 Buried silicon oxide film 103 Silicon oxide film 104a, 104b P-type silicon substrate 104ac N-type diffusion layer 105 N-type diffusion layer 106a, 106b N Type silicon substrate 106ac P type diffusion layer 107 P type diffusion layer 108 Gate oxide film 109 Polysilicon gate electrode 110 Bias circuit for the first circuit block 111 Bias circuit 201 for the second circuit block 201 Pulse generation circuit 201-1 NOR gate 201-2, 201-3 Inverter circuit 202 P-channel MOSFET 203 P-channel MOSFET 204 N-channel MOSFET 205 N-channel MOSFET 206, 207 Capacitive element 208 Inverter circuit 40 Contact holes 402 contact holes 403 contact hole 404 lines ACT signal input terminal VA1, VB1 first output terminal VA2, VB2 second output terminal

[Procedure amendment]

[Submission date] December 8, 1995

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Figure 3

[Correction method] Change

[Correction contents]

3 is a cross-sectional view taken along the line AA of FIG. 2 (FIG. 3A), BB
3 is a sectional view taken along line C-C (FIG. 3B).
(C)).

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Fig. 4

[Correction method] Change

[Correction contents]

FIG. 4 shows a first bias circuit according to the first embodiment.
FIG. 4A is a circuit diagram showing an example of FIG. 4A and FIG. 4A is a signal waveform diagram for explaining the operation of the circuit of FIG.
(B)).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/786

Claims (4)

[Claims] 1. A plurality of P-channel MOSFETs formed on a silicon-on-insulator substrate, and a plurality of N-channel MOSFETs.
A channel MOSFET and a bias circuit are included. The bias circuit supplies a power supply voltage to the silicon base portion below the gate electrode of at least a part of the P-channel MOSFETs of the plurality of P-channel MOSFETs at the active time and at the standby time. A voltage higher than the power supply voltage is supplied and the plurality of N-channel MOSFEs are provided.
A semiconductor device, wherein a ground potential is supplied to the silicon base portion below the gate electrode of at least a part of the N-channel MOSFET of T during active and a voltage lower than the ground potential during standby. 2. A plurality of functional circuit blocks including a plurality of P-channel MOSFETs and a plurality of N-channel MOSFETs formed on a silicon-on-insulator substrate, and at least one P in the functional circuit block.
A power supply voltage is supplied to the silicon base portion below the gate electrode of the channel MOSFET when active, a voltage higher than the power supply voltage is supplied during standby, and a silicon base portion below the gate electrode of the N-channel MOSFET is supplied when active. Supply ground potential,
A semiconductor device comprising: a bias circuit that supplies a voltage lower than a ground potential during standby. 3. A pulse generation circuit for generating a continuous pulse when a signal at an input terminal is at a predetermined level, a first P-channel MOSFET having one source / drain electrode and a gate electrode connected to a ground terminal, and the pulse generation. The output of the circuit and the other source of the first P-channel MOSFET
A first capacitive element inserted between the drain electrode and the first source / drain electrode; a first capacitive element inserted between the source / drain electrode and the first P-channel; A second P-channel MOSFET connected to the other source / drain of the MOSFET and the other source / drain electrode thereof connected to the first output terminal, and a second P-channel MOSFET having one source / drain electrode and the gate electrode connected to the power supply terminal. One N-channel MOSFET, a second capacitance element inserted between the output terminal of the pulse generation circuit and the other source / drain of the first N-channel MOSFET, and one source / drain electrode and gate electrode Is connected to the other source / drain electrode of the first N-channel MOSFET, and the other source / drain electrode is the second source / drain electrode.
Second N-channel MOSFET connected to the output terminal of the
A charge pump circuit, an inverter circuit having an input terminal connected to the input terminal, a third electrode having a source electrode and a base electrode connected to the power supply terminal, and a gate electrode connected to an output terminal of the inverter circuit. Channel MOSFE
T and drain electrodes are the third P-channel MOSFET
A third N-channel MOSFE having a gate electrode connected to the output terminal of the inverter circuit and a source electrode and a substrate electrode connected to the first output terminal
A fourth N-channel MOSFET in which the T and drain electrodes are connected to the ground terminal, a gate electrode is connected to the drain of the third P-channel MOSFET, and a source electrode and a body electrode are connected to the first output terminal. A pull-up circuit, a fifth N-channel MOSFET having a source electrode and a base electrode connected to the ground terminal and a gate electrode connected to the input terminal, and a drain electrode connected to a drain electrode of the fifth N-channel MOSFET. A fourth P-channel MOSF having a gate electrode connected to the input terminal and a source electrode and a substrate electrode connected to the second output terminal
ET and a fifth P-channel MOSFET having a drain electrode connected to the power supply terminal, a gate electrode connected to the drain of the fifth N-channel MOSFET, and a source electrode and a body electrode connected to the second output terminal 3. A semiconductor device according to claim 1, which is a bias circuit having a pull-down circuit. 4. A first P-channel MOSFET and a second P-channel MOSFET
4. The semiconductor device according to claim 3, wherein the body electrode of the P-channel MOSFET is connected to the power supply terminal, and the body electrodes of the first N-channel MOSFET and the second N-channel MOSFET are connected to the ground terminal.