JPH0936849A - Bit synchronization circuit/system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the high speed transmission of an optical burst signal to make resistance to duty fluctuation high and to be synchronized with a reception burst signal in a short period. SOLUTION: This circuit is provided with a data sampling part 1 for sampling an input signal and generating signals of n-systems and a selection output part 2 for selecting the signal synchronized with the reception burst input signal among the sampled n-system signals. There are also provided with a change point detection part 3 detecting the rising/trailing change points of the signal from the data sampling part 1, a holding part 4 holding a change point detection result, a clock judgement part 5 judging the signal which the selection output part 2 is to select, based on either output result in the change point detection part 3 or the holding part 4 or the both results, and a judgement result holding part 6 holding the output result of the clock judgement part 5 for prescribed timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst transmission compatible bit synchronization circuit and a bit synchronization system for reproducing a signal in synchronization with the phase of a burst signal, and more particularly to a point-to-multipoint optical transmission system. The present invention relates to a bit synchronization circuit and a bit synchronization method suitable for application when the point side receives a burst signal from the multipoint side.

[0002]

2. Description of the Related Art As a conventional technique relating to a bit synchronization system for burst transmission signals, a point-to-multipoint system is constructed by connecting one communication device and a plurality of communication devices via an optical distribution device (star coupler). A bit synchronization method in an optical transmission system is known.

FIG. 9 is a block diagram showing a configuration example of such a conventional point-to-multipoint optical transmission system, and FIG. 10 shows a case where one communication device receives information cells from a plurality of communication devices. FIG. 11 is a diagram illustrating a situation, and a bit synchronization method according to a conventional technique will be described below with reference to FIGS. 9 and 10. In FIG. 9, 100,
Reference numerals 101-1 and 101-2 are communication devices, and 102 is a star coupler.

The illustrated optical transmission system includes one communication device 1.
00 and a plurality of communication devices 101-1 to 101-2 are connected via a star coupler 102 to form a point-to-multipoint optical transmission system. In the optical transmission system configured as described above, the communication device 101
In the case of transmitting an information cell to one of the communication devices 100-1 to 101-2, the communication device 100 and each communication device 101-
Each communication device 101 due to the difference in distance from 1 to 101-2.
Information cells transmitted from -1 to 101-2 to the communication device 100 have different optical levels and phase differences from the device internal system clock of the communication device 100, respectively.
It is transmitted in a burst and arrives at the communication device 100.

FIG. 10 shows an optical level of a burst signal when the communication device 100 as described above receives information cells from the communication devices 101-1 to 101-2. As can be seen from this figure, the optical levels of the burst signals of the information cells arriving at the communication device 100 from the communication devices 101-1 to 101-2 greatly differ from each other. Although not shown, these burst signals are
The phase difference from the device internal system clock of the communication device 100 is different.

The communication device 100 performs bit synchronization after converting the arrived burst signal into an electric signal by an optical / electrical conversion device. For bit synchronization in this communication device 100, a bit synchronization byte consisting of an alternating signal of 1/0 is provided near the beginning of the burst signal. But,
Considering transmission efficiency, only a limited number of bytes can be provided for the bit synchronization byte, and therefore the communication device 100 needs to perform bit synchronization within a section of several bytes of the bit synchronization byte.

As a conventional technique relating to the bit synchronization circuit for the burst transmission signal as described above, for example, "P
A technique described in "Burst Signal Corresponding Bit Synchronous Circuit in DS Optical Subscriber System" (Shingaku Zendai (Autumn) B-830, 1993) is known.

[0008] This conventional technique multi-phases the received burst signal, and performs bit synchronization by a DPLL circuit that retimes at a phase position shifted by a half phase from the change point of the received burst signal. In this prior art, a transmission rate of about 60 Mbps is assumed.

[0009]

In the system shown in FIG. 9 described above, high-speed transmission (155.52 Mb)
When performing the ps), the duty ratio variation of the input data becomes significant due to the delay of the followability of the automatic threshold control during the optical / electrical conversion of the burst signal received by the communication device 100.

FIG. 11 is a diagram showing the relationship between the time change of the threshold value for explaining this and the identified signal.

In FIG. 11, FIG. 11A shows the received optical signal, FIG. 11B shows the threshold signal for identifying the optical signal, and FIG. 11C shows the signal identified by the threshold. From this figure, it can be seen that the duty ratio of the received signal changes when the time change of the threshold value is significant.

Generally, when high-speed transmission is attempted, the ideal position of retiming for synchronization is further limited due to the influence of jitter, electrical distortion, and the like. Therefore, when the above-described synchronization method using the PLL circuit is applied to the system shown in FIG. 9, a phase deviated by a fixed phase from the change point of the received data is set as an ideal position for retiming as in the prior art. The method adopted has the problem that it has low resistance to duty fluctuations as described above.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a bit synchronization circuit and a bit synchronization system having high resistance to duty fluctuation.

[0014]

According to the present invention, the above object is to provide a data sampling section for sampling a received burst input signal into an n-series (where n is an integer of 2 or more) signal by a bit synchronizing circuit. And a selection output unit that selects and outputs a signal synchronized with the received burst input signal from the n-series signals sampled by the data sampling unit,
Further, n sampled by the data sampling unit
A change point detection unit that detects rising and falling change points of each of the series of signals, a holding unit that holds the detection result detected by the change point detection unit for a certain timing, the change point detection unit and the holding unit A clock determination unit that determines a signal to be selected by the selection output unit based on either or both of the output results from the unit, and a determination result holding unit that holds the output result of the clock determination unit for a certain timing. It is achieved by comprising.

The data sampling section includes a sampling means for generating a multi-phase clock composed of a plurality of n series having mutually different phases, sampling the received burst input signal using the multi-phase clock, and outputting it as an n series signal. You can

The change point detection unit detects the rising and falling change points of the received burst signal, and determines the phase position of the change point and the number of change points at the same time period as the received burst signal. Can be included.

The holding unit may include holding processing means for holding the change point detection result of the change point detection unit for one cycle of the same time cycle as the data cycle of the received burst signal.

The clock determination unit uses, as the determination logic, the phase position of the change point of the received burst signal transmitted from either or both of the change point detection unit and the holding unit.
It is possible to include a determination processing unit that determines the reception burst signal sampled at the intermediate phase position of the two transition points of the rising and falling of the reception burst signal as the signal to be selected by the selection output unit.

As the decision logic in the clock decision unit,
Further, the phase position and the number of transition points of the rising or falling transition point of the reception burst signal within the same time period as the data cycle of the reception burst signal output from the transition point detection unit, and the data of the reception burst signal in the holding unit. Judgment processing means for judging the signal to be selected by the selection output unit based on either or both of the phase position and the number of change points from the change point detection unit held for one cycle of the same time period as the cycle. Can be included. The specific logic of this determination processing means is as follows.

The number of rising or falling transition points of the received burst signal within the same time period as the data cycle of the received burst signal, which is output from the transition point detection unit, is 1 When the number of change points from the change point detection unit held for one cycle of the same time period is 0, the phase position shifted by a fixed timing from the phase position of the change point output from the change point detection unit. The reception burst signal sampled in 1 is determined to be a signal to be selected by the selection output unit.

The number of rising or falling transition points of the received burst signal within the same time period as the data cycle of the received burst signal output from the transition point detection unit is 1, and the holding unit stores the data cycle of the received burst signal. When the number of change points from the change point detection unit held for one cycle of the same time period is 1, the phase position of the change point output from the change point detection unit and the change output from the holding unit The reception burst signal sampled at the intermediate phase position with respect to the phase position of the point is determined as the signal to be selected by the selection output unit.

The number of rising or falling transition points of the received burst signal within the same time period as the data cycle of the received burst signal output from the transition point detection unit is 1, and the data cycle of the received burst signal is stored in the holding unit. When the number of change points from the change point detection unit held for one cycle of the same time period is 2, the phase position of the change point output from the change point detection unit and 2 output from the holding unit. The received burst signal sampled at the intermediate phase position with respect to the trailing edge phase position of the two change points is determined as the signal to be selected by the selection output unit.

When the number of rising or falling transition points of the reception burst signal within the same time period as the data cycle of the reception burst signal output from the transition point detection unit is 2, it is output from the transition point detection unit. The reception burst signal sampled at the intermediate phase position between the phase positions of the two change points is determined as the signal to be selected by the selection output unit.

If the rising or falling transition point of the received burst signal within the same time period as the data cycle of the received burst signal is not detected, the determination result holding unit determines the result of the determination made by the clock determination unit up to now. Can be provided only for a certain timing.

Further, the information from the judgment result holding unit can be averaged within a certain time and used as the selection information of the selection output unit.

[0026]

According to the present invention, the received burst signal is sampled to detect the rising and falling transition points, the result is delayed, and the change point information from the past is also combined to determine the signal synchronized with the reception burst signal. Therefore, it is possible to determine the synchronization of the received burst signal considering the duty variation.

Further, as a means for sampling the received burst signal, a multi-phase clock composed of a plurality of n series having mutually different phases is generated, the received burst input signal is sampled using this multi-phase clock, and these are input to the n series. Since it is output as a signal of, it is possible to adapt to the operation at high speed.

Further, according to the present invention, not only the position of the change point but also the number of change points in one cycle is detected as the change point detection information, and the information is delayed by one cycle to obtain the delayed information and The information before the delay, that is, the position and the number of the change points for the past two cycles can be used as the information for determining the signal synchronized with the received burst signal.

As the logic for determining the signal synchronized with the received burst signal, the point where a fixed value is deviated by a fixed value from the rising change point of the signal is not used as the retiming position as in the prior art, but the rising change is performed. Since the retiming position is set at the midpoint between the point and the falling change point, the retiming can always be performed at the ideal retiming position even when the duty variation as described above occurs. .

Further, as the logic for judging the signal synchronized with the received burst signal in consideration of the number of change points, it is possible to use the logic classified according to the number of change points in the past two cycles.

FIG. 8 is a diagram showing an example of the phase relationship between the internal clock of the device and the received burst signal for explaining the logic for determining the signal synchronized with the received burst signal. A method of determining the signal synchronized with the received burst signal by the logic classified according to the number of change points in two cycles will be described. In the following, a set of the number of change points in the past two cycles will be described with the symbol (current change point, past change point number). In FIG. 8, FIG. 8 (a) is an internal clock of a device equipped with the bit synchronization circuit according to the present invention, and FIGS. 8 (b) to 8 (f) are examples of received burst signals.

In the case of (1, 0), for example, as shown in FIG. 8B, this corresponds to the case where the beginning of the bit synchronization signal is detected in the current cycle, which is a fixed value shift from the current change point. The point is the retiming position.

In the case of (1, 1), for example, as shown in FIG. 8C, the beginning of the bit synchronization signal is detected in the past cycle, and the end of the bit synchronization signal is detected in the current cycle. This corresponds to the case where the phase difference between the received burst signal and the internal clock of the apparatus is close to 180 °, and the midpoint between the two change points within two cycles is calculated and set as the retiming position. This makes it possible to cope with the duty fluctuation of the received burst signal.

In the case of (1 and 2), for example, as shown in FIG. 8D, when the phase difference between the received burst signal and the internal clock of the apparatus is close to 0 ° and the duty changes. Correspondingly, the midpoint between the trailing edge of the previous cycle and the change point in the current cycle is calculated and used as the retiming position. This makes it possible to cope with the duty fluctuation of the received burst signal.

When the number of change points in the current cycle is 2, for example, as shown in FIG. 8 (e), the phase difference between the received burst signal and the internal clock of the apparatus is close to 0 ° and the duty changes. It corresponds to the case where two change points are detected after the pattern of FIG. 8F described later, or the case where the end of the bit synchronization signal is detected, and the intermediate point between both change points is calculated. Set to the retiming position. This makes it possible to cope with the duty fluctuation of the received burst signal.

When the number of change points in the current cycle is 0, for example, as shown in FIG. 8 (f), the phase difference between the received burst signal and the internal clock of the apparatus is close to 0 ° and the duty changes, This corresponds to the case where the change point is not detected after the pattern of FIG. 8E described above or the end of the bit synchronization signal is detected, and the judgment result so far is held and Set to the retiming position. Also in this case, it is possible to deal with the case of duty fluctuation. It is also possible to deal with the case where the change point disappears due to a bit identification error or the like.

When the information from the determination result holding unit is averaged within a certain time and used as the selection information of the selection output unit, the detected change point position suddenly becomes an abnormal value due to a bit identification error or the like. The effect can be alleviated.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a bit synchronization circuit and a bit synchronization system according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a bit synchronizing circuit according to the first embodiment of the present invention, FIG. 2 is a time chart explaining the operation of the bit synchronizing circuit shown in FIG. 1, and FIG. 3 is a change in FIG. Block diagram showing a configuration example of a point detection unit,
4 is a block diagram showing a configuration example of the data sampling section in FIG. 1, and FIG. 5 is a block diagram showing a configuration example of the multiphase clock generation section in FIG. 1 and 3 to 5, 1 is a data sampling unit, 2 is a selection output unit, 3 is a change point detection unit, 4 is a holding unit, 5 is a clock determination unit, 6 is a determination result holding unit, and 20 is a latch. , 21 is a change point pulse detection section, 22 is a change point encoder section, 30 is a polyphase sample section, 31 is a polyphase clock generation section, 32 is a shift register, 33-1 to 33-7 are delay sections, and 34 is It is the frequency division.

The bit synchronizing circuit shown in FIG. 1 samples the received burst input signal into an n-series (where n is an integer of 2 or more) signal, and the data sampler 1 samples the data. A selection output unit 2 that selects and outputs a signal synchronized with the received burst input signal from the n-series signals.

The feature of the illustrated embodiment of the present invention resides in the means for judging the signal synchronized with the received burst input signal, and this judging means is of the n-series sampled by the data sampling section 1. A change point detection unit 3 that detects respective rising and falling change points of a signal, a holding unit 4 that holds the detection result detected by the change point detection unit 3 at a certain timing, a change point detection unit 3, and a holding unit Either of the output results from 4, or
A clock determination unit 5 that determines a signal to be selected by the selection output unit 2 based on both of them, and a determination result holding unit 6 that holds the output result of the clock determination unit 5 at a certain timing are configured.

In the following description, the phase number n of the multiphase clock, which is an n-series signal for sampling, is n = 8.
Shall be In addition, for each of the eight series of signals sampled by the data sampling unit 1, if necessary,
A description will be given by sequentially assigning numbers according to the sampled phase positions. Further, a clock having the same frequency as the frequency of the input data, such as the system clock of the device equipped with the bit synchronization circuit according to the embodiment of the present invention, will be referred to as a master clock.

The data sampling section 1 may be constructed as shown in FIG. 4 (a) or 4 (b). Figure 4 (a)
The configuration example shown in (1) comprises a multi-phase sampling section 30 and a multi-phase clock generation section 31, and samples a received burst signal with a multi-phase clock generated by the multi-phase clock generation section 31.

Assuming that the number of phases n of the multi-phase clock is n = 8, the multi-phase clock generator 31 will generate the multi-phase clock as shown in FIG.
Reference clock with the same frequency as the received signal (n-1)
= 1 by the seven delay units 33-1 to 33-7
It may be configured to delay from the timing of / 8 cycle to the timing of (1/8 cycle) × 7 to generate a multi-phase clock having a phase difference of 1/8 cycle. Further, as shown in FIG. 5B, the multiphase clock generator 31 divides the high-speed clock having a frequency of n = 8 times the received signal by 8 by the frequency divider 34, or The part 34 divides into four by using the rising change point of the high-speed clock having a frequency of n / 2 = 4 times as a trigger, and by dividing the falling change point into four, the phase difference of 1/8 cycle is obtained. Can be configured to generate an 8-phase multi-phase clock having

The configuration example of the data sampler 1 of the received burst signal shown in FIG. 4B uses a shift register 32. The shift register 32 causes the received burst signal to be n = 8 times the received signal or n / 2. = Sampling with a high-speed clock having a frequency of 4 times and outputting as an n-series signal.

As shown in FIG. 3, the changing point detecting section 3 comprises a latch section 20, a changing point pulse sending section 21, and a changing point encoder section 22. The latch unit 20 of the change point detection unit 3 configured as described above latches the eight series of signals sampled by the data sampling unit 1 by the master clock. The change-point pulse transmission unit 21 outputs H when the latched 8-phase signal is different from the state of the signal latched by the previous clock, that is, the signal of the previous number, and the same as the state of the signal of the previous number. L is output to generate an 8-phase pulse train. The number of the signal in the H state in the pulse train thus generated is the number corresponding to the phase position where the rising or falling change point of the received burst signal exists.

The changing point encoder section 22 detects the number of the pulse in the H state in the 8-phase pulse train obtained from the changing point pulse sending section 21 every one cycle of the master clock, and further, The lowest number among them (hereinafter,
Number A) and the oldest number (hereinafter number B)
Is called) and output. The number output by this represents the phase position of the change point of the rising or falling edge of the received burst signal within one cycle of the master clock in units of the phase difference between the multi-phase clock phases. Equivalent to.

The holding unit 4 holds the above-mentioned output from the change point detecting unit 3 for a period of one cycle of the master clock. As a result, the result output from the holding unit 4 is the change point number output from the change point detection unit 3 one cycle before the master clock. However, the holding unit 4 includes the change point detection unit 3
Holds the time when the change point is not detected during one cycle of the master clock (the number of the position held so far + 1 the length of 8 cycles).

The clock determination section 5 uses either or both of the change point number output from the change point detection section 3 and the change point number one cycle before the master clock output from the holding section 4. On the basis of the information, the number which is in the middle of the two change points is calculated. Specifically, when the number A and the number B do not match, the clock determination unit 5
A number C, which is an intermediate point between the number A and the number B of the change points output from the change point detection unit 3, is calculated.

Further, when the number A and the number B match and the change point is detected one cycle before the master clock, the clock determination section 5 outputs the number B and the holding section 4. The number C of the intermediate point between the number B (hereinafter, referred to as B ′) of the change point of one cycle before the master clock is calculated, and the number A and the number B match, and the number 1 of the master clock is calculated. When the change point is not detected before the cycle, as described above, the holding unit 4 outputs the master clock 2
Since the number B (hereinafter, referred to as B ″) + 8 of the change point before the cycle is supplied, an intermediate point between the (number B ″ +8) and the number B is calculated and is output as the number C.

The judgment result holding unit 6 holds the number C which has been judged so far when the change point output from the change point detection unit 3 is not detected.

The selection output unit 2 selects and outputs a signal corresponding to the same number as the number C from the signals of 8 series sampled by the data sampling unit 1.

The time chart shown in FIG. 2 shows the operation of the first embodiment of the present invention described above.

In FIG. 2, (a) is a master clock,
(B) is a received burst input signal, (c0) to (c7) are multiphase clocks, (d0) to (d7) are input signals sampled by the data sampling unit 1, (e1), (e)
2) is the number A and the number B in the change point detector 3,
(F) shows the number C selected by the selection output unit 2, respectively.

In the first embodiment of the present invention, the intermediate point between the number A and the number B is selected in the cycle 1 of the master clock in FIG. 2, and the result in the cycle 1 is held in the cycle 2. Then
In cycle 3, the midpoint between the number B and the number B in cycle 1 (the number B ″) is selected, and in cycle 4, the midpoint between the number B and the number B in the cycle 3 (the number B ′) is selected.

Next, a bit synchronizing circuit according to the second embodiment of the present invention will be described. In the second embodiment of the present invention, the clock decision is made from the phase position of the change point of the input data and the number of change points, and the block shown in FIG. 1 similar to the first embodiment of the present invention. The change point detection unit 3, the holding unit 4, and the clock determination unit 5 have different configurations.

Change point detection unit 3 of the second embodiment of the present invention
Detects the above-mentioned number A and number B corresponding to the phase position of the change point, similarly to the change point detection unit 3 of the first embodiment,
Further, the number of change points in one cycle of the master clock is detected and output.

Further, like the holding unit 4 of the first embodiment, the holding unit 4 holds the output from the change point detection unit 3 for a period of one cycle of the master clock, but the change point detection unit When the change point is not detected in 3, the special operation as in the case of the first embodiment described above is not performed.

The clock determination unit 5 includes the number A, the number B, the number of change points supplied from the change point detection unit 3, and the number one cycle before the master clock supplied from the holding unit 4. Either A, the number B, the number of change points, or both, is used to calculate a number in the middle of the two change points.

FIG. 6 is a diagram for explaining the decision logic in the clock decision unit 5, and the decision logic in the clock decision unit 5 will be specifically described below with reference to this figure.

When the number of change points in one cycle of the master clock is 0, the number A one cycle before the held master clock is output [FIG. 6 (a)]. When the number of change points in one cycle of the master clock is 1 and the number of change points in the previous cycle of the master clock is 0, the number A (or the number B) is half the cycle of the master clock n / 2 = 4 is added and the determination number C is output [FIG. 6 (b)]. If the number of change points within one cycle of the master clock is 1 and the number of change points before one cycle of the master clock is 1 and 2, then number A
(Or number B) and the number B (number B ') one cycle before the master clock is calculated, and this is output as the determination number C [Fig. 6 (c), Fig. 6 (d)]. When the number of change points in one cycle of the master clock is 2, the number A plus 3 is output as the determination number C [FIG.
(E)].

Then, the determination result holding unit 6 has made the determination so far when the change point output from the change point detection unit 3 is not detected, as in the case of the first embodiment of the present invention described above. The number C is held. In addition, the selection output unit 2
Is the same as in the case of the first embodiment of the present invention, from among the 8 series of signals sampled by the data sampling unit 1,
A signal corresponding to the same number as the number C is selected.

FIG. 7 is a block diagram showing the structure of a bit synchronizing circuit according to the third embodiment of the present invention. In FIG. 7, reference numeral 7 is an integrator, and other symbols are the same as those in FIG.

A third embodiment of the present invention shown in FIG. 7 is shown in FIG.
1 is different from the circuit shown in FIG. 1 in that the output of the determination result holding unit 6 is given to the selection output unit 6 via the integrating unit 7 in the bit synchronization circuit described in 1. Is configured.

In the third embodiment of the present invention, the integration section 7 performs a moving average of the determination result supplied from the determination result holding section 6 for two cycles of the master clock, and the selection output section 2
Is output to. By this averaging, even when the detected change point position suddenly becomes an abnormal value due to a bit identification error or the like, the abnormality can be mitigated.

The averaging section is not limited to two cycles of the master clock, but may be three cycles or more.

[0067]

As described above, according to the present invention, since the retiming phase determination is performed by using both the rising and falling points of the received burst signal, the high speed transmission is achieved. In the above, it becomes possible to perform synchronization in a short section with respect to the received burst signal in which the duty fluctuation has occurred.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a bit synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart explaining the operation of the bit synchronization circuit shown in FIG.

FIG. 3 is a block diagram showing a configuration example of a change point detection unit in FIG.

FIG. 4 is a block diagram showing a configuration example of a data sampling unit in FIG.

5 is a block diagram showing a configuration example of a multi-phase clock generation unit in FIG.

FIG. 6 is a diagram for explaining the decision logic of the clock decision unit in the second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a bit synchronization circuit according to a third embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of a phase relationship between a device internal clock and a received burst signal for explaining a logic for determining a signal synchronized with the received burst signal.

FIG. 9 is a block diagram showing a configuration example of a point-to-multipoint optical transmission system according to a conventional technique.

FIG. 10 is a diagram illustrating a situation in which one communication device receives information cells from a plurality of communication devices.

FIG. 11 is a diagram illustrating a relationship between a threshold time change and an identified signal.

[Explanation of symbols]

 1 Data Sampling Section 2 Selection Output Section 3 Change Point Detection Section 4 Holding Section 5 Clock Judgment Section 6 Judgment Result Holding Section 7 Integrating Section 20 Latch Section 21 Change Point Pulse Detection Section 22 Change Point Encoder Section 30 Multiphase Sample Section 31 Multiphase Clock generator 32 Shift register 33-1 to 33-7 Delay unit 34 Frequency divider 100, 101-1, 101-2 Communication device 102 Star coupler

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadashi Akiwa 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Inventor Yasuyuki Okumura 1-1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo No. Japan Telegraph and Telephone Corporation

Claims (24)

[Claims] 1. A data sample section for sampling a received burst input signal and outputting it as an n-series (where n is an integer of 2 or more) signal, and an n-series signal sampled by the data sample section. In a bit synchronization circuit having a selection output section for selecting and outputting a signal synchronized with a received burst input signal, a change point of rising edge and a change of falling edge of each of the n-series signals sampled by the data sampling section. A change point detection unit that detects a point, a holding unit that holds the detection result detected by the change point detection unit for a certain timing, and either one or both of the change point detection unit and the output result from the holding unit A clock determination unit that determines a signal to be selected by the selection output unit based on A bit synchronization circuit comprising: a determination result holding unit that holds only timing. 2. A sampling for generating a multi-phase clock composed of a plurality of n-sequences having mutually different phases, sampling the received burst input signal using this multi-phase clock, and outputting the signal as an n-series signal. 2. The bit synchronization circuit according to claim 1, further comprising means. 3. The change point detection unit detects a rising change point and a falling change point of the sampled reception burst signal, and detects a phase position of the change point at each time cycle that is the same as the data cycle of the reception burst signal. 3. The bit synchronization circuit according to claim 1, further comprising a determination processing unit that determines the number of change points. 4. The holding unit is configured to include a holding processing unit that holds the change point detection result from the change point detection unit for one cycle of the same time period as the data cycle of the reception burst signal. The bit synchronization circuit according to claim 1, 2 or 3. 5. The clock determination unit determines whether the received burst signal rises or falls based on the phase position of the change point of the received burst signal transmitted from either or both of the change point detection unit and the holding unit. 5. The reception burst signal sampled at the phase position closest to the intermediate phase of the change point is provided with determination processing means for determining the signal to be selected by the selection output unit. The bit synchronization circuit according to any one of the above. 6. The phase determination and change of the rising change point or the falling change point of the received burst signal within the same time period as the data cycle of the received burst signal output from the change point detection section. Based on either one or both of the number of points and the phase position and number of change points from the change point detection section held by the holding section for one cycle of the same time period as the data cycle of the received burst signal. 5. The bit synchronization circuit according to claim 1, wherein the selection output unit includes a determination processing unit that determines a signal to be selected. 7. The number of rising change points or falling change points of the received burst signal within the same time period as the data cycle of the received burst signal output from the change point detection section is 1 in the clock determination section. If the number of change points from the change point detector held in the hold unit for one cycle of the same time period as the data cycle of the received burst signal is 0, the change point output from the change point detector is It is characterized by comprising a judgment processing means for judging a reception burst signal sampled at a phase position closest to a phase shifted by a fixed timing with respect to the phase position as a signal to be selected by the selection output unit. The bit synchronization circuit according to claim 1. 8. The number of rising change points or falling change points of the received burst signal within the same time period as the data cycle of the received burst signal output from the change point detection section is 1 in the clock determination section. If the number of change points from the change point detection unit held in the holding unit for one cycle of the same time period as the data cycle of the received burst signal is 1, the change point output from the change point detection unit is A received burst signal sampled at an intermediate phase position between the phase position and the phase position of the change point output from the holding unit,
5. The bit synchronization circuit according to claim 1, further comprising a determination processing unit that determines that the selection output unit is a signal to be selected. 9. The number of rising change points or falling change points of the received burst signal within the same time period as the data cycle of the received burst signal output from the change point detection section is 1 in the clock determination section. When the number of change points from the change point detection unit held by the holding unit for one cycle of the same time period as the data cycle of the received burst signal is 2, the change point output from the change point detection unit is Judgment processing for judging the received burst signal sampled at an intermediate phase position between the phase position and the phase position of the trailing edge of the two change points output from the holding unit as a signal to be selected by the selection output unit. 5. The bit synchronization circuit according to claim 1, further comprising means. 10. The number of rising change points or falling change points of the received burst signal within the same time period as the data cycle of the received burst signal output from the change point detection section is two. In this case, the reception burst signal sampled at the intermediate phase position between the phase positions of the two change points output from the change point detection unit is provided with a determination processing unit that determines the signal to be selected by the selection output unit. The bit synchronization circuit according to any one of claims 1 to 4, wherein: 11. The determination result holding unit, when the change point detection unit does not detect a rising change point or a falling change point of the received burst signal within the same time period as the data cycle of the received burst signal, 11. The bit synchronization circuit according to claim 1, further comprising holding means for holding the determination result determined by the clock determination unit up to a certain timing. 12. The apparatus according to claim 1, further comprising an averaging means for averaging the information from the determination result holding unit within a certain time period to obtain the selection information of the selection output unit.
1. The bit synchronization circuit according to any one of 1. 13. A reception burst input signal is sampled into an n-series signal (where n is an integer of 2 or more), and a signal synchronized with the reception burst input signal is selected from the sampled n-series signals. In the bit synchronization method of outputting by outputting the rising change point and the falling change point of the sampled received burst signal, delaying the change point detection result by a certain timing, the sampled received burst signal Synchronized with the received burst input signal from the sampled signals based on either or both of the detection result of the rising transition point and the falling transition point and the detection result of the transition point delayed by the certain timing. A bit characterized by judging a signal and holding the judgment result only at a certain timing Synchronous method. 14. A process for generating a multi-phase clock composed of a plurality of n-sequences having mutually different phases, sampling the received burst input signal using this multi-phase clock, and outputting the sampled signal as an n-series signal. The bit synchronization method according to claim 13. 15. A process of detecting rising and falling transition points of a multi-phase-sampled reception burst signal, and determining a phase position of the transition point and the number of transition points for each time period that is the same as the data cycle of the reception burst signal. 15. The bit synchronization method according to claim 13 or 14, characterized by including. 16. A detection result obtained by detecting rising and falling transition points of the sampled reception burst signal is set to 1 at the same time period as the data cycle of the reception burst signal.
16. The bit synchronization method according to claim 13, 14 or 15, further comprising a process of holding only a period. 17. A reception burst signal sampled at an intermediate phase position between two rising and falling transition points of the reception burst signal is synchronized with the reception burst input signal based on the phase position of the transition point of the reception burst signal. 17. The bit synchronization method according to claim 13, further comprising a determination process for determining that the signal is a registered signal. 18. The phase position and the number of transition points of the rising or falling transition point of the received burst signal and the number of transition points within the same time period as the data cycle of the received burst signal, and one cycle of the same time period as the data cycle of the received burst signal. A process of determining a signal synchronized with the received burst input signal from among the sampled signals based on one or both of the phase position and the number of change points in the time period that is past by minutes. The bit synchronization system according to any one of claims 13 to 16, which is characterized by the above. 19. The number of rising or falling transition points of the received burst signal in the same time period as the data period of the received burst signal is 1, and the number of past one period of the same time period as the data period of the received burst signal is increased. When the number of change points in the time period is 0, the received burst signal sampled at a phase position shifted by a certain fixed timing with respect to the phase position of the rising or falling change point of the received burst signal in the one cycle is used. 17. The bit synchronization system according to claim 13, further comprising a process of determining that the signal is synchronized with the received burst input signal. 20. The number of rising or falling transition points of the reception burst signal within the same time period as the data cycle of the reception burst signal is 1, and the number of past one cycle of the same time period as the data cycle of the reception burst signal is exceeded. When the number of change points in the time period is 1, sampling is performed at an intermediate phase position between the phase position of the rising or falling change point of the received burst signal in the one cycle and the phase position of the change point one cycle before. 17. The bit synchronization system according to claim 13, further comprising a process of determining the received burst signal as a signal synchronized with the received burst input signal. 21. The number of transition points of rising or falling of the received burst signal within the same time period as the data cycle of the received burst signal is 1, and the number of past one cycle of the same time cycle as the data cycle of the received burst signal. When the number of change points in the time period is 2, the phase position of the rising or falling change point of the received burst signal in the one cycle and the phase position of the trailing edge of the two change points one cycle before The received burst signal sampled at the intermediate phase position between
19. The bit synchronization system according to claim 13, further comprising a process of determining that the signal is synchronized with the received burst input signal. 22. When the number of rising or falling transition points of the received burst signal within the same time period as the data cycle of the received burst signal is 2, the intermediate phase position of the phase positions of the two transition points within the one cycle. 19. The bit synchronization method according to claim 13, further comprising a process of determining the received burst signal sampled in step 1 as a signal synchronized with the received burst input signal. 23. When a rising or falling transition point of the reception burst signal within the same time period as the data cycle of the reception burst signal is not detected, a signal synchronized with the reception burst input signal determined up to now is provided at a certain timing. 13 to 2 are only held.
2. The bit synchronization method according to any one of 2. 24. An averaging process for averaging information for selecting a signal synchronized with the received burst signal from among the sampled n series of received burst signals within a certain time. Item 24. The bit synchronization method according to any one of Items 13 to 23.