JPH09322158A - Image signal transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable phase correction without providing any special phase difference detection circuit by resetting a read address corresponding to the reference of a signal of which the phase is most advanced. SOLUTION: The transmitted signals of two systems are respectively inputted to serial/parallel(S/P) converting circuits 111 and 112, the image signal of 15 bits, the reference signal of 1 bit and a CLK signal are outputted as their outputs and these signals are equal with the input signals of P/S 104 and 105 at a transmission parts 1000. These outputs of S/P 111 and 112 having phase difference are respectively inputted to the data inputs, write address resets and write clocks of memories A113 and B114. The reference signal of a phase advanced signal is defined as the read address reset signal of the memories A113 and B114, the CLK of a phase advanced signal is defined as the read CLK of the memories A113 and B114 and DATA are read out so that data having no phase difference can be outputted from the memories A113 and B114.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it possible to transmit an image signal to a distant place by compensating for a phase difference shift when transmitting one image signal by dividing it into a plurality of transmission lines. The present invention relates to an image signal processing device.

[0002]

2. Description of the Related Art When a set of digital image signals nbit is divided into a plurality of pieces and transmitted, and when these are combined and reproduced at a receiving side, a difference in transmission time between two transmitted signals, a so-called phase difference. May occur, it is necessary to correct it and restore the original correct signal. For example, data A
(Xbit) and data B ((n-x) bit) are divided into two systems, each parallel digital signal is converted into a serial digital signal and transmitted separately, and each transmitted serial digital signal A conventional correction method in the case of converting the original parallel data A (xbit) and the data B ((n-x) bit) and synthesizing them to restore the original nbit signal will be described with reference to FIG. In FIG. 6, the output data A and the data B of the serial / parallel conversion circuit (S / P) 601 are signals that have been converted from two serial signals that have been transmitted into parallel signals, and the so-called difference in transmission time It includes the phase difference. A common phase reference signal is added to the data A and the data B of the transmitted signal. The phase difference amount detection circuit 602 detects the phase difference amount of the phase reference signal transmitted by the two systems, and based on the detection result, the phase advance signal is detected by the delay circuit 603 or 604. Delayed by a minute.

As described above, conventionally, a circuit for detecting the phase difference between a plurality of transmitted signals is provided, and the phase difference is corrected by delaying the signal whose phase is advanced based on the detection result. .

[0004]

However, in the above-mentioned prior art, there is a phase difference between the transmission paths of a plurality of systems, and when correcting the phase difference, the phase reference signal transmitted to each of the transmission paths to the receiving side. It is necessary to provide a phase difference detection circuit because the phase difference is detected and the signal with the advanced phase is delayed and corrected based on the detection result.

The present invention eliminates the need for providing the special phase difference detection circuit as described above when the system having the most advanced phase among the signals transmitted through the plural systems of transmission lines is known. Another object of the present invention is to provide an excellent image signal transmission device that enables phase difference correction.

Further, according to the present invention, the special phase difference amount detecting circuit as described above is provided even when the system of the signal with the most advanced phase among the signals transmitted through the plural systems of transmission lines is not known. An object of the present invention is to provide an excellent image signal transmission device capable of correcting a phase difference without using the image signal transmission device.

[0007]

In order to achieve the above object, the present invention divides an n-bit digital image signal output from a signal source into a plurality of parallel signals, each of which has a constant period of 1 bit. The signals added with the reference signal are converted into serial signals and transmitted from the transmission unit, and the reception unit synchronizes the same parallel signals and reference signals with the same parallel signals and reference signals immediately after division from the serial signals. After playing back multiple clock signals,
The plurality of transmitted and reproduced parallel signals are independently written into different memory circuits at respective timing reference signals to reset write addresses and write at respective clock timings, and have a phase difference at the time of transmission. There is no phase difference by resetting the read address with the reference signal of the signal with the most advanced phase among the multiple transmitted signals written in the memory as it is and by reading with the clock of the signal with the most advanced phase Since it is output as data, it is possible to correct the phase difference of the digital image signal transmitted through the plurality of transmission paths without providing a special phase difference detection circuit on the receiving side.

Further, according to the present invention, even when the signal with the most advanced phase among the plurality of transmitted digital image signals is not known, a simple phase discrimination circuit is provided to detect a special phase difference amount. It is possible to correct the phase difference between signals transmitted through two transmission paths without providing a circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, an n-bit digital image signal output from a signal source is divided into a plurality of parallel signals, and each signal is 1 bit.
A signal added with a reference signal of a constant period is converted into a serial signal and transmitted from the transmission unit, and the reception unit receives a plurality of parallel signals from the plurality of serial signals and the same plurality of reference signals immediately after the division and the parallel signal and After regenerating a plurality of clock signals synchronized with the reference signal, the transmitted and regenerated plurality of parallel signals are independently and separately written in different memory circuits with the respective timing reference signals to reset the write address and the respective clock signals. Writing is performed at the timing, and the read address is reset with the reference signal of the signal with the most advanced phase among the multiple transmitted signals written in the memory with the phase difference at the time of transmission, It is output as data with no phase difference by reading with the clock of the signal that is advancing. , Even without providing a special phase difference detecting circuit to the receiving side, it is possible to correct the phase difference between the digital image signals transmitted by a plurality of transmission paths.

According to a second aspect of the present invention, a source for generating a parallel digital image signal, a means for dividing the parallel digital image signal into a plurality of parallel signals, and a parallel signal obtained by dividing the plurality of parallel signals are common. A unit for adding a reference signal of a constant period, a unit for converting each of a plurality of parallel signals to which the reference signal is added into a serial signal and outputting as a plurality of serial signals, and a unit for transmitting each of the plurality of serial signals. Means, means for receiving a plurality of transmitted serial digital signals, and a plurality of parallel signals and reference signals immediately after the original division from each of the plurality of received serial digital signals and the parallel signals and the reference signals A means of recovering the synchronized clock and the units that occur during the transmission of multiple recovered parallel signals. A memory means having an address for the number of clocks equal to or longer than the longest time of which the difference is known in advance, a means for writing a plurality of reproduced parallel signals in the memory, and a write address of the plurality of memory means are respectively reproduced. A means for resetting with a reference signal, and writing of reproduced parallel signals to a plurality of memory means,
Means to perform in synchronization with each reproduced clock,
It is provided with a means for resetting the read addresses of the plurality of memory means with a common reset signal and a means for reading the respective parallel signals written in the plurality of memory means at the timing of a common clock. An image signal transmission device characterized by using, as a clock, a reference signal and a clock reproduced from the serial signal with the most advanced phase among a plurality of transmitted serial signals. Further, it has an effect of being able to absorb the phase difference between the image signals divided into a plurality of parts.

According to a third aspect of the present invention, a phase discriminating circuit for discriminating a signal having the most advanced phase among a plurality of reproduced parallel signals and a phase discriminating circuit based on an output of the phase discriminating circuit 3. The image transmission device according to claim 2, further comprising a plurality of selectors for supplying the reference signal and the clock of the advanced signal to the respective memory means, wherein the image is divided into a plurality of images and is transmitted by different transmission means. Even if the image signal with the most advanced phase of the signal is not determined in advance, the phase difference between the divided image signals can be absorbed.

(Embodiment 1) An embodiment of the present invention will be described below with reference to FIGS. 1 to 5. FIG. 1 shows the configuration of an image signal transmission apparatus according to the first embodiment of the present invention, which is an example of a case where transmission is performed by dividing into two systems.
The amount of phase difference that occurs when image signals are transmitted through separate transmission paths almost always depends on the transmission distance of the system, and in most systems, the maximum transmission distance is predetermined. Therefore, it is general that the maximum phase difference is also fixed. In this embodiment, the phase difference is less than 4 CLK.

In FIG. 1, 1000 is a transmitter, and 110
Reference numeral 0 is a receiver. In the transmitter 1000, the signal source 1
01 is a digital G signal 10 bits, B signal 10 bits, R
A total of 30 bits of 10 bits of signals and 1 bit of CLK are output.
The GBR total of 30 bits is separated by a separation circuit 102 into two systems of 15 bits each. The reference signal generation circuit 103 generates and outputs a reference signal having a constant period. This reference signal is, for example, a signal that becomes 1 CLK “High” every 4 CLK. Fifteen
The image signals divided for each bit are input to parallel / serial conversion circuits (P / S) 104 and 105, respectively. To the P / Ss 104 and 105, a reference signal 1 bit which is an output signal of the reference signal generation circuit 103 is also input. The P / Ss 104 and 105 convert the input 16-bit parallel signal into a 1-bit serial signal and output it.
The signals output from the P / Ss 104 and 105 are output to a transmission line by a transmission means (not shown).

There are various possible reasons why the signals of the two systems output from the transmission unit 1000 have a phase difference when received by the reception unit 1100. One of the reasons is the transmission unit. When two serial signals of 1000 outputs are converted into optical signals having different wavelengths, and the optical signals of the two kinds of wavelengths are wavelength-multiplexed and transmitted by one optical fiber, the wavelength difference may occur. It may be caused by a difference in transmission speed of the optical signal. In this case, since the optical wavelength is determined in advance, it is possible to know in advance which phase of the signals of the two systems leads.

The two transmitted signals are received by the receiving unit 1.
It is received by a receiving means (not shown) 100 and input to serial / parallel conversion circuits (S / P) 111 and 112, respectively. S / P111 and 112 are 15 each
It outputs a bit image signal, a 1-bit reference signal, and a CLK signal, respectively. The outputs of the S / Ps 111 and 112 are the same signals as the input signals of the P / Ss 103 and 104 of the transmitter 1000. At this time, the output signal of S / P111 and S / P1
The 12 output signals have a phase difference. The 15-bit image signal and the 1-bit reference signal and CLK of the output of S / P111 and the output of S / P112 which have this phase difference are the data input of memory A113 and memory B114 (hereinafter referred to as DAT).
A_IN) and write address reset (hereinafter WRS
T) and the write clock (hereinafter WCLK).

FIG. 2 is a timing chart showing the operations of the memory A 113 and the memory B 114. In FIG. 2, it is assumed that the image A signal input to the memory A leads the image B signal input to the memory B in phase. Memory A and memory B
Resets the write address at the rising edge of the WRST signal and outputs DATA at the timing of WCLK.
Write _IN to address 0 to address 3. At this time, the timings of writing in the memory A and the memory B have a phase difference. In addition, addresses 0 to 0 of the memory A and the memory B
The data written in the address 3 is held for 4 CLKs. The data written at different timings with this phase difference is used as a read address reset signal (hereinafter referred to as RRST) of the memory A and the memory B with the reference signal of the signal with the advanced phase, and the CLK of the signal with the advanced phase is used.
Read CLK of memory A and memory B (hereinafter RCL
As K), by reading the DATA while the DATA is held at the addresses 0 to 3, the data having no phase difference can be output from the memory A and the memory B. That is, in FIG. 2, the reference signal A is used for RRST of the memories A and B, and CL is used for RCLK of the memories A and B.
Image A from memory A and image B from memory B using KA
Is output.

Next, a configuration example of the memory A 113 and the memory B 114 is shown in FIG. The input signals are image A and image B having a phase difference, reference signal A and reference signal B, CLKA and CL.
It is KB. In this example, it is assumed that the phases of the image A, the reference signal A, and CLKA are advanced. First, the block of the memory A113 will be described. The image A is input to flip-flops (hereinafter FF) 304, 305, 306, 307.
The reference signal A is input as the clock of the FF 304 and the data of the FF 301. CLKA is FF301, 30
2, 303 and clock input to the counter 308.
The reference signal A input to the FF301 is input to the FF302 with a delay of 1 CLK, and further to FF303 with a delay of 1 CLK.
, And is output 1 CLK later. FF30
The output of 1 becomes the CLK of FF305, the output of FF302 becomes the CLK of FF306, and the output of FF303 becomes F.
It becomes CLK of F307. That is, FF304, 30
5, 306, and 307 have the same input data signal, but CLK is a signal that rises once every 4 CLK delayed by 1 CLK. Therefore, the image A is FF304, 30
It is written in 5, 306, 307 with 1 CLK offset,
It will be held for 4 CLK. That is, FF30
4, 305, 306 and 307 are four address spaces of the memory A 113. FF304, 30
The outputs of 5, 306 and 307 are the selectors 30 respectively.
The 9th input is input as 0th input, 1st input, 2nd input, and 3rd input. The counter 308 resets the count value to the initial value with the reference signal A, and outputs the count value of 0 to 3 CLK. This output is a 4-input / 1-output selector 309.
Is input as the select value of. The selector 309 is
Inputs 0 to 3 are selected based on the select value and output.

Next, the blocks of the memory B114 will be described. Image B, reference signals B and C are stored in the memory B114.
LKB is input. The image B is input as the input signal to the FFs 314, 315, 316, and 317. The reference signal B is input as a clock input of the FF 314 and an input data signal of the FFs 311, 312, 313. CLKB is FF311, 312,
It becomes the clock input of 313. FF3 of memory B114
11, 312, 313, 314, 315, 316, 31
7 is FFs 301, 302, 303 of the memory A 113,
Operates in the same way as 304, 305, 306, 307, and FF
The images 314, 315, 316, and 317 are shifted by 1 CLK each time, and the image B is written, and each image is held for 4 CLK. FF
The outputs of 314, 315, 316, and 317 are 4 respectively.
Input 1 output selector 318 0th input, 1st input, 2
It is input as the third input and the third input. The 4-input 1-output selector 318 inputs the output signal of the counter 308 of the memory A 113 as a select value and selects the 0th to 3rd inputs based on the select value and outputs them. This 4 inputs 1
The output selectors 309 and 318 output the images A and B having no phase difference by inputting the select value at the common timing. With the above configuration, the operation shown in FIG. 2 can be performed and the phase difference can be corrected.

The 15-bit phase difference-corrected image signals output from the memory A 113 and the memory B 114 in FIG. 1 are input to the synthesizing circuit 115 and do not have the same phase difference as the GBR signal output from the signal source 100. Output a signal.

(Embodiment 2) FIG. 4 shows a configuration of an image signal transmission apparatus according to a second embodiment of the present invention, which is an example of division into two systems for transmission. It is assumed that the maximum phase difference between the signals is less than 2 CLK, and that the phase-advancing signal of the two transmitted image signals is unknown. When it is not known which of the two transmitted image signals has the advanced phase, it is necessary to provide the phase discriminating circuit in the first embodiment.

In FIG. 4, 401, 402, 403,
The operations of 404, 405, 411, and 412 are the same as those in the first embodiment.
101, 102, 103, 104, 105, 111,
Since it is the same as 112, it is omitted. 15bit output signal of serial / parallel conversion circuit (S / P) 411 and 412
Image signal, 1-bit reference signal, and CLK are input to the memory A 413 and the memory B 414 as in FIG.
~ Written to address 3. At this time, the reference signals A and CLKA output from the S / P 411 and the reference signals B and CLKB output from the S / P 412 are input to the phase determination circuit 420. The phase discrimination circuit 420 discriminates a signal in which the phase of the two-system signal is advanced.

The realization method of this phase discrimination circuit 420 is as follows.
For example, the following method can be considered. Time from rising of reference signal A to rising of reference signal B (X)
Then, in the time from the rising of the reference signal B to the rising of the reference signal A (4 CLK-X), the system of the first rising reference signal when the rising interval is less than 2 CLK of the maximum phase difference known in advance. Determined as a system with advanced phase. That is, if X is less than 2 CLK, the reference signal A
The phase of the system of 1 is advanced, and when X is 2 CLK or more, the phase of the system of the reference signal B is advanced.

The selector 421 inputs the reference signal A and the reference signal B, and the selector 422 inputs the CLKA and CLKB. Based on the output of the phase discriminating circuit 420, respectively.
It outputs the reference signal of the system in phase and CLK. The read reset signal and read CLK of the memory A 413 and the memory B 414 are output signals of the selectors 421 and 422. The operations of the memory A 413, the memory B 414, and the synthesizing circuit 415 are the same as those in the first embodiment, and will not be repeated.

In this embodiment, the phase difference is 2CL.
Since there are four memory addresses even though the number is less than K, it becomes redundant. Therefore, it is desirable to use two memory addresses. The circuit at that time is shown in FIG. FIG. 5 shows a circuit almost similar to that of FIG. 3, but in FIG. 3, there are four flip-flops that serve as addresses in both memory A and memory B.
04 and 505, 514 and 515, and the clock input of this flip-flop is set to 2CLK by using two OR circuits 506 and 507, 516 and 517, respectively.
This is the rising signal of the number of times. With such a circuit configuration, it is possible to realize the memory A413 and the memory B414 in FIG. 4 without redundancy, when the system in which the maximum phase difference is less than 2 CLK and the phase is advanced is not known.

As described above, according to this embodiment, the phase difference can be corrected even when the system having the most advanced phase when it is transmitted through a plurality of transmission lines is not known. it can.

[0026]

As described above, according to the present invention, in a device for dividing one parallel digital image signal into a plurality of transmission lines and transmitting the same through a plurality of transmission lines, there is a phase difference between the plurality of transmission lines. When correcting the phase difference, it is possible to correct the phase difference without providing a special phase difference detection circuit when the system with the most advanced phase among the signals transmitted through the transmission paths of the multiple systems is known. Has the effect of enabling.

Further, even if the system of the signal with the most advanced phase among the signals transmitted through the plurality of systems of transmission lines is not known, a simple phase discrimination circuit is provided to detect a special phase difference amount. There is an effect that the phase difference can be corrected without providing a circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of an image signal transmission device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining operations of a memory A and a memory B in the same device.

FIG. 3 is a block diagram of a memory A and a memory B in the same device.

FIG. 4 is a block diagram of an image signal transmission device according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a memory A and a memory B in the same device.

FIG. 6 is a block diagram of a phase difference correction circuit in a receiver of a conventional image signal transmission device.

[Explanation of symbols]

1000, 4100 Transmitter 1100, 4100 Receiver 101, 401 Signal source 102, 402 Separation circuit 103, 403 Reference signal generation circuit 104, 105, 404, 405 Parallel / serial conversion circuit (P / S) 111, 112, 411, 412 serial / parallel conversion circuit (S / P) 113, 114, 413, 414 memory circuit 115, 415 combination circuit 301, 302, 303, 304, 305, 306, 3
07, 311, 312, 313, 314, 315, 31
6, 317, 501, 502, 503, 504, 50
5, 511, 512, 513, 514, 515 Flip-flop circuit 308, 508 Counter 309 318, 509, 518 Selector 340, 540 Output signal 506, 507, 516, 517 OR circuit

Claims (3)

[Claims] 1. A transmission unit that divides an n-bit digital image signal output from a signal source into a plurality of parallel signals and adds each signal to a reference signal with a constant period of 1 bit into a serial signal. After reproducing from the plurality of serial signals from the plurality of serial signals in the receiving unit and after reproducing the same plurality of parallel signals and a plurality of reference signals and a plurality of clock signals synchronized with the parallel signals and the reference signals,
The plurality of transmitted and reproduced parallel signals are independently written into different memory circuits at respective timing reference signals to reset write addresses and write at respective clock timings, and have a phase difference at the time of transmission. An image signal characterized by performing read address reset by the reference signal of the signal with the most advanced phase among the plurality of transmitted signals written in the memory as it is, and by reading with the clock of the signal with the most advanced phase Transmission equipment. 2. A source for generating a parallel digital image signal, a means for dividing the parallel digital image signal into a plurality of parallel signals, and a reference signal having a constant fixed period common to each of the plurality of parallel signals. Means, means for converting each of the signals obtained by adding the reference signal to the plurality of parallel signals to a serial signal and outputting as a plurality of serial signals, means for transmitting each of the plurality of serial signals, and Means for receiving a plurality of serial digital signals, a plurality of parallel signals and reference signals immediately after the original division from each of the received plurality of serial digital signals, and a clock synchronized with the parallel signals and the reference signals And a phase difference generated during transmission of the plurality of reproduced parallel signals. Of memory means having an address for the number of clocks longer than the previously known maximum time, means for writing the plurality of reproduced parallel signals into the memory, and write addresses for the plurality of memory means respectively. Means for resetting with the reproduced reference signal, means for writing the reproduced parallel signals to the plurality of memory means in synchronization with the respective reproduced clocks, and reading of the plurality of memory means A means for performing address reset with a common reset signal and a means for reading each parallel signal written in the plurality of memory means at a common clock timing are provided, and the common reset signal and the common clock are used as the common clock. Serial signal with the most advanced phase among multiple serial signals transmitted Image signal transmission apparatus characterized by the use of al reproduced reference signal and the clock. 3. A phase discriminating circuit for discriminating the most advanced phase signal among a plurality of reproduced parallel signals, and a reference signal and a clock for the most advanced phase signal based on the output of the phase discriminating circuit. 3. The image transmission device according to claim 2, further comprising a plurality of selectors for providing the respective memory means.