JPH09289421A - High frequency power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a simple and compact circuit constitution for a drain bias circuit of an FET by using a parallel resonance circuit consisting of a microstrip line and a capacitor to construct the drain bias circuit and optimizing the length and width of the microstrip line and also the capacity value of the capacitor. SOLUTION: A drain bias circuit of an FET 11 consists of a parallel resonance circuit 14 consisting of a microstrip line 12 and a capacitor 13. The capacity of a bypass capacitor 15 is controlled together with the line and width of the line 12 and the capacity value of the capacitor 13 respectively. At the same time, the reflection coefficient is minimized between an output terminal 16 and the FET 11 and also the largest power is supplied to a load resistance. As a result, the length and width of the line 12 can be reduced and increased respectively. Thus, it is possible to eliminate the elements of large electric length, to suppress the phase rotation, to secure the matching of unexpected frequency bands, and to prevent a sudden change of gain at a point near the relevant frequency. Furthermore, a simple and compact constitution is attained for the drain bias circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drain bias circuit for a field effect transistor in a high frequency power amplifier for the quasi-microwave band used in mobile communication devices such as mobile phones.

[0002]

2. Description of the Related Art In recent years, there has been a strong demand for miniaturization and weight reduction of semiconductor devices and electronic components used in mobile communication equipment such as mobile phones and portable radios.
High-frequency power amplifiers used in these transmitters are also required to be downsized.

A field effect transistor (hereinafter abbreviated as FET) for power amplification is used in such a high frequency power amplifier, and its output circuit has a drain voltage supply side Vdd from the drain electrode side of the FET. In order to obtain a sufficiently high impedance in the high frequency region, a drain bias circuit is usually formed by a microstrip line having a length of λ / 4 (λ: wavelength of the fundamental wave).

An example of such a drain bias circuit is shown in the circuit diagram of FIG. In FIG. 4, 1 is an FE for power amplification
A drain bias circuit composed of a microstrip line 2 having a length of λ / 4 and a bypass capacitor 3 is formed on the drain side thereof. Thereby, F
When the drain voltage supply side Vdd is seen from the point A on the drain electrode side of ET1, it is coupled in terms of direct current but has a high impedance so that there is no leakage of power in terms of high frequency.
The high frequency power amplified by T1 is output to the output terminal 4.

Further, in such a drain bias circuit, the reflection coefficient of the FET 1 side viewed from the output terminal 4 side is made as small as possible, and the maximum electric power is supplied to the load resistor (not shown). The capacitance value of the bypass capacitor 3 (usually about 1000 pF) and the length of the microstrip line 2 are adjusted. Therefore, the microstrip line 2 is arranged not only on the substrate surface of the circuit board of the high-frequency power amplifier, but also on the back surface of the circuit board so that the microstrip line 2 can be drawn in the widest and longest manner. A structure is employed in which the circuit is provided and connected to the circuit on the surface of the substrate through a via hole or the like, or the circuit substrate is multilayered and the microstrip line 2 is inner layered.

[0006]

However, in the conventional drain bias circuit configured as described above,
Since the microstrip line 2 having a length of λ / 4 is used, there are the following problems.

Since the size of the microstrip line 2 becomes very large, for example, about 30 mm for a frequency of 1.5 GHz, it is difficult to downsize the high frequency power amplifier.

As shown in the circuit diagram of FIG. 5, the bypass capacitor 3 in an actual drain bias circuit has a capacitor component 5 and a via hole for electrically connecting the bypass capacitor 3 or the bypass capacitor 3 and the ground. Since it has the parasitic inductor component 6, it constitutes a series resonator. Therefore, due to the actual length of the microstrip line 2, a low frequency AC signal of about several tens of MHz cannot be blocked and leaks between the resonance frequency of the series resonator and the DC (0 Hz), Oscillation via the drain may occur at the frequency of the AC signal.

The size of the microstrip line 2 is λ /
4 and large electric length make S
_Since the phase rotation of ₁₁ (forward reflection coefficient) may be large, S ₁₁ may pass the matching point twice,
Or worse take a chance matched in the frequency band that does not differ from expected transmission band for the gain S ₂₁ (forward transmission coefficient) certain size to a frequency band is obtained (about 20～30MHz) is required On the other hand, the gain S ₂₁ may change sharply before and after the matched frequency. Therefore, in order to prevent this, the matching circuit is adjusted so that the high frequency power is amplified only near the predetermined frequency. Necessary, which makes circuit design difficult.

The present invention has been completed as a result of intensive research conducted by the present inventor in order to solve the above problems, and an object thereof is to eliminate the need for an element having a large electric length such as a λ / 4 line. The high-frequency power amplifier can be downsized, while suppressing phase rotation to prevent unexpected gain matching in the frequency band and steep changes in the gain near the matched frequency, as well as oscillation via the drain. F that can be prevented
An object of the present invention is to provide a high frequency power amplifier including an ET drain bias circuit.

[0011]

A high frequency power amplifier according to the present invention is a high frequency power amplifier using field effect transistors, wherein the drain bias circuit of the field effect transistors is a parallel resonance circuit including a microstrip line and a capacitor. It is characterized by being configured using a circuit.

According to the high frequency power amplifier of the present invention, a parallel resonance circuit composed of a microstrip line and a capacitor is used in place of the λ / 4 length microstrip line which constitutes the conventional drain bias circuit. Since the drain bias circuit is configured, the length of the microstrip line can be significantly shortened, the drain bias circuit can be extremely miniaturized, and the circuit configuration can be simplified, thereby, the high frequency power amplifier. Can be further miniaturized.

Further, according to the high frequency power amplifier of the present invention, since a device having a large electrical length such as λ / 4 length is eliminated from the drain bias circuit circuit, it is possible to suppress the phase rotation. This makes it possible to prevent matching in a frequency band that does not exist and sharp changes in the gain near the matched frequency.

Further, according to the high frequency power amplifier of the present invention, it is possible to freely block any frequency by adjusting the inductance component or the capacitor component of the parallel resonant circuit in the drain bias circuit to a desired value. Therefore, if the frequency at which oscillation via the drain due to the bypass capacitor may occur is known in advance, the parallel resonant circuit should be adjusted to block that frequency to prevent oscillation via the drain. Can be deterred.

Furthermore, according to the high frequency power amplifier of the present invention, even when it is desired to set a pass stop band in order to prevent oscillation via the drain for a plurality of frequencies, a plurality of the parallel resonant circuits are connected in series. By connecting to, the desired pass-stop band can be set freely because a desired pass-through frequency can be blocked with a smaller occupied area than the conventional drain bias circuit. Oscillation can be effectively and efficiently suppressed.

As described above, according to the present invention, the high-frequency power amplifier can be miniaturized, and at the same time, matching in an unexpected frequency band, a steep change in the gain in the vicinity of the matched frequency, or via a bias is performed. It was possible to provide a high-frequency power amplifier including a FET drain bias circuit capable of preventing the above oscillation.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of a drain bias circuit of an FET showing an embodiment of a high frequency power amplifier of the present invention. In the figure, 11 is a FET for power amplification,
A parallel resonance circuit 14 including a microstrip line 12 and a capacitor 13 is formed on the drain side. 15 is a bypass capacitor, and these parallel resonance circuits
A drain bias circuit is constituted by 14 and the bypass capacitor 15. As a result, when the drain voltage supply side Vdd is seen from the drain electrode side of the FET 11, the high frequency power amplified by the FET 11 has a high impedance so that the power is not leaked in terms of high frequency although it is coupled in terms of direct current. Output to output terminal 16.

FE in the high frequency power amplifier of the present invention
In the drain bias circuit of T, the capacitance of the bypass capacitor 15 is set so that the reflection coefficient when the FET 11 side is viewed from the output terminal 16 side becomes as small as possible and the maximum electric power is supplied to the load resistor (not shown). The value, the length / width of the microstrip line 12 of the parallel resonant circuit 14, and the capacitance value of the capacitor 13 are adjusted. Here, the microstrip line 12 is different from the conventional λ / 4 length,
It can be formed as a line having a short length and a wide width. Therefore, it is possible to suppress the phase rotation by eliminating the element having a large electric length, and it is possible to prevent the matching in an unexpected frequency band and the steep change of the gain in the vicinity of the matched frequency. The width of the microstrip line 12 may be the same as that of the conventional λ / 4 length, or may be narrower depending on the specifications.

The size of the microstrip line 12 is FET
It is appropriately set according to the frequency to be amplified by 11 and the frequency at which passage is blocked from the capacitance value of the capacitor 13 connected in parallel. For example, a capacitor 13 for a frequency of 1.5 GHz
When the capacitance value is about 3 to 10 pF, the microstrip line 12 has a length of about 3 to 5 mm and a width of about 0.2 to 0.4 m.
It is sufficient to set the length to about m, and it is possible to form a microstrip line with a length of about λ / 4 and a width of about 0.2 mm. Is. Note that the thickness, material, forming method, etc. of the microstrip line 12 may be those conventionally known.

Further, the microstrip line 12 is not only arranged on the surface of the circuit board of the high frequency power amplifier, but also on the surface of the circuit board so that it can be arranged most efficiently according to the demand. Microstrip line on the back
A configuration may be adopted in which 12 is provided and connected to the circuit on the surface of the substrate through a via hole or the like, or the circuit substrate is multilayered and the microstrip line 12 is provided inside.

A multilayer ceramic chip capacitor, a thin film chip capacitor, or the like may be used for the capacitor 13,
Surface mounting using a chip capacitor can reduce the area occupied on the circuit board, which is advantageous for downsizing the drain bias circuit. The capacitance value may be arbitrarily set according to the frequency at which passage is blocked and according to the size of the microstrip line 12 connected in parallel.

With these, the parallel resonant circuit may be set so that the leakage power of the AC signal toward the drain power source Vdd is as small as possible. Then, by connecting a plurality of these parallel resonance circuits in series, the resonance frequency is a resonance frequency at which oscillation via the drain may occur due to the series resonator due to the capacitor component of the bypass capacitor 15 and the parasitic inductance component. By setting to, it becomes possible to prevent passage of the resonance frequency as desired, and it is possible to suppress oscillation via the drain.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. FIG. 2 shows an example in which a plurality of parallel resonance circuits (three in this example) for forming a drain bias circuit are connected in series. Reference numeral 21 denotes a power amplification FET, and 22a, 22b, 22c. Is a microstrip line, 23
a. 23b. 23c are capacitors, and 24a. 24b. 24c are parallel resonant circuits composed of them. Also 25a ・ 25b ・ 25c
Is a bypass capacitor, which constitutes a drain bias circuit, and the high frequency power amplified by the FET 21 is output to the output terminal 26.

In this way, the parallel resonance circuits 24a, 24b, 24c
If multiple drains are connected in series to form a drain bias circuit, the length and width of the microstrip lines 22a, 22b, 22c, or the capacitance value of the capacitors 23a, 23b, 23c in each parallel resonant circuit 24a, 24b, 24c. Of the parallel resonant circuit 24 by setting
Resonance can be achieved at different frequencies for each of a, 24b, and 24c, whereby passage of arbitrary plural frequencies can be blocked, and a desired pass stop band can be set. Moreover, since the area occupied by each of the parallel resonant circuits 24a, 24b, and 24c is small, the high-frequency power amplifier can be sufficiently miniaturized even with such a drain bias circuit.

FIG. 3 is a circuit diagram showing another embodiment of the present invention. FIG. 3 shows an example in which two amplifying FETs are used to configure the drain bias circuit of the present invention, 31a and 31b are power amplifying FETs, 32a and 32b are microstrip lines, and 33a / 33
Reference numeral b is a capacitor, and 34a and 34b are parallel resonant circuits including them. Further, 35a and 35b are bypass capacitors, which form a drain bias circuit. Further, 36a, 36b and 36c are matching circuits, 36a is an input matching circuit of the FET 31a, 36b is an output matching circuit of the FET 31a and an input matching circuit of the FET 31b,
36c is configured as an output matching circuit of the FET 31b, and by these, the high frequency power amplified by the FETs 31a and 31b is output to the output terminal 37.

As described above, the high frequency power amplifier using two FETs has a circuit configuration that is usually adopted in order to obtain a sufficient gain. In the conventional drain bias circuit using the λ / 4 length microstrip line, a signal (especially a low frequency signal) that cannot be removed by the bypass capacitor is fed back through the common power supply line Vdd in the drain bias circuit, which causes oscillation. However, by configuring the drain bias circuit by using the parallel resonant circuits 34a and 34b as in this example, the length and width of the microstrip lines 32a and 32b and the capacitance value of the capacitors 33a and 33b can be generated. By adjusting, it is possible to prevent passage of signals (especially low-frequency signals) that cannot be removed by the bypass capacitors 35a and 35b, thereby suppressing oscillation via the drain. Also in this example, since the area occupied by each of the parallel resonant circuits 34a and 34b is small, the high frequency power amplifier can be sufficiently miniaturized even when such a drain bias circuit is used. .

[0028]

EXAMPLES Specific examples will be described in detail below. Example 1 First, as a comparative example, a high frequency power amplifier including the conventional drain bias circuit shown in the circuit diagram of FIG. 4 was manufactured. Here, the dimensions of the microstrip line 2 are 30 mm in length and 0.4 mm in width, and the bypass capacitor 3
The electrostatic capacitance used was 1000 pF. The parasitic inductance component 6 due to the via hole of the bypass capacitor 3 was 0.8 nH.

Next, a high frequency power amplifier having the drain bias circuit according to the present invention shown in the circuit diagram of FIG. 1 was produced. The dimensions of the microstrip line 12 are 5.0 mm long and 0.4 mm wide, and the capacitance of the capacitor 13 is 6.0 pF to form the parallel resonant circuit 14. The capacitance of the bypass capacitor 15 is the same as above.
The one with 1000 pF was used. Bypass capacitor 15
The parasitic inductance component due to the via hole is 0.8 nH
Met.

With respect to these high frequency power amplifiers, S ₂₁ (FET1.
Transmission coefficient from 11 side to output terminal 4/16 side) and S ₃₁
(Transmission coefficient from FET1 / 11 side to Vdd side) is measured,
The drain bias circuit in the conventional high-frequency power amplifier is shown in FIG. 6, and the drain bias circuit in the high-frequency power amplifier of the present invention is shown in FIG. 7 in FIG. 6 and FIG. And the vertical axis represents the magnitude of S ₂₁ and S ₃₁ . The dotted line in each figure is the characteristic curve of S ₂₁ , and the solid line is the characteristic curve of S ₃₁ .

From these results, the ability of the bias circuit to cut off the AC signal (from FET 1 · 11 side to Vdd
A comparison of the transmission coefficient to the side S ₃₁ ) shows that the measurement result of the conventional drain bias circuit shown in FIG. 6 shows that S ₃₁ is about −20 dB at a frequency of about 1.5 GHz, while FIG. In addition, the measurement result of the drain bias circuit of the present invention shows that the attenuation of about −30 dB or more is obtained in the vicinity of about 1.5 GHz. Therefore, it is confirmed that the present invention can obtain the drain bias circuit having more excellent characteristics. did it.

The size of the microstrip line 12 in the drain bias circuit of the high-frequency power amplifier of the present invention is 5.0 mm in length × 0.4 mm in width, which is much larger than that of the microstrip line 2 in the conventional drain bias circuit. Since it is small, it was confirmed that the drain bias circuit could be significantly downsized, and the high frequency power amplifier could be downsized accordingly.

[Example 2] As a drain bias circuit in a high frequency power amplifier of the present invention constituted by connecting a plurality of parallel resonance circuits in series, a high frequency power having a drain bias circuit shown in the circuit diagram of Fig. 8 is constructed. An amplifier was made. In FIG. 8, 41 is a FET, and 42a, 42b, 42
c is a microstrip line, 43a, 43b, 43c are capacitors, 44a, 44b, 44c are parallel resonant circuits, 45 is a bypass capacitor, and 46 and 47 are the capacitor component and parasitic inductance component of the bypass capacitor 45, respectively.
48 is an output terminal.

Here, the microstrip lines 42a and 42a
The dimensions of b and 42c are 5.0 mm long and 0.4 mm wide, and the capacitance of the capacitor 43a is 6 pF.
b was 32 pF and the capacitor 43c was 12 pF. Further, the capacitor component 46 of the bypass capacitor 45 was 1000 pF, and the parasitic inductance component 47 due to the via hole was 0.8 nH.

Regarding this high frequency power amplifier, as in the case of [Example 1], the transmission characteristic of the drain bias circuit is S.
₂₁ and S ₃₁ were measured, and in FIG. 9 showing the results in a diagram in FIG. 9, the horizontal axis represents the frequency f and the vertical axis represents the magnitudes of S ₂₁ and S ₃₁ , as in FIGS. 6 and 7. The dotted line is the characteristic curve of S ₂₁ , and the solid line is the characteristic curve of S ₃₁ .

From the results of FIG. 9, in the case of the drain bias circuit in which a plurality of parallel resonance circuits are connected, R ₁ · R in the figure is shown.
It can be seen that the parallel resonance point indicated by ₂ · R ₃ can increase the low-frequency stopband. Increasing the stop band in this way is impossible with a conventional drain bias circuit using a λ / 4 length microstrip line, and the drain bias circuit in the high-frequency power amplifier of the present invention can be any desired It was confirmed to be extremely useful because the passband can be set freely with respect to the frequency.

The present invention is not limited to the above examples, and various modifications and improvements can be made without departing from the spirit of the present invention.

[0038]

As described above, according to the present invention, since the drain bias circuit of the FET is configured by using the parallel resonance circuit including the microstrip line and the capacitor, the length of the microstrip line is significantly increased. It is possible to shorten the size of the drain bias circuit without using an element having a large electric length such as a λ / 4 line, and to simplify the circuit configuration. It has been possible to provide a possible high frequency power amplifier.

Further, according to the present invention, since a device having a large electric length such as λ / 4 length is eliminated from the drain bias circuit, the phase rotation can be suppressed, thereby matching in an unexpected frequency band. It is possible to prevent a sharp change in the gain near the frequency where
It has been possible to provide a high frequency power amplifier including the ET drain bias circuit.

Further, according to the present invention, by adjusting the inductance component or the capacitor component of the parallel resonance circuit composed of the microstrip line and the capacitor to a desired value, a drain bias circuit capable of freely blocking passage of any frequency is provided. Therefore, if the frequency at which oscillation via the drain is likely to occur is known in advance, the oscillation via the drain should be suppressed by adjusting the parallel resonant circuit to block that frequency. It was possible to provide a high frequency power amplifier provided with a drain bias circuit of a FET capable of performing the above.

Furthermore, according to the present invention, even when it is desired to set a pass stop band in order to prevent oscillation via the drain for a plurality of frequencies, a plurality of parallel resonant circuits each including a microstrip line and a capacitor are provided. By connecting in series, arbitrary multiple frequencies can be blocked as desired with a smaller occupied area than the conventional drain bias circuit, so that the desired pass stop band can be freely set, and F capable of effectively and efficiently suppressing oscillation via the drain
It has been possible to provide a high frequency power amplifier including the ET drain bias circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a high frequency power amplifier of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the high frequency power amplifier of the present invention.

FIG. 3 is a circuit diagram showing another embodiment of the high frequency power amplifier of the present invention.

FIG. 4 is a circuit diagram showing a conventional high frequency power amplifier.

FIG. 5 is a circuit diagram showing a conventional high frequency power amplifier.

FIG. 6 is a diagram showing a transmission characteristic of a conventional high frequency power amplifier.

FIG. 7 is a diagram showing the transmission characteristics of the high frequency power amplifier of the present invention.

FIG. 8 is a circuit diagram showing another embodiment of the high frequency power amplifier of the present invention.

FIG. 9 is a diagram showing the transmission characteristics of the high frequency power amplifier of the present invention.

[Explanation of symbols]

Field effect transistors 12, 22a-c, 32a, b, 42a-c ... Microstrip lines 13, 23a-c, 33a, b , 43a-c ... Capacitors 14, 24a-c, 34a, b, 44a-c ... Parallel resonant circuit 15, 25a-c, 35a, b, 45 ... Bypass capacitors

Claims (1)

[Claims] 1. A high frequency power amplifier using field effect transistors, characterized in that the drain bias circuit of said field effect transistors is configured using a parallel resonance circuit composed of a microstrip line and a capacitor. Power amplifier.