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JPH09266351A - Alingan semiconductor light emitting element - Google Patents

Alingan semiconductor light emitting element

Info

Publication number
JPH09266351A
JPH09266351A JP7422096A JP7422096A JPH09266351A JP H09266351 A JPH09266351 A JP H09266351A JP 7422096 A JP7422096 A JP 7422096A JP 7422096 A JP7422096 A JP 7422096A JP H09266351 A JPH09266351 A JP H09266351A
Authority
JP
Japan
Prior art keywords
layer
gan
light emitting
buffer layer
stripe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7422096A
Other languages
Japanese (ja)
Inventor
Toshiro Hayakawa
利郎 早川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Priority to JP7422096A priority Critical patent/JPH09266351A/en
Priority to US08/827,252 priority patent/US6072818A/en
Publication of JPH09266351A publication Critical patent/JPH09266351A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/452Ohmic electrodes on AIII-BV compounds

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an AlInGaN semiconductor light emitting element which has an reduced impedance. SOLUTION: Sequentially grown on a sapphire face substrate 1 are a p-GaN low-temperature buffer layer 2, p-GaN buffer layer 3, p-In0.1 Ga0.9 N buffer layer 4, a cladding layer, a p-Al0.15 Ga0.85 N cladding layer 5, a p-GaN light guiding layer 6, an active layer 7, an n-GaN light guiding layer 8, an n-Al0.15 Ga0.85 N cladding layer 9 and an n-GaN cap layer 10. The grown structure is subjected to a plasma CVD process to form an SiN film 14 over its entire surface, subjected to photolithographic and etching processes to remove unnecessary parts except for an light emitting region therefrom, and then subjected to a reactive ion beam etching(RIBE) process using chlorine ions to remove an epitaxial layer other than the light emitting region until the p-GaN buffer layer 3 is exposed. The SiN film 14 is formed there in with a stripe-shaped window 12 for current injection, formed thereon with Ti/Al/Au layers as an n-side electrode 13 which covers the stripe window 12, and then an exposed area of the p-GaN buffer layer is deposited and annealed in a nitrogen atmosphere to form Ni/Au layers as a p-side ohmic electrode 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体発光素子の
構造に関し、特に詳しくは、発光ダイオード(LED)
および半導体レーザを含むAlxInyGa1-x-yN系半導体発光
素子に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor light emitting device, and more particularly, a light emitting diode (LED).
And an Al x In y Ga 1-xy N based semiconductor light emitting device including a semiconductor laser.

【0002】[0002]

【従来の技術】従来より、500nm を切る短波長光源とし
てAlInGaN系のLEDおよび半導体レーザが注目されて
いる。本材料は青・緑の波長領域の高輝度LEDとして
極めて優れた特性を有し(文献(1)Jpn.J.Appl.Phys.
vol.34,No.7A,pp.L797-799(1995))、信号機や屋外表示
装置の光源として実用化が進められている。また、半導
体レーザとしては、最近室温で417nm のパルス発振が報
告された(文献(2)Jpn.J.App1.Phys.vol35, No.1B,p
p.L74-76(1996))。
2. Description of the Related Art AlInGaN-based LEDs and semiconductor lasers have hitherto attracted attention as short-wavelength light sources below 500 nm. This material has extremely excellent characteristics as a high-intensity LED in the blue / green wavelength range (Reference (1) Jpn.J.Appl.Phys.
vol.34, No.7A, pp.L797-799 (1995)), is being put to practical use as a light source for traffic lights and outdoor display devices. As a semiconductor laser, a pulse oscillation of 417 nm has recently been reported at room temperature (Reference (2) Jpn.J.App1.Phys.vol35, No.1B, p).
p.L74-76 (1996)).

【0003】上記文献(2)記載のAlInGaN 系半導体レ
ーザでは、p型半導体層と電極との接触抵抗が非常に高
いため、パルス駆動時の動作電圧が数十ボルトと高くな
り、発振時に素子に投入される電力は通常の素子より10
倍程度高くなるため、素子の発熱や、変調時の歪みが大
きくなるという欠点がある。そこで、素子のインピーダ
ンスの低減が課題とされている。
In the AlInGaN type semiconductor laser described in the above-mentioned document (2), since the contact resistance between the p-type semiconductor layer and the electrode is very high, the operating voltage during pulse driving becomes as high as several tens of volts, and the element is oscillated during oscillation. The power input is 10 compared to normal devices
Since it is about twice as high, there is a drawback that the element heats up and distortion during modulation increases. Therefore, reduction of the impedance of the element has been an issue.

【0004】また、上記AlInGaN 系半導体レーザの応用
としては短波長化により現在実現されている630nm 半導
体レーザより格段に小さい径の光スポットが得られるこ
とから、光ディスクメモリの高密度化への応用が最も期
待される。このためには、安定な光ビームが得られる単
一モードレーザの実現が必須であり、AlInGaN 系で期待
される360-500nm の短波長域では横モード安定化のため
の作りつけの光導波路のストライプ幅は2μm程度かそれ
以下の狭ストライプであることが必要となる。
Further, as an application of the above AlInGaN type semiconductor laser, since a light spot having a diameter much smaller than that of the 630 nm semiconductor laser which is currently realized can be obtained by shortening the wavelength, it is applicable to high density optical disk memory. Most expected. For this purpose, it is essential to realize a single-mode laser that can obtain a stable light beam, and in the short wavelength range of 360-500 nm expected for AlInGaN system, a built-in optical waveguide for transverse mode stabilization is required. The stripe width needs to be a narrow stripe of about 2 μm or less.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記文
献に示される従来構造の素子においては基板上にn型半
導体層を先に積層した後にp型半導体層を積層して作製
する構成をとっており、狭ストライプを設ける場合、p
型半導体層と電極との接触面積が狭められ、さらにイン
ピーダンスを増加させることとなる。また、p型半導体
層に狭ストライプを形成すると、p型半導体自体の高抵
抗率もインピーダンス増加の要因となる。
However, the element having the conventional structure disclosed in the above-mentioned document has a structure in which the n-type semiconductor layer is first laminated on the substrate and then the p-type semiconductor layer is laminated. , When a narrow stripe is provided, p
The contact area between the type semiconductor layer and the electrode is narrowed, and the impedance is further increased. Further, when a narrow stripe is formed in the p-type semiconductor layer, the high resistivity of the p-type semiconductor itself also causes an increase in impedance.

【0006】本発明は、上記事情を鑑みてなされたもの
であり、インピーダンスを低減したAlInGaN 系半導体発
光素子を提供することを目的とするものである。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an AlInGaN-based semiconductor light emitting device having a reduced impedance.

【0007】[0007]

【課題を解決するための手段】本発明の半導体発光素子
は、基板上の少なくとも一部に、少なくともp型クラッ
ド層、活性層およびn型クラッド層を含む複数の半導体
層と絶縁膜とがこの順に積層され、前記絶縁膜に単一モ
ード発振をさせるための狭ストライプの電流注入窓が形
成され、前記絶縁膜上に前記電流注入窓を覆うようにn
側電極が形成され、前記p型クラッド層側にp側電極が
形成されているAlxInyGa1-x-yN(0≦x,y≦1)系半導体
発光素子において、前記p側電極が前記半導体層と接触
する面積が前記電流注入窓の面積よりも広いことを特徴
とするものである。
In a semiconductor light emitting device of the present invention, a plurality of semiconductor layers including at least a p-type cladding layer, an active layer and an n-type cladding layer and an insulating film are provided on at least a part of a substrate. N-stripe current injection windows for single mode oscillation are formed in the insulating film, and n is formed on the insulating film so as to cover the current injection windows.
In an Al x In y Ga 1-xy N (0 ≦ x, y ≦ 1) -based semiconductor light emitting device in which a side electrode is formed and a p-side electrode is formed on the p-type cladding layer side, the p - side electrode is The area in contact with the semiconductor layer is larger than the area of the current injection window.

【0008】すなわち、従来と異なり、基板側にp型半
導体層を先に成長しその後n型半導体層を成長してpn
接合を作製する構造をとったことにより、素子のストラ
イプ構造を形成する部分、すなわち面積が小さくなる部
分にn型半導体層を用い、抵抗率が高く電極との接触抵
抗も高いp型半導体層の面積を広くとり、p側電極との
接触面積も広くすることにより素子のインピーダンスを
下げたことを特徴とするものである。
That is, unlike the prior art, a p-type semiconductor layer is first grown on the substrate side, and then an n-type semiconductor layer is grown to pn.
By adopting the structure of forming the junction, the n-type semiconductor layer is used in the portion where the stripe structure of the element is formed, that is, in the portion where the area is small, and the p-type semiconductor layer having high resistivity and high contact resistance with the electrode is formed. It is characterized in that the impedance of the element is lowered by widening the area and widening the contact area with the p-side electrode.

【0009】[0009]

【発明の効果】本発明の半導体発光素子は、基板上にp
型半導体層を先に成長し、その後n型半導体層を成長さ
せる構造をとったことにより、ストライプ構造の発光素
子において、p側半導体と電極との接触面積も広くする
ことができ、リッジ構造を有する発光素子の場合には、
p型半導体層の面積を広くすることができる。これによ
り素子のインピーダンスを低減でき、動作電圧を低減し
高効率化・高出力化が実現できる。また、変調時の変調
周波数の向上や変調歪みの低減を図ることができる。従
って、これらの光源を用いた印刷・写真・医療画像など
のハードコピー出力システムの高速化・高品位化を実現
することができる。
The semiconductor light emitting device of the present invention has the p-type on the substrate.
Since the structure in which the p-type semiconductor layer is grown first and then the n-type semiconductor layer is grown, the contact area between the p-side semiconductor and the electrode can be widened in the light emitting device having the stripe structure, and the ridge structure can be formed. In the case of a light emitting element having
The area of the p-type semiconductor layer can be increased. As a result, the impedance of the element can be reduced, the operating voltage can be reduced, and high efficiency and high output can be realized. Further, it is possible to improve the modulation frequency during modulation and reduce modulation distortion. Therefore, it is possible to realize high speed and high quality of a hard copy output system for printing, photographs, medical images and the like using these light sources.

【0010】[0010]

【発明の実施の形態】以下、図面を用いて本発明の実施
の形態を説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0011】図1は、本発明に係る第一の実施の形態の
半導体レーザ断面模式図を示す。サファイアc面基板1
上にMOCVD法を用いて、p-GaN低温バッファ層2、
p-GaN バッファ層3(Mgドープ、5μm )、p-In0.1Ga
0.9Nバッファ層4(Mgドープ、0.1μm )、p-Al0.15Ga
0.85Nクラッド層5(Mgドープ、0.5μm)、p-GaN光ガイ
ド層6(Mgドープ、0.1μm)、アンドープ活性層7、n-
GaN 光ガイド層8(Siドープ、0.1μm )、n-Al0.15Ga
0.85Nクラッド層9(Siドープ、0.5μm)およびn-GaNキ
ャップ層10(Siドープ、0.3μm)を順次成長する。活性
層7は、アンドープAl0.04Ga0.96N 障壁層(0.01μ
m)、アンドープIn0.2Ga0.8N 量子井戸層(3nm)およ
びアンドープAl0.04Ga0.96N障壁層(0.01μm)の3層構
造とする。
FIG. 1 is a schematic sectional view of a semiconductor laser according to the first embodiment of the present invention. Sapphire c-plane substrate 1
P-GaN low temperature buffer layer 2, using MOCVD method,
p-GaN buffer layer 3 (Mg-doped, 5 μm), p-In 0.1 Ga
0.9 N buffer layer 4 (Mg-doped, 0.1 μm), p-Al 0.15 Ga
0.85 N cladding layer 5 (Mg-doped, 0.5 μm), p-GaN optical guide layer 6 (Mg-doped, 0.1 μm), undoped active layer 7, n-
GaN optical guide layer 8 (Si-doped, 0.1 μm), n-Al 0.15 Ga
A 0.85 N cladding layer 9 (Si-doped, 0.5 μm) and an n-GaN cap layer 10 (Si-doped, 0.3 μm) are sequentially grown. The active layer 7 is an undoped Al 0.04 Ga 0.96 N barrier layer (0.01 μm).
m), an undoped In 0.2 Ga 0.8 N quantum well layer (3 nm) and an undoped Al 0.04 Ga 0.96 N barrier layer (0.01 μm).

【0012】その後、窒素ガス雰囲気中で熱処理により
p型不純物を活性化する。
After that, the p-type impurities are activated by heat treatment in a nitrogen gas atmosphere.

【0013】次に、SiN 膜14をプラズマCVDで全面に
製膜した後、フォトリソグラフィとエッチングにより発
光領域以外の不要部分を除去する。
Next, after the SiN film 14 is formed on the entire surface by plasma CVD, unnecessary portions other than the light emitting region are removed by photolithography and etching.

【0014】この後、塩素イオンを用いたRlBE(re
active ion beam etching )により発光領域以外のエピ
タキシャル層をp-GaN バッファ層3が露出するまでエッ
チング除去する。この際にレーザの共振器端面を形成す
る。
After this, RlBE (re
The epitaxial layer other than the light emitting region is removed by etching by active ion beam etching until the p-GaN buffer layer 3 is exposed. At this time, the cavity end face of the laser is formed.

【0015】SiN 膜14に電流注入のためのストライプ状
窓12(幅10μm)を作製後、該ストライプ窓12を覆うよ
うにn側電極13としてTi/Al/Ti/Au を、またp-GaN バッ
ファ層3の露出部にp側電極11としてNi/Auを蒸着・窒
素中アニールしてオーミック電極を形成する。
After forming a stripe-shaped window 12 (width 10 μm) for current injection in the SiN film 14, Ti / Al / Ti / Au is used as an n-side electrode 13 so as to cover the stripe window 12 and p-GaN. Ni / Au is vapor-deposited on the exposed portion of the buffer layer 3 as the p-side electrode 11 and annealed in nitrogen to form an ohmic electrode.

【0016】図2は、本発明に係る第二の実施の形態の
リッジ光導波構造を有する半導体レーザ断面模式図を示
す。サファイアc面基板1上にMOCVD法を用いて、
p-GaN 低温バッファ層2、p-GaNバッファ層3(Mgドー
プ、5μm)、p-In0.1Ga0.9Nバッファ層4(Mgドープ、
0.1μm)、p-Al0.15Ga0.85Nクラッド層5(Mgドープ、
0.5μm)、p-GaN 光ガイド層6(Mgドープ、0.1μm)、
アンドープ活性層27、n-GaN 光ガイド層8(Siドープ、
0.1μm)、n-Al0.15Ga0.85Nクラッド層9(Siドープ、
0.5μm)、n-GaNキャップ層10(Siドープ、0.3μm )を
成長する。活性層27は、アンドープAl0.04Ga0.96N 障壁
層(0.01μm )、アンドープIn0.2Ga0.8N 量子井戸層
(3nm)4層/アンドープIn0.1Ga0.9N障壁層(5nm)3
層よりなる多重量子井戸構造およびアンドープAl0.04Ga
0.96N 障壁層(0.01μm)とする。
FIG. 2 is a schematic sectional view of a semiconductor laser having a ridge optical waveguide structure according to a second embodiment of the present invention. Using the MOCVD method on the sapphire c-plane substrate 1,
p-GaN low temperature buffer layer 2, p-GaN buffer layer 3 (Mg-doped, 5 μm), p-In 0.1 Ga 0.9 N buffer layer 4 (Mg-doped,
0.1 μm), p-Al 0.15 Ga 0.85 N cladding layer 5 (Mg-doped,
0.5 μm), p-GaN optical guide layer 6 (Mg-doped, 0.1 μm),
Undoped active layer 27, n-GaN optical guide layer 8 (Si-doped,
0.1 μm), n-Al 0.15 Ga 0.85 N cladding layer 9 (Si-doped,
0.5 μm), and n-GaN cap layer 10 (Si-doped, 0.3 μm) is grown. The active layer 27 is composed of undoped Al 0.04 Ga 0.96 N barrier layer (0.01 μm), undoped In 0.2 Ga 0.8 N quantum well layer (3 nm) 4 layers / undoped In 0.1 Ga 0.9 N barrier layer (5 nm) 3
Layered multi-quantum well structure and undoped Al 0.04 Ga
0.96 N barrier layer (0.01 μm).

【0017】その後、窒素ガス雰囲気中で熱処理により
p型不純物を活性化する。
After that, the p-type impurities are activated by heat treatment in a nitrogen gas atmosphere.

【0018】次に、フォトリソグラフィとエッチングに
より、n-Al0.15Ga0.85N クラッド層9のn-GaN光ガイド
層8から0.1μmまでを残し厚として幅2.2μm程度のリッ
ジストライプを形成する。この際、リッジ端面近傍を素
子上部より見た模式図(図3)に示すように後でエッチ
ング形成する端面の部分に相当する領域は幅を20μmと
広く形成する。実線40はリッジエッチングの形状を、波
線41は端面形成エッチングの形状・位置関係を示す。図
のようにレーザ端面近傍でリッジ幅を広げているのはリ
ッジ部形状の端面の平坦性へ及ぼす悪影響を低減するた
めである(J.Quantum Electronics vol.27,pp.1319-133
1(1991))。次に、SiN 膜14をプラズマCVDで全面に
製膜した後、そのSiN 膜14をフォトリソグラフィとエッ
チングにより発光領域以外の不要部分を除去する。
Next, by photolithography and etching, a ridge stripe having a width of about 2.2 μm is formed by leaving the n-Al 0.15 Ga 0.85 N cladding layer 9 from the n-GaN optical guide layer 8 to 0.1 μm in thickness. At this time, as shown in the schematic view (FIG. 3) of the vicinity of the end face of the ridge viewed from the upper part of the element, the region corresponding to the end face to be formed later by etching has a wide width of 20 μm. A solid line 40 shows the shape of the ridge etching, and a wavy line 41 shows the shape / positional relationship of the end face forming etching. As shown in the figure, the reason for widening the ridge width near the laser end face is to reduce the adverse effect on the flatness of the ridge-shaped end face (J.Quantum Electronics vol.27, pp.1319-133.
1 (1991)). Next, after the SiN film 14 is formed on the entire surface by plasma CVD, the SiN film 14 is removed by photolithography and etching to remove unnecessary portions other than the light emitting region.

【0019】この後、塩素イオンを用いたRlBEによ
り発光領域以外のエピタキシャル層をp-GaNバッファ層
3が露出するまでエッチング除去する。この際にレーザ
の共振器端面を形成する。
After that, the epitaxial layer other than the light emitting region is etched away by RlBE using chlorine ions until the p-GaN buffer layer 3 is exposed. At this time, the cavity end face of the laser is formed.

【0020】この後、前記第一の実施の形態と同様にSi
N 膜14に電流注入のためのストライプ状窓12を作製後、
n側電極13としてTi/Al/Ti/Au 、p側電極11としてNi/A
u をそれぞれ蒸着・窒素中アニールしてオーミック電極
を形成する。
After this, as in the first embodiment, Si is used.
After forming the striped window 12 for current injection in the N film 14,
Ti / Al / Ti / Au as n-side electrode 13 and Ni / A as p-side electrode 11
Each u is vapor-deposited and annealed in nitrogen to form an ohmic electrode.

【0021】以上2件の実施の形態において、ストライ
プ上部のn-GaNキャップ層10へのn側電極接触幅は2-10
μm 程度であるが、p-GaNバッファ層3上に形成するp
側電極11の半導体層との接触面積はチップ全体の幅を広
げることによりn側電極の10-100倍程度広くとることが
可能である。従って、p型半導体層の接触抵抗率がn型
半導体層に比較して1-2 桁高い場合でもデバイス性能の
低下を防止することができる。また、電流通路となるp
-GaNバッファ層3の抵抗が問題となる場合には、厚みを
更に厚くすることにより低抵抗化できる。
In the above two embodiments, the contact width of the n-side electrode on the n-GaN cap layer 10 on the upper portion of the stripe is 2-10.
μm, but p formed on the p-GaN buffer layer 3
The contact area of the side electrode 11 with the semiconductor layer can be made 10 to 100 times wider than that of the n-side electrode by increasing the width of the entire chip. Therefore, even when the contact resistivity of the p-type semiconductor layer is higher than that of the n-type semiconductor layer by one or two orders of magnitude, it is possible to prevent deterioration of device performance. In addition, p which becomes a current path
-If the resistance of the GaN buffer layer 3 becomes a problem, the resistance can be lowered by further increasing the thickness.

【0022】すなわち、本発明は、主にn型キャップ層
とp型バッファ層の性質と構成要因により素子のインピ
ーダンスを低減するものである。
That is, the present invention is to reduce the impedance of the device mainly by the properties and constituent factors of the n-type cap layer and the p-type buffer layer.

【0023】従って、半導体レーザの層構造としては上
記実施の形態以外に量子井戸を用いないダブルヘテロ構
造など一般に考えられる種々の構造を採用することが可
能である。
Therefore, as the layer structure of the semiconductor laser, various generally conceivable structures such as a double hetero structure not using quantum wells can be adopted other than the above-mentioned embodiment.

【0024】また、基板としては、絶縁性物質ではスピ
ネル構造を有する物質(例えば、AlMg2O4 )等のサファ
イア以外の任意のものを用いることができる。更に、サ
ファイアのような絶縁性物質ではなく、SiC のような導
電性物質の基板21を用いて図4、図5のような素子構造
とする場合にも電極との接触面積の小さい半導体層をn
型とし、p側電極11がp型半導体層と接触する面積を広
くとることができるため低抵抗化が可能である。
As the substrate, any material other than sapphire such as a material having a spinel structure (for example, AlMg 2 O 4 ) can be used as the insulating material. Further, when the substrate 21 made of a conductive material such as SiC is used instead of an insulating material such as sapphire to form the element structure as shown in FIGS. 4 and 5, a semiconductor layer having a small contact area with the electrode is formed. n
Since the p-side electrode 11 can be formed in a large area and the p-side electrode 11 can make a large area in contact with the p-type semiconductor layer, the resistance can be reduced.

【0025】前記実施の形態においては、レーザ端面を
塩素イオンを用いたRlBEにより形成したが、通常の
劈開や光学研磨法などを用いて形成してもよい。
In the above-mentioned embodiment, the laser end face is formed by RlBE using chlorine ions, but it may be formed by a usual cleavage or optical polishing method.

【0026】以上半導体レーザ素子として述べたが、同
様の構造で端面発光型LEDとして用いる場合にも効果
があることは言うまでもない。前述の文献(1)に記載
されているような通常のLED構造においても、発光部
の上部電極は狭いほうが光を遮断する面積が小さく光り
の取り出し効率が上昇するためp型層上にn型層を形成
した本発明の構造を用いると低抵抗化できて有利であ
る。更に、LEDにおいては上部電極直下の電流拡がり
が大きいほうが均一発光が得られるので、上部にn型層
を用いて低抵抗化したほうがさらに有利である。
Although the semiconductor laser device has been described above, it is needless to say that it is also effective when it is used as an edge emitting LED with the same structure. Also in the normal LED structure as described in the above-mentioned document (1), the narrower the upper electrode of the light emitting section is, the smaller the area for blocking light is, and the light extraction efficiency is increased, so that the n-type is formed on the p-type layer. It is advantageous to use the structure of the present invention in which a layer is formed because the resistance can be reduced. Further, in the LED, the larger the current spread immediately below the upper electrode is, the more uniform light emission can be obtained. Therefore, it is more advantageous to use the n-type layer on the upper part to reduce the resistance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一の実施の形態に係る半体発光装置
の断面模式図
FIG. 1 is a schematic cross-sectional view of a half-body light emitting device according to a first embodiment of the invention.

【図2】本発明の第二の実施の形態に係る半導体発光装
置の断面模式図
FIG. 2 is a schematic sectional view of a semiconductor light emitting device according to a second embodiment of the present invention.

【図3】図2に示す本発明の第二の実施の形態に係る半
導体発光装置におけるリッジストライプと端面形成位置
との関係を示す説明図
FIG. 3 is an explanatory diagram showing a relationship between a ridge stripe and an end face formation position in the semiconductor light emitting device according to the second embodiment of the present invention shown in FIG.

【図4】本発明のその他の実施の形態に係る半導体発光
装置の断面模式図
FIG. 4 is a schematic sectional view of a semiconductor light emitting device according to another embodiment of the present invention.

【図5】本発明のその他の実施の形態に係る半導体発光
装置の断面模式図
FIG. 5 is a schematic sectional view of a semiconductor light emitting device according to another embodiment of the present invention.

【符号の説明】 1 サファイア基板 2 p-GaN低温バッファ層 3 p-GaNバッファ層 4 p-In0.1Ga0.9Nバッファ層 5 p-Al0.15Ga0.85Nクラッド層 6 p-GaN光ガイド層 7 アンドープ活性層 8 n-GaN光ガイド層 9 n-Al0.15Ga0.85Nクラッド層 10 n-GaNキャップ層 11、13 電極 14 SiN膜[Explanation of symbols] 1 sapphire substrate 2 p-GaN low temperature buffer layer 3 p-GaN buffer layer 4 p-In 0.1 Ga 0.9 N buffer layer 5 p-Al 0.15 Ga 0.85 N clad layer 6 p-GaN optical guide layer 7 undoped Active layer 8 n-GaN optical guide layer 9 n-Al 0.15 Ga 0.85 N cladding layer 10 n-GaN cap layer 11, 13 electrode 14 SiN film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板上の少なくとも一部に、少なくとも
p型クラッド層、活性層およびn型クラッド層を含む複
数の半導体層と絶縁膜とがこの順に積層され、前記絶縁
膜に単一モード発振をさせるための狭ストライプの電流
注入窓が形成され、前記絶縁膜上に前記電流注入窓を覆
うようにn側電極が形成され、前記p型クラッド層側に
p側電極が形成されているAlxInyGa1-x-yN(0≦x, y≦
1)系半導体発光素子において、 前記p側電極が前記半導体層と接触する面積が前記電流
注入窓の面積よりも広いことを特徴とするAlInGaN系半
導体発光素子。
1. A plurality of semiconductor layers including at least a p-type clad layer, an active layer and an n-type clad layer and an insulating film are laminated in this order on at least a part of a substrate, and single mode oscillation is performed on the insulating film. To form a narrow stripe current injection window, an n-side electrode is formed on the insulating film so as to cover the current injection window, and a p-side electrode is formed on the p-type cladding layer side. x In y Ga 1-xy N (0≤x, y≤
1) A system semiconductor light emitting device, wherein an area where the p-side electrode is in contact with the semiconductor layer is larger than an area of the current injection window.
JP7422096A 1996-03-28 1996-03-28 Alingan semiconductor light emitting element Pending JPH09266351A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP7422096A JPH09266351A (en) 1996-03-28 1996-03-28 Alingan semiconductor light emitting element
US08/827,252 US6072818A (en) 1996-03-28 1997-03-28 Semiconductor light emission device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7422096A JPH09266351A (en) 1996-03-28 1996-03-28 Alingan semiconductor light emitting element

Publications (1)

Publication Number Publication Date
JPH09266351A true JPH09266351A (en) 1997-10-07

Family

ID=13540896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7422096A Pending JPH09266351A (en) 1996-03-28 1996-03-28 Alingan semiconductor light emitting element

Country Status (1)

Country Link
JP (1) JPH09266351A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001044570A (en) * 1999-07-27 2001-02-16 Nichia Chem Ind Ltd Nitride semiconductor laser element
WO2001043206A1 (en) * 1999-12-13 2001-06-14 Nichia Corporation Light-emitting device
JP2001358404A (en) * 2000-06-09 2001-12-26 Nichia Chem Ind Ltd Semiconductor laser element and its manufacturing method
KR20030045573A (en) * 2001-12-04 2003-06-11 엘지이노텍 주식회사 Fabrication method of Light Emitting Diode
WO2005086244A1 (en) * 2004-03-05 2005-09-15 Epivalley Co., Ltd. Iii -nitride semiconductor light emitting device
WO2005088742A1 (en) * 2004-03-15 2005-09-22 Zakrytoe Aktsionernoe Obschestvo 'innovatsionnaya Firma 'tetis' High-power light emitting diode
US8633101B2 (en) 2009-10-01 2014-01-21 Toyota Jidosha Kabushiki Kaisha Semiconductor device and manufacturing method of semiconductor device
CN103715071A (en) * 2013-11-29 2014-04-09 南京大学扬州光电研究院 MOCVD epitaxy processing method of AlInGaN quaternary alloy thin-film material

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001044570A (en) * 1999-07-27 2001-02-16 Nichia Chem Ind Ltd Nitride semiconductor laser element
WO2001043206A1 (en) * 1999-12-13 2001-06-14 Nichia Corporation Light-emitting device
US6738175B2 (en) 1999-12-13 2004-05-18 Nichia Corporation Light emitting device
KR100688239B1 (en) * 1999-12-13 2007-03-02 니치아 카가쿠 고교 가부시키가이샤 Light-emitting device
JP2001358404A (en) * 2000-06-09 2001-12-26 Nichia Chem Ind Ltd Semiconductor laser element and its manufacturing method
KR20030045573A (en) * 2001-12-04 2003-06-11 엘지이노텍 주식회사 Fabrication method of Light Emitting Diode
WO2005086244A1 (en) * 2004-03-05 2005-09-15 Epivalley Co., Ltd. Iii -nitride semiconductor light emitting device
US7432534B2 (en) 2004-03-05 2008-10-07 Epivalley Co., Ltd. III-nitride semiconductor light emitting device
WO2005088742A1 (en) * 2004-03-15 2005-09-22 Zakrytoe Aktsionernoe Obschestvo 'innovatsionnaya Firma 'tetis' High-power light emitting diode
US8633101B2 (en) 2009-10-01 2014-01-21 Toyota Jidosha Kabushiki Kaisha Semiconductor device and manufacturing method of semiconductor device
CN103715071A (en) * 2013-11-29 2014-04-09 南京大学扬州光电研究院 MOCVD epitaxy processing method of AlInGaN quaternary alloy thin-film material

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