JPH09246920A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device with a built-in pulse generation circuit capable of obtaining the pulses of a desired duty without depending on the frequency of input pulses by simple constitution. SOLUTION: In a PLL circuit provided with a ring oscillator composed of the odd-numbered stages of delay circuits with a CMOS inverter circuit 12 to which an operating current corresponding to a control voltage is supplied as one delay circuit, it is utilized that the respective delay signals of the ring oscillator are provided with a timing difference corresponding to a stage number, the output signals of the respective delay circuits are selectively outputted by a selector 11 and internal pulse signals provided with the desired duty are formed by a logical processing with the oscillation output of the ring oscillator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a clock generation technique using a built-in PLL circuit.

[0002]

2. Description of the Related Art As a circuit for forming a pulse signal having a desired pulse duty, an input pulse and a delayed signal thereof are logically processed, and a pulse having a desired pulse width is obtained by adjusting the delay time. It is generally considered that this is done.

[0003]

In the case where the pulse duty is set by logically processing the input pulse and the pulse delayed by the delay circuit as described above, the variable rate of the pulse duty is set to the frequency of the input pulse. Depends on
It cannot be applied to a pulse formed by a pulse generating circuit that can be changed to various frequencies like a PLL circuit.

An object of the present invention is to provide a semiconductor integrated circuit device having a pulse generator circuit having a simple structure and capable of obtaining a pulse having a desired duty without depending on the frequency of an input pulse. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a PLL circuit including a ring oscillator including odd-numbered stages of delay circuits each having a CMOS inverter circuit supplied with an operating current corresponding to a control voltage as one delay circuit, each delay signal of the ring oscillator has a timing corresponding to the number of stages. By utilizing the difference, the output signal of each delay circuit is selectively output by the selector and logically processed with the oscillation output of the ring oscillator to form an internal pulse signal having a desired duty.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit diagram of an embodiment of a main part of a pulse generating circuit according to the present invention. Each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. In the same figure, the one with a circle attached to the gate represents a P-channel MOSFET. This also applies to the following drawings.

A ring oscillator is used as the VCO (voltage controlled oscillation) circuit 9. That is, N channel type M
For the CMOS inverter circuit 12 including the OSFET Q5 and the P-channel MOSFET Q6, the operating current is changed to the N-channel MOSFET Q3 and the P-channel MO.
Supply from SFET Q4
A control current corresponding to the control voltage of the oscillation frequency flows through TQ3 and Q4.

The control voltage is the N-channel type MO.
It is applied directly to the gate of SFET Q3. Such MO
The SFET Q3 performs a voltage / current conversion operation and operates as a current source MOSFET that forms a control current corresponding to the control voltage. The control voltage is an N-channel MOS
It is converted into a current signal by the FET Q1. The converted drain current is supplied to the diode-type P-channel MOSFET Q2. The P-channel MOSFET Q2 and the P-channel MOSFET
Q4 is in the form of a current mirror, and an operating current corresponding to the control voltage is formed from the MOSFET Q4 to generate the C
P-channel type MOSFE of the MOS inverter circuit 12
It is supplied to TQ6.

In the figure, the CMOS inverter circuit 1 described above is used.
Five similar CMOS inverter circuits including 2 are connected in a ring form in a column form. Each CMOS inverter circuit has an N-channel type MOSFET and a P-channel type MOSF which form a current corresponding to a control voltage as described above.
An operating current is supplied from ET. For example, when the control voltage is lowered, the operating current flowing through each CMOS inverter circuit decreases. When the operating current of such a CMOS inverter circuit decreases, the charge or discharge current of the input capacitance of the CMOS inverter circuit of the next stage is decreased by the output signal of the CMOS inverter circuit. As a result, the signal delay time increases and the oscillation frequency increases. Lower. Conversely, when the control voltage is increased, the operating current flowing through each CMOS inverter circuit increases. When the operating current of such a CMOS inverter circuit increases, the charge or discharge current of the input capacitance of the CMOS inverter circuit of the next stage is increased by the output signal of the CMOS inverter circuit. As a result, the signal delay time decreases and the oscillation frequency decreases. Make it higher In this way, the oscillation pulse corresponding to the control voltage is obtained.

The CMOS inverter circuit is composed of MOSFETs each having the same element constant. Therefore, based on the VCO oscillation output signal, the output signal of the 5-stage CMOS inverter circuit as in the above embodiment has a delay time of ⅕ to 1/2 cycle of the oscillation pulse. is there. The inventor of the present application considered using this fact to set the pulse duty of the output pulse.

That is, the output signal of each stage of the CMOS inverter circuit is supplied to the selector 11 as a clock (1), a clock (2), a clock (3) and a clock (4), and a desired pulse duty is supplied by this selector. Output to the gate circuits 13 and 14 together with the VCO output signal and synchronized with the VCO, and outputs (1) and (2) that have the desired pulse duty. Is to get.

In this embodiment, although not particularly limited, 2
An output circuit is provided to obtain the normal output (1) and output (2). One is to obtain an output (1) whose pulse duty is smaller than that of the VCO output signal by performing an AND process by the NAND gate circuit 13 and the inverter circuit N1. The other one is an output (2) in which the pulse duty is made larger than that of the VCO output signal by performing the logical sum processing by the NOR gate circuit 14 and the inverter circuit N2.
Is what you get.

FIG. 2 is a timing chart for explaining an example of the operation of the pulse generating circuit. The delay time t between the clock (1) and the clock (2) is the half cycle of the oscillation cycle divided by the number of stages of the CMOS inverter circuit, that is, the oscillation cycle / (2 × the number of stages). In other words, when the clock (1) is used as a reference, the VCO output signal rises (or falls) after a delay time of 5 × t from its rise (or fall).

The output (1) is shown when the clock (3) is selected by the above selection. That is, the output (1) is output from the VCO during the high level period of the clock (3).
The output signal rises at the timing when it exceeds the logic threshold, and falls when the clock (3) falls below the logic threshold while the VCO output signal is at the high level. Therefore, 3/10 = 30
It is possible to obtain a pulse with a pulse duty of%.

The output (2) is shown when the clock (3) is selected by the selection. That is,
The output (2) rises at the timing when the clock (3) exceeds the logic threshold and falls at the timing when the VCO output signal falls below the logic threshold. This makes it possible to obtain a pulse with a pulse duty of 7/10 = 70%.

As described above, the selector 11 does not necessarily have to be 4
One of the two output circuits may be supplied to the two output circuits, or one of them may be selected for each output circuit. The output (1) and the output (2) do not always have to be output as a pair, and only one clock pulse having a required duty may be used.

FIG. 3 shows the P including the ring oscillator.
An overall block diagram of the LL circuit is shown. Although not particularly limited, when the frequency itself of the output pulse is arbitrarily set, the reference frequency signal is divided by the program counter (frequency dividing circuit). The phase comparison circuit forms a phase difference (frequency difference) output between the divided signal and the VCO output signal, and the loop filter smooths it to form a control voltage, and the VCO output signal of the ring oscillator is divided into the above divided parts. Match the frequency signal.

In addition to the above program counter, the system clock may be used as the reference signal as shown by the dotted line in the figure. For example, in a semiconductor integrated circuit device that constitutes a memory or various peripheral circuits, a system clock of a microcomputer system in which the memory is mounted is input and an internal clock signal synchronized with the system clock is generated. In this case, the adjustment of the pulse duty may be useful for optimizing the setup time and hold time in taking in the address signal and data from the microprocessor in consideration of the delay in the signal transmission path. Become.

In this embodiment, the oscillation signal of the ring oscillator is set in synchronization with the system clock as described above, and the period corresponding to the frequency is equally divided into the delay signal of the ring oscillator. The pulse duty can maintain a desired duty without being influenced by the frequency. Moreover, since the signal of the delay stage of the ring oscillator is used, it can be realized by an extremely simple configuration in which a selector and a logic circuit are added. In addition to the setup and hold time settings above,
It can also be used to control the number of clocks to fetch the system clock by changing the duty of the signal.

In this embodiment, the selection signal S of the selector 11 is formed depending on whether the fuse F is blown or not.
P-channel MOSF between power supply voltage and circuit ground potential
The ETQ7 and the fuse F are connected in series, and the signal at the interconnection point is fed back to the gate of the P-channel MOSFET Q7 via the CMOS inverter circuit N3. As a result, if the fuse F is blown, the MOSFET
Q7 and the inverter circuit N3 form a latch circuit and form a low-level selection signal S. Hello F
If is not cut off, the input signal of the inverter circuit N3 becomes low level and the high level selection signal S is formed,
Since the P-channel MOSFET Q7 is turned off, it is possible to prevent the direct current from flowing through the fuse F.

The selector 11 is not particularly limited, but is C
It is composed of a MOS switch circuit. When one of the four inputs is selected as described above, two sets of fuse circuits similar to those described above are provided and are decoded to form one selection signal. In addition to this, one switch may be provided for each switch, and the one with the fuse blown may be selected.

The operational effects obtained from the above embodiment are as follows. (1) CM to which operating current corresponding to control voltage is supplied
In a PLL circuit including a ring oscillator including an odd number of stages of delay circuits with the OS inverter circuit as one delay circuit, the fact that each delay signal of the ring oscillator has a timing difference corresponding to the number of stages is used to The output signal is selectively output by the selector and logical processing is performed with the oscillation output of the ring oscillator to form an internal pulse signal with the desired duty, and the desired duty is maintained without being affected by the frequency with a simple configuration. It is possible to obtain the effect that the output pulse can be obtained.

(2) By using a ring oscillator that delays using a CMOS inverter circuit,
The effect that a pulse generation circuit with low current consumption can be obtained is obtained.

(3) By setting the pulse duty by the program element, an output pulse according to the purpose of use can be obtained, so that the versatility of the semiconductor integrated circuit device can be enhanced. .

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the inverter circuit may use a differential circuit other than the CMOS inverter circuit as described above. That is,
Semiconductor integrated circuit devices include ECL in addition to CMOS integrated circuits.
It may be a bipolar integrated circuit such as an (emitter coupled logic) circuit.

The selector may use the switch as described above, or may form a wiring by the master slice method so as to transmit only a desired delayed signal. The control signal may be supplied from the external terminal to select one. When the external terminal is provided in this way, the user can set the pulse duty of the internal pulse. INDUSTRIAL APPLICABILITY The present invention can be widely used for semiconductor integrated circuit devices having a pulse generation circuit built therein.

[0027]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a PLL circuit including a ring oscillator including odd-numbered stages of delay circuits each having a CMOS inverter circuit supplied with an operating current corresponding to a control voltage as one delay circuit, each delay signal of the ring oscillator has a timing corresponding to the number of stages. By utilizing the difference, the output signal of each delay circuit is selectively output by the selector, and the internal pulse signal having the desired duty is formed by logical processing with the oscillation output of the ring oscillator. The configuration makes it possible to obtain an output pulse that maintains a desired duty without being affected by the frequency.

[Brief description of drawings]

FIG. 1 is a circuit diagram of essential parts showing an embodiment of a clock generation circuit according to the present invention.

FIG. 2 is a timing chart for explaining an example of the operation of the clock generation circuit of FIG.

FIG. 3 is an overall circuit diagram showing an embodiment of a clock generation circuit according to the present invention.

[Explanation of symbols]

9 ... VCO circuit, 11 ... Select, 12 ... CMOS inverter circuit, 13 ... NAND gate circuit, 14 ... NOR gate circuit, Q1-Q7 ... MOSFET, N1-N3 ... Inverter circuit, F ... Fuse, S ... Selection signal.

Claims (3)

[Claims] 1. A PLL circuit including a ring oscillator composed of odd-numbered delay circuits with a CMOS inverter circuit to which an operating current corresponding to a control voltage is supplied as one delay circuit, and an output signal of each delay circuit is selectively selected. And a logic circuit that receives the output signal of the selector and the oscillation output of the ring oscillator, and has a built-in pulse generation circuit that forms an internal pulse signal with a desired duty by the logic circuit. A semiconductor integrated circuit device characterized by the following. 2. The P-channel type M in which the CMOS inverter circuit is adapted to flow a current corresponding to a control voltage.
The operating current is supplied through an OSFET and an N-channel MOSFET.
Semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein the selector selects a desired output signal of the delay circuit according to a selection signal formed by a programmable element.