JPH09232378A - Semiconductor chip mounting structure - Google Patents
Semiconductor chip mounting structureInfo
- Publication number
- JPH09232378A JPH09232378A JP8065395A JP6539596A JPH09232378A JP H09232378 A JPH09232378 A JP H09232378A JP 8065395 A JP8065395 A JP 8065395A JP 6539596 A JP6539596 A JP 6539596A JP H09232378 A JPH09232378 A JP H09232378A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- insulating substrate
- conductive
- semiconductor
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体チップを絶縁
性基板に搭載するための構造、特に複数の半導体チップ
を絶縁性基板に搭載するための構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for mounting a semiconductor chip on an insulating substrate, and more particularly to a structure for mounting a plurality of semiconductor chips on an insulating substrate.
【０００２】[0002]
【従来の技術】従来、半導体チップを絶縁性基板に搭載
する構造としては、例えば図５の断面図に示すような構
造が一般的に用いられている。同図に於いて１は半導体
チップであって絶縁性の接着剤２によって絶縁性基板３
にその底面を固定している。前記絶縁性基板３には外部
接続用の導電性パターン４、５が設けてあり、該導電性
パターン４、５と前記半導体チップ１上面の外部端子
（図示せず）とは導電性ワイヤー６、７によって夫々電
気的に接続している。更に、前記半導体チップ１の外部
端子の酸化防止、導電性ワイヤー６、７の変形または切
断等を防止することを目的として、半導体チップ１及び
導電性ワイヤー６、７を絶縁性の樹脂８により覆う構造
となっている。2. Description of the Related Art Conventionally, as a structure for mounting a semiconductor chip on an insulating substrate, for example, a structure as shown in a sectional view of FIG. 5 is generally used. In the figure, 1 is a semiconductor chip, and an insulating substrate 3 is provided with an insulating adhesive 2.
The bottom is fixed to. Conductive patterns 4, 5 for external connection are provided on the insulating substrate 3, and the conductive patterns 4, 5 and the external terminals (not shown) on the upper surface of the semiconductor chip 1 are electrically conductive wires 6, 7 are electrically connected to each other. Further, the semiconductor chip 1 and the conductive wires 6 and 7 are covered with an insulating resin 8 for the purpose of preventing the external terminals of the semiconductor chip 1 from being oxidized and preventing the conductive wires 6 and 7 from being deformed or cut. It has a structure.
【０００３】また図５に示したような半導体チップ搭載
の構造とは異なる、例えば図６に示すような半導体チッ
プの搭載構造が提案されている。同図に於いては、半導
体チップ１の外部端子（図示せず）に、導電性突起物
９、１０を形成しておき、それらを絶縁性基板３の表面
に設けた導電性パターン４、５に、例えばはんだ付け、
熱圧着、或いは溶融する等の手段によって、電気的接続
すると共に機械的保持している。更に、必要に応じて半
導体チップ１と絶縁性基板３との間に絶縁性の樹脂８を
充填しており、この樹脂８は半導体チップ１と絶縁性基
板３との機械的接続を強固なものとするよう作用する。
即ち、半導体チップ１及び絶縁性基板３の周囲の温度が
変化した場合、前記半導体チップ１と絶縁性基板３との
熱膨張係数の違いから前記導電性突起物９、１０に歪み
が発生することとなるが、樹脂８を備えることによって
前記歪みを緩和するという効果がある。また樹脂８を充
填する事により水分の侵入を防止し、前記半導体チップ
１の外部端子（一般にアルミニウムで構成されている）
の腐食を防ぐという効果も有している。Further, there has been proposed a semiconductor chip mounting structure, for example, as shown in FIG. 6, which is different from the semiconductor chip mounting structure as shown in FIG. In the figure, conductive projections 9 and 10 are formed on the external terminals (not shown) of the semiconductor chip 1 and the conductive patterns 4 and 5 are provided on the surface of the insulating substrate 3. For example, soldering,
They are electrically connected and mechanically held by means such as thermocompression bonding or melting. Furthermore, an insulating resin 8 is filled between the semiconductor chip 1 and the insulating substrate 3 as needed, and this resin 8 ensures a strong mechanical connection between the semiconductor chip 1 and the insulating substrate 3. To act.
That is, when the temperature around the semiconductor chip 1 and the insulating substrate 3 changes, the conductive protrusions 9 and 10 are distorted due to the difference in the coefficient of thermal expansion between the semiconductor chip 1 and the insulating substrate 3. However, the provision of the resin 8 has an effect of relaxing the strain. Further, the resin 8 is filled to prevent moisture from entering, and the external terminals of the semiconductor chip 1 (generally made of aluminum)
It also has the effect of preventing corrosion.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、図５或
いは図６に示した従来の構造によって複数の半導体チッ
プを絶縁性基板に搭載する際、図７（ａ）、（ｂ）に示
すように半導体チップが占有する面積はその搭載する数
に比例し、その数が多くなるほど絶縁性基板に広い実装
面積が必要になるという欠点があった。従って、近年各
種電子機器の小型化が要求されているのに対して、従来
の半導体チップ搭載の構造では実装面積の小面積化に限
界があるという欠点があった。However, when a plurality of semiconductor chips are mounted on an insulating substrate by the conventional structure shown in FIG. 5 or FIG. 6, as shown in FIGS. The area occupied by the chips is proportional to the number of mounted chips, and the larger the number, the larger the mounting area required for the insulating substrate. Therefore, in recent years, various electronic devices have been required to be downsized, but the conventional semiconductor chip mounting structure has a drawback in that there is a limit in reducing the mounting area.
【０００５】本発明は上述した如き半導体チップを絶縁
性基板に搭載する構造が有する欠点を除去する為になさ
れたものであって、複数の半導体チップが絶縁性基板を
占有する面積を狭くする構造を提供することを目的とす
る。The present invention has been made to eliminate the drawbacks of the structure in which a semiconductor chip is mounted on an insulating substrate as described above, and has a structure in which the area occupied by a plurality of semiconductor chips on the insulating substrate is narrowed. The purpose is to provide.
【０００６】[0006]
【課題を解決するための手段】上述の目的を達成するた
め本発明に係わる半導体チップの搭載法は、絶縁性基板
の表面に形成された導電性パターンと、半導体チップの
外部端子に形成された導電性突起物とを電気的に導通す
るように接合した半導体チップ部品に於いて、前記半導
体チップ上面に新たに半導体チップを接着剤にて固定
し、導電性ワイヤーにて、絶縁性基板表面に形成された
導電パターンと、新たに設置した半導体チップ外部端子
とを電気的に導通するように接続する事を特徴としたも
のである。In order to achieve the above-mentioned object, a semiconductor chip mounting method according to the present invention comprises a conductive pattern formed on the surface of an insulating substrate and external terminals of the semiconductor chip. In a semiconductor chip component joined to a conductive protrusion so as to be electrically conductive, a semiconductor chip is newly fixed to the upper surface of the semiconductor chip with an adhesive, and a conductive wire is applied to the surface of the insulating substrate. It is characterized in that the formed conductive pattern and the newly installed semiconductor chip external terminal are electrically connected to each other.
【０００７】[0007]
【発明の実施の形態】以下、本発明を実施の形態例を示
す図面に基づいて詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings showing an embodiment.
【０００８】図１、図２、図３は夫々本発明に係わる複
数の半導体チップを絶縁性基板に搭載する構造の一形態
例を示す、外観斜視図、上面図、Ａ−Ａ’断面図であっ
て、複数の半導体チップを積層とし、それを絶縁性基板
に搭載する構造を示したものである。FIGS. 1, 2, and 3 are an external perspective view, a top view, and a sectional view taken along the line AA 'showing an example of a structure in which a plurality of semiconductor chips according to the present invention are mounted on an insulating substrate. That is, a structure in which a plurality of semiconductor chips are stacked and mounted on an insulating substrate is shown.
【０００９】即ち、第１の半導体チップ１はその外部端
子（図示せず）に例えば半田、金等の金属からなる導電
性突起物９、１０を設けるとともに、半導体チップ１の
外部端子を設けた面と絶縁性基板３の導電パターン４、
５を設けた面を対向させ、更に導電性突起物９、１０と
導電パターン４、５とを電気的に接続することによっ
て、半導体チップ１を絶縁性基板３に機械的に保持する
構造としている。That is, the first semiconductor chip 1 is provided with the external terminals (not shown) of the semiconductor chip 1 as well as the conductive protrusions 9 and 10 made of a metal such as solder or gold. Surface and the conductive pattern 4 of the insulating substrate 3,
The semiconductor chip 1 is mechanically held on the insulating substrate 3 by making the surfaces provided with 5 face each other and electrically connecting the conductive protrusions 9 and 10 to the conductive patterns 4 and 5. .
【００１０】更に、前記半導体チップ１の外部端子を設
けていない面に、例えばディスペンサー等を用いて絶縁
性の接着剤２を塗布した後、第２の半導体チップ１１を
固定する。尚、その半導体チップ１１と前記半導体チッ
プ１とは外部端子を設けていない面同士が対向するよう
に固定する。その後、前記半導体チップ１１上面に設け
ている外部端子１４、１４、……と絶縁性基板上に形成
した導電パターン１２、１３とを、例えば金、銀、銅、
アルミニウム等の導電性ワイヤー６、７によって電気的
に接続するよう構成したものである。Further, after the insulating adhesive 2 is applied to the surface of the semiconductor chip 1 on which the external terminals are not provided by using, for example, a dispenser, the second semiconductor chip 11 is fixed. The semiconductor chip 11 and the semiconductor chip 1 are fixed so that the surfaces on which external terminals are not provided face each other. After that, the external terminals 14, 14, ... Provided on the upper surface of the semiconductor chip 11 and the conductive patterns 12, 13 formed on the insulating substrate are, for example, gold, silver, copper,
It is configured to be electrically connected by the conductive wires 6 and 7 such as aluminum.
【００１１】前述のように構成することによって、複数
の半導体チップを絶縁性基板に搭載する際に、その複数
の半導体チップが占める実装面積を狭く構成することが
できる。With the above-mentioned configuration, when mounting a plurality of semiconductor chips on the insulating substrate, the mounting area occupied by the plurality of semiconductor chips can be reduced.
【００１２】尚、前記の構造において、導電性突起物
９、１０と導電パターン４、５との接合方法は、当該導
電性突起物９、１０を例えば半田で構成した場合は熱圧
着或いは溶融して接続する方法とし、金属で構成した場
合は熱圧着または導電性接着剤を介して接続する方法が
一般的である。また、前記導電性ワイヤー６、７と半導
体チップ１１の外部端子または導電性パターン４、５と
の接続は、ワイヤーボンダー等を用いて行えばよい。In the above structure, the method of joining the conductive protrusions 9 and 10 with the conductive patterns 4 and 5 is such that when the conductive protrusions 9 and 10 are made of, for example, solder, thermocompression bonding or melting is performed. In the case of metal, a general method is thermocompression bonding or a conductive adhesive. The conductive wires 6 and 7 may be connected to the external terminals of the semiconductor chip 11 or the conductive patterns 4 and 5 using a wire bonder or the like.
【００１３】図４は、更に半導体チップ１、１１と絶縁
性基板との機械的保持を強固とする、或いは前記半導体
チップ１１の外部端子の酸化防止、または導電性ワイヤ
ー６、７の変形または切断等を防止すること等を目的と
した形態例であり、ディスペンサ装置等を用いて半導体
チップ１１上方側面、また半導体チップ１と絶縁性基板
３との隙間に絶縁性の樹脂８を適量適下充填し、前記半
導体チップ１、１１を覆う構造としたものである。In FIG. 4, the mechanical holding between the semiconductor chips 1 and 11 and the insulating substrate is further strengthened, the external terminals of the semiconductor chip 11 are prevented from being oxidized, or the conductive wires 6 and 7 are deformed or cut. This is an example of a form for the purpose of preventing the above problems, and an appropriate amount of the insulating resin 8 is appropriately filled in the upper side surface of the semiconductor chip 11 and the gap between the semiconductor chip 1 and the insulating substrate 3 by using a dispenser device or the like. However, the semiconductor chips 1 and 11 are covered with the structure.
【００１４】また、半導体チップ１、１１の外部電極と
絶縁性基板３上の導電性パターン４、５、１２、１３と
を夫々電気的に接続した後、樹脂８で覆う構造として説
明したが、本発明はこれに限定されるものではなく、半
導体チップ１を搭載した後、半導体チップ１と絶縁性基
板３との間を樹脂封止し、その後、半導体チップ１１を
搭載してから、該半導体チップ１１の外周を樹脂８で覆
うようにしてもよく、工程上任意の順番に於いて任意の
箇所に樹脂封止を実施したものであってもよい。Further, the structure has been described in which the external electrodes of the semiconductor chips 1 and 11 and the conductive patterns 4, 5, 12, and 13 on the insulating substrate 3 are electrically connected and then covered with the resin 8. The present invention is not limited to this, and after mounting the semiconductor chip 1, the semiconductor chip 1 and the insulating substrate 3 are resin-sealed, and then the semiconductor chip 11 is mounted, and then the semiconductor chip The outer periphery of the chip 11 may be covered with the resin 8, or the resin may be sealed in an arbitrary position in an arbitrary order in the process.
【００１５】尚、上記形態例において半導体チップを搭
載する基板を絶縁性基板として説明したが、具体的には
プリント基板、ＴＡＢテープ、セラミック基板、シリコ
ン基板、または半導体パッケージの母体基板等、表面に
導電性パターンが形成可能な絶縁性基板ならいかなる材
料であってもよいことは説明するまでもない。Although the substrate on which the semiconductor chip is mounted has been described as an insulating substrate in the above embodiment, specifically, it may be a printed circuit board, a TAB tape, a ceramic substrate, a silicon substrate, a base substrate of a semiconductor package, or the like. It goes without saying that any material may be used as long as it is an insulating substrate on which a conductive pattern can be formed.
【００１６】[0016]
【発明の効果】本発明は以上説明した如く構成するもの
であるから、複数の半導体チップを絶縁性基板に搭載す
る構造に於いて、絶縁性基板を占有する面積を狭くする
上で著しい効果を発揮する。Since the present invention is configured as described above, in a structure in which a plurality of semiconductor chips are mounted on an insulating substrate, a remarkable effect can be obtained in reducing the area occupied by the insulating substrate. Demonstrate.
【図１】本発明に係わる半導体チップを搭載した構造の
一形態例を示す外観斜視図FIG. 1 is an external perspective view showing an example of a structure in which a semiconductor chip according to the present invention is mounted.
【図２】本発明に係わる半導体チップを搭載した構造の
一形態例を示す上面図FIG. 2 is a top view showing an example of a structure in which a semiconductor chip according to the present invention is mounted.
【図３】本発明に係わる半導体チップを搭載した構造の
一形態例を示す断面図FIG. 3 is a cross-sectional view showing an example of a structure in which a semiconductor chip according to the present invention is mounted.
【図４】本発明に係わる半導体チップを搭載した構造の
一形態例を示す断面図FIG. 4 is a cross-sectional view showing an example of a structure in which a semiconductor chip according to the present invention is mounted.
【図５】従来の半導体チップを搭載した構造を示す断面
図FIG. 5 is a sectional view showing a structure in which a conventional semiconductor chip is mounted.
【図６】従来の半導体チップを搭載した構造を示す断面
図FIG. 6 is a sectional view showing a structure in which a conventional semiconductor chip is mounted.
【図７】（ａ）、（ｂ）は従来の半導体チップを複数個
搭載した構造を示す断面図7A and 7B are cross-sectional views showing a structure in which a plurality of conventional semiconductor chips are mounted.
１……半導体チップ ２……接着剤 ３……絶縁性基板 ４、５、１２、１３……導電性パターン ６、７……導電性ワイヤー ８……樹脂 ９、１０……導電性突起 １１……半導体チップ １４……外部端子 1 ... Semiconductor chip 2 ... Adhesive 3 ... Insulating substrate 4, 5, 12, 13 ... Conductive pattern 6, 7 ... Conductive wire 8 ... Resin 9, 10 ... Conductive protrusion 11 ... … Semiconductor chip 14 …… External terminals
Claims (1)
ーンと、半導体チップの外部端子に形成された導電性突
起物とを電気的に導通するように接合した半導体チップ
部品に於いて、前記半導体チップ上面に新たに半導体チ
ップを接着剤にて固定し、導電性ワイヤーにて、絶縁性
基板表面に形成された導電パターンと、新たに設置した
半導体チップ外部端子とを電気的に導通するように接続
する事を特徴とした半導体チップ搭載の構造。1. A semiconductor chip component in which a conductive pattern formed on a surface of an insulating substrate and a conductive protrusion formed on an external terminal of a semiconductor chip are joined so as to be electrically connected to each other. A semiconductor chip is newly fixed on the upper surface of the semiconductor chip with an adhesive, and a conductive wire electrically connects the conductive pattern formed on the surface of the insulating substrate to the newly installed external terminal of the semiconductor chip. A structure with a semiconductor chip, which is characterized by connecting like this.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8065395A JPH09232378A (en) | 1996-02-27 | 1996-02-27 | Semiconductor chip mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8065395A JPH09232378A (en) | 1996-02-27 | 1996-02-27 | Semiconductor chip mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09232378A true JPH09232378A (en) | 1997-09-05 |
Family
ID=13285788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8065395A Pending JPH09232378A (en) | 1996-02-27 | 1996-02-27 | Semiconductor chip mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09232378A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003124238A (en) * | 2001-10-12 | 2003-04-25 | Matsushita Electric Ind Co Ltd | Electronic part mounting device and electronic part mounting method |
-
1996
- 1996-02-27 JP JP8065395A patent/JPH09232378A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003124238A (en) * | 2001-10-12 | 2003-04-25 | Matsushita Electric Ind Co Ltd | Electronic part mounting device and electronic part mounting method |
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