JPH09213800A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and manufacture thereof in which an interlayer insulating film having a sufficient stress relaxation effect is obtained without complicating the process. SOLUTION: An aluminum film 21 is formed, and a mask pattern 23, comprising a plasma silicon oxide film 19 having a compressive stress, is formed on the aluminum film 21. Then, the aluminum film 21 is etched using the mask pattern 23 to form an aluminum wiring 18. Next, an O3 -TEOS oxide film 20 having a tensile stress is formed in a state where the mask pattern 23 remains to form a buried layer 24 over the aluminum wiring 18 and the mask pattern 23. Finally, the surface of the buried layer 24 is smoothed in accordance with the CMP method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to an interlayer insulating film suitable for a multilayer wiring technique and a method for forming the same.

[0002]

2. Description of the Related Art In a conventional semiconductor device having multi-layer wiring, for example, after forming a lower aluminum wiring,
Chemical vapor deposition (Chemical Vapor Deposit) on this wiring
There is known a structure in which a silicon oxide film is formed by an ion (hereinafter, referred to as CVD) method, and then an upper aluminum wiring is formed.

Further, as shown in FIG. 3A, a first silicon oxide film 4 is formed on a lower aluminum wiring 3 formed on a silicon substrate 1 with an insulating film 2 interposed therebetween, and thereafter,
As shown in Fig. 3 (b), SOG (Spin On Glas
s) forming a film 5, and then, as shown in FIG.
A structure in which the second silicon oxide film 6 is formed is also known. In this case, after the SOG film 5 is formed, plasma etching is performed on the entire surface to form the SOG film 5 on the aluminum wiring 3.
Are removed, the first silicon oxide film 4, the SOG film 5,
A relatively flat interlayer insulating film made of the second silicon oxide film 6 can be formed.

As described above, the interlayer insulating film may be composed of a single film or a plurality of films, but the insulating film has either compressive stress or tensile stress inside. When the interlayer insulating film is formed of a single film, or when films of the same kind are laminated, there is a problem that the substrate warps and interferes with subsequent manufacturing steps. Further, if the films are laminated in many layers, a large stress may be applied to the semiconductor substrate and the aluminum wiring to break the aluminum wiring, which may cause a defect such as so-called stress migration.

Therefore, as a means for solving this problem,
A structure in which an insulating film having a compressive stress and an insulating film having a tensile stress are alternately laminated (see JP-A-57-45931 and JP-A-5-109909), or an insulating layer having a tensile stress in a lower wiring. A structure has been proposed in which a side wall made of a film is provided and an insulating film having a compressive stress is formed on the side wall (see Japanese Patent Laid-Open No. 64-57645).

Among the above-mentioned means for solving the problems, for example, a method in which a lower layer wiring is provided with a side wall generally adopts the following manufacturing method. First, as shown in FIG. 4A, after forming an insulating film 9 on a silicon substrate 8, an aluminum layer 10 having a film thickness of 0.5 μm to be a lower layer wiring is formed, and etching is performed using the resist pattern 11 as a mask. By doing so, the aluminum wiring 12 is formed. Then, FIG.
As shown in FIG. 3, a silicon oxide film 13 having a film thickness of 0.5 μm is formed on the entire surface by using the plasma CVD method, and then CF ₄ is formed.
By anisotropically etching the entire surface in a system gas plasma, as shown in FIG. 4C, the silicon oxide film 13a is left only on the side wall of the aluminum wiring 12. Thereafter, as shown in FIG. 4D, an ozone-tetraethoxysilane (hereinafter referred to as O ₃ -TEOS) oxide film 14 having a film thickness of 1.0 μm is formed on the entire surface by the atmospheric pressure CVD method.

[0007] According to the present method, a plasma silicon oxide film 13a which is provided on the side wall of the aluminum wiring 12 has a compressive stress, O ₃ -TEOS provided between the wiring 12 and the wiring
Since the oxide film 14 has tensile stress, both stresses are canceled out, and the stress of the entire substrate can be relaxed.

[0008]

However, the above-mentioned 2)
Of the two methods, in the method of laminating a film having compressive stress and a film having tensile stress, it is necessary to use different film forming processes multiple times to laminate different kinds of insulating films. Since it is determined from the viewpoint of relaxation, there is a problem that planarization, which is an important factor as an interlayer insulating film, is difficult. On the other hand, in the method of providing the side wall made of an insulating film on the wiring, the effect of stress relaxation is extremely small because the side wall exists only in the vicinity of the wiring, and a sufficient stress relaxation effect cannot be obtained for the entire substrate. was there.

The present invention has been made to solve the above-mentioned problems, and does not complicate the process.
An object of the present invention is to provide a semiconductor device in which an interlayer insulating film having a sufficient stress relaxation effect can be obtained and a manufacturing method thereof.

[0010]

In order to achieve the above object, in a semiconductor device of the present invention, a first insulating film having a compressive stress or a tensile stress is formed directly on a wiring, The wiring and the first insulating film are filled with a second insulating film having a stress opposite to the above stress.

Further, a method of manufacturing a semiconductor device according to the present invention
A step of forming a wiring layer, a step of forming a mask material pattern made of a first insulating film having a stress of either compressive stress or tensile stress on the wiring layer, and etching the wiring layer using the mask material pattern as a mask Forming a wiring and a second insulating film having a stress opposite to the above stress with the mask material pattern left, and forming a buried layer for embedding the wiring and the mask material pattern. It is characterized by having. Furthermore, after forming the buried layer, the surface of the buried layer may be flattened. As a specific material for the above film, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film formed by a plasma CVD method is used as an insulating film having compressive stress, and an insulating film having tensile stress is used. A silicon oxide film formed by a low pressure CVD method can be used.

Further, the magnitude of the stress is not uniformly determined by the kind of the film, and for example, a silicon oxide film formed by atmospheric pressure CVD method in an O ₃ -TEOS atmosphere is used as the insulating film having tensile stress. Then, by controlling the gas flow rate during the growth of the silicon oxide film or by using the silicon oxide film by the sputtering method as the insulating film having the compressive stress, the substrate bias during the growth of the silicon oxide film can be controlled. It is also possible to adjust the magnitude of tensile stress and compressive stress.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a process flow diagram sequentially showing a method of manufacturing a semiconductor device of the present embodiment, particularly a step of forming an interlayer insulating film on a lower layer wiring.

As shown in FIG. 1D, in the semiconductor device of this embodiment, an insulating film 17 is formed on a silicon substrate 16, and an aluminum wiring 18 which is a lower layer wiring is formed on the insulating film 17.
(Wiring) is formed. Then, the plasma silicon oxide film 19 (first insulating film) having a compressive stress is formed only directly on the aluminum wiring 18, and these wirings 18 are formed.
Also, the plasma silicon oxide film 19 is filled with the O ₃ -TEOS oxide film 20 (second insulating film) having tensile stress. Then, the surface of the O ₃ -TEO is flattened
An upper wiring (not shown) is provided on the S oxide film 20.

That is, the plasma silicon oxide film 19 and the O ₃ -TEOS oxide film 20 form an interlayer insulating film between the upper layer wiring and the lower layer wiring.
These two types of oxide films are divided into a region on the aluminum wiring 18 and a region other than the region.

Next, a method of manufacturing the semiconductor device having the above structure will be described. First, as shown in FIG. 1A, an aluminum film 21 (wiring layer) having a film thickness of 0.5 μm is formed on the entire surface of the insulating film 17 formed on the silicon substrate 16. Then, a plasma silicon oxide film 19 having a film thickness of 1.5 μm, which becomes a mask material when the aluminum film 21 is etched later, is formed by using the plasma CVD method.
At this time, as the film thickness of the plasma silicon oxide film 19,
It is necessary to set the film thickness such that the resist pattern used during patterning can withstand plasma etching. Also,
In order to fully exert the stress relaxation effect in the present embodiment, a film thickness of at least about 1.0 μm is necessary. From the above, the normal film thickness is 1.0 to 2.0 μm.
It is desirable to be about.

After that, a resist pattern 22 is formed by photolithography, and CF is used as a mask.
Plasma etching of the plasma silicon oxide film 19 is carried out in a _4- system gas plasma to form a mask material pattern 23 during etching of the aluminum film.

Further, as shown in FIG. 1B, after removing the resist pattern 22, plasma etching of the aluminum film 21 using the mask material pattern 23 as a mask is performed to form an aluminum wiring 18.

Next, as shown in FIG. 1C, O ₃ -T
A silicon oxide film 20 is formed by an atmospheric pressure CVD method in an EOS atmosphere, and a buried layer 24 is formed. At this time, O ₃ −
The film thickness of the TEOS oxide film 20 needs to be set so as to sufficiently fill the groove 25 formed between the wirings 18. In the case of the present embodiment, the film thickness of the aluminum wiring 18 is 0.5 μm and the film thickness of the mask material pattern 23 is 1.5 μm.
Since the groove 25 has a depth of about 2.0 μm because of the thickness m, the thickness of the O ₃ -TEOS oxide film 20 is 2.5 μm.
Set to about m. Further, the groove 25 between the wirings 18 is almost completely filled by using the O ₃ -TEOS oxide film 20.

Then, as shown in FIG. 1D, chemical mechanical polishing (hereinafter, referred to as C).
O) on the aluminum wiring 18 by using the (MP) method.
_{The surface of the 3-} TEOS oxide film 20 is flattened by etching until there is no protrusion. At this time, since the film thickness of the O ₃ -TEOS oxide film 20 on the wiring 18 is estimated to be about 1.5 μm, it is necessary to remove at least this amount. After the CMP, the aluminum wiring 18
The upper plasma silicon oxide film 19 may or may not be exposed.

After that, an opening is provided at a predetermined position and an upper layer wiring (not shown) is formed, thereby completing the interlayer insulating film forming process between the wirings.

In the method of manufacturing the semiconductor device of the present embodiment, the plasma silicon oxide film 19 used as the mask material pattern 23 at the time of forming the aluminum wiring 18 has a compressive stress, and the O ₃ used as the embedding layer 24 is used. Since the TEOS oxide film 20 has tensile stress, both stresses are canceled out, the stress of the entire substrate can be relaxed, and problems such as substrate warpage and disconnection of the aluminum wiring 18 can be prevented. it can. In particular, since the O ₃ -TEOS oxide film 20 can adjust the degree of tensile stress by adjusting the gas flow rate during its growth, the stress relaxation effect of the entire substrate can be optimized, and the buried layer It is suitable for use as 24.

In particular, according to this method, the plasma silicon oxide film 19 having compressive stress is formed by the thickness of the interlayer film, and compared with the conventional method in which the plasma silicon oxide film is provided only on the side wall of the aluminum wiring. Further, since the volume occupied by the plasma silicon oxide film 19 becomes large, it is possible to obtain a special effect that the stress relaxation effect becomes larger than the conventional one. The plasma silicon oxide film 19 is used as the mask material pattern 2 when the aluminum film 18 is etched.
Since it is used as No. 3, it is not purposely formed only for the purpose of stress relaxation, and it can be a rational method that is not complicated as compared with the conventional process.

Furthermore, by using the O ₃ -TEOS oxide film 20 in the buried layer 24, the groove 25 between the wirings 18 can be effectively buried, and an interlayer insulating film without voids can be formed. Further, since the flattening by CMP is performed after the O ₃ -TEOS oxide film 20 is formed, the upper wiring can be easily formed.

In this embodiment, the plasma silicon oxide film is used as the material of the mask material. However, the material is not limited to this, and a plasma silicon nitride film, a plasma silicon oxynitride film, or the like has a compressive stress. Any film may be used. Further, as a material for the buried layer, O ₃ -TEO is used.
Although the S oxide film is used, other film having a tensile stress such as a CVD-PSG film may be used instead of the S oxide film.

Furthermore, the combination of the mask material and the burying layer is not limited to the present embodiment, and any combination of a film having a compressive stress and a film having a tensile stress may be used. It is necessary to select this combination in consideration of the ratio of the area occupied by the wiring portion to the area of the entire substrate. Therefore, in some cases, it is necessary to form a dummy wiring pattern having no circuit-like connection in a region other than the wiring region to adjust the area.

Further, as a material of the aluminum wiring of the present embodiment, aluminum may contain impurities such as copper and silicon. Further, it may be a film having a laminated structure containing a refractory metal such as titanium or a refractory metal nitride.

The second embodiment of the present invention will be described below with reference to FIG. FIG. 2 is a process flow diagram sequentially showing a method of manufacturing a semiconductor device of the present embodiment, particularly a step of forming an interlayer insulating film on a lower wiring. In the present embodiment, copper is used as a wiring material, and low pressure CVD (Low Pressure-CVD, hereinafter, LP-C) is used as a mask material at the time of wiring formation.
This is different from the first embodiment in that a silicon oxide film formed by the VD method) is used and that a silicon oxide film formed by sputtering is used as a buried layer.

It is known that the silicon oxide film formed by the LP-CVD method has a tensile stress, and the silicon oxide film formed by sputtering has a compressive stress.

First, as shown in FIG. 2A, a Cu (copper) film 27 (wiring layer) having a film thickness of 0.5 μm is formed on the entire surface of the insulating film 17 formed on the silicon substrate 16. .
Since the Cu film 27 has a melting point of about 1065 to 1083 ° C., it has sufficient heat resistance to withstand the subsequent LP-CVD process. Then, a silicon oxide film 28 (first insulating film) having a film thickness of 1.5 μm, which serves as a mask material during etching of the Cu film, is formed by the LP-CVD method. After that, a resist pattern 22 is formed by the photolithography technique, and the LP-CVD oxide film 28 is plasma-etched using this as a mask to form a mask material pattern 29.

Then, as shown in FIG. 2B, after the resist pattern 22 is removed, the lower Cu film 27 is plasma-etched in Cl ₂ gas by using the mask material pattern 29 as a mask, whereby the Cu wiring 30 is formed. (Wiring) is formed.

Next, as shown in FIG. 2C, a silicon oxide film 31 (second insulating film) is formed by a sputtering method.
To form a buried layer 32. When the sputtering method is used, the compressive stress in the silicon oxide film 31 can be gradually increased by changing the substrate bias from 0V to -200V. For example, when the substrate bias is −200V, the film stress (compression) is about 2 × 10.
Take a value of about ⁹ [dyne / cm ² ]. Therefore, in the present embodiment, the substrate bias is set to -200V, and the film thickness of the silicon oxide film 31 is set to about 2.0 μm.

After that, as in the first embodiment, FIG.
As shown in (d), the silicon oxide film 3 is formed by the CMP method.
The convex portion 1 is removed to flatten the surface. Then, by providing an opening at a predetermined position and forming an upper layer wiring,
The interlayer insulating film forming process between the wirings is completed.

In the present embodiment, in addition to the same effect as that of the first embodiment, by selecting an appropriate substrate bias when forming the silicon oxide film 31 by using the sputtering method, It is possible to control the compressive stress of the substrate to optimize the stress relaxation effect of the entire substrate, and as a result,
Problems such as warpage of the substrate and disconnection of the Cu wiring can be prevented. Further, by using the silicon oxide film 31 formed by the sputtering method, it is possible to form an interlayer insulating film having an excellent embedding property.

As the wiring material used in this embodiment, Cu may contain impurities.

[0036]

As described above in detail, according to the present invention, the first insulating film used as the mask material pattern at the time of forming the wiring has either compressive stress or tensile stress and is buried. Since the second insulating oxide film used as a layer has a stress opposite to that, both stresses are canceled out and the stress of the entire substrate can be relieved, causing problems such as substrate warpage and wiring disconnection. Can be prevented. At this time, the first insulating film is formed by the thickness of the interlayer film, and the insulating film occupies a larger volume than the conventional method in which the insulating film is provided only on the side wall of the wiring. A large stress relaxation effect can be obtained. Further, since the first insulating film is used as a mask material pattern at the time of etching for wiring formation, it is not purposely formed only for the purpose of stress relaxation, and the conventional process does not become complicated. Furthermore, when an O ₃ -TEOS oxide film or a silicon oxide film formed by a sputtering method is used as the material of the film, the stress in the film can be freely adjusted by controlling the film formation conditions, and the stress relaxation of the entire substrate Optimization can be achieved.

[Brief description of drawings]

FIG. 1 is a process flow chart showing a manufacturing process (interlayer insulating film forming process) of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process flow diagram showing manufacturing steps (interlayer insulating film forming step) of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process flow chart showing a conventional general interlayer insulating film forming step.

FIG. 4 is a process flow chart showing a conventional interlayer insulating film forming step in which an insulating film is provided on a wiring side wall.

[Explanation of symbols]

16 silicon substrate 17 insulating film 18 aluminum wiring (wiring) 19 plasma silicon oxide film (first insulating film) 20 O ₃ -TEOS oxide film (second insulating film) 21 aluminum film (wiring layer) 22 resist pattern 23, 29 Mask Material Pattern 24, 32 Buried Layer 25 Groove 27 Cu Film (Wiring Layer) 28 LP-CVD Oxide Film (First Insulating Film) 30 Cu Wiring (Wiring) 31 Silicon Oxide Film by Sputtering Method (Second Insulation) film)

Claims (6)

[Claims] 1. A first insulating film having a compressive stress or a tensile stress is formed immediately above a wiring, and the wiring and the first insulating film have a second stress having a stress opposite to the stress. A semiconductor device characterized by being filled with an insulating film. 2. A step of forming a wiring layer, and a first step of applying a compressive stress or a tensile stress on the wiring layer.
A step of forming a mask material pattern made of the insulating film of
A step of forming a wiring by etching the wiring layer using the mask material pattern as a mask; and a step of forming a second insulating film having a stress opposite to the stress with the mask material pattern left. A method of manufacturing a semiconductor device, comprising: a step of forming a buried layer in which wiring and a mask material pattern are embedded. 3. The method for manufacturing a semiconductor device according to claim 2, wherein after the buried layer made of the second insulating film is formed, the surface of the buried layer is flattened. Device manufacturing method. 4. The method for manufacturing a semiconductor device according to claim 2, wherein a silicon oxide film, a silicon nitride film, or a silicon oxynitride film formed by a plasma CVD method is used as the insulating film having the compressive stress. A method of manufacturing a semiconductor device, wherein a silicon oxide film formed by a low pressure CVD method is used as the insulating film having the tensile stress. 5. The method of manufacturing a semiconductor device according to claim 2, wherein a silicon oxide film formed by an atmospheric pressure CVD method in an ozone-tetraethoxysilane atmosphere is used as the insulating film having the tensile stress, A method for manufacturing a semiconductor device, wherein the magnitude of tensile stress is adjusted by controlling the gas flow rate during the growth of the silicon oxide film. 6. The method for manufacturing a semiconductor device according to claim 2, wherein a silicon oxide film formed by a sputtering method is used as the insulating film having the compressive stress, and a substrate bias during growth of the silicon oxide film is controlled. A method of manufacturing a semiconductor device, characterized in that the magnitude of the compressive stress is adjusted by performing the above.