JPH09200871A - Telemeter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the continuity of data outputted from an external device and to prevent analysis operation on the ground from being affected by a change in the period of a burst clock signal outputted from the external device by inserting a dummy frame when the period is changed. SOLUTION: A change in the output position of a burst clock signal 4 is detected by a dummy data control circuit 40. When the output of dummy data is requested to a frame editing circuit 6, the circuit 6 stops the edition of parallel digital data 19 and executes switching operation to the dummy data. As the result of the switching operation, dummy digital data 41 are outputted from a 4th selector circuit 35 to a 1st selector circuit 10. The circuit 10 outputs measurement data 21 based upon the data 41 and A/D conversion data 9. The data 21 and synchronizing pattern data are multiplexed by a 3rd selector circuit 24. The circuit 24 outputs a signal 26 to a P/S conversion circuit 27. The signal 26 is converted into serial data and a regulated frame format is formed and outputted as an output signal 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention collects and edits analog data and digital data mixedly,
The present invention relates to a telemeter device mounted on a spacecraft for the purpose of sending data to a ground device or the like.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram of a conventional telemeter device, which will be described as two kinds of analog signals and digital signals input from an external device. In the plurality of analog signals input from the external device, 1 is a signal defining the plurality of analog signals. In the digital signal input from the external device, 2 is a clock signal continuously input, 3 is a parallel data signal input in bursts, 4 is the parallel data signal 3
It is a burst clock signal input in synchronization with.
It is assumed that the parallel data signal 3, clock signal 2 and burst clock signal 4 are temporally in a synchronous relationship.

A plurality of analog signals 1 input from an external device are input to an analog multiplexer 5 and multiplexed by a first control signal 7 of a frame editing circuit 6. The multiplexed analog data is converted from analog data into parallel A / D converted data 9 by the A / D conversion circuit 8 and output to the first selector circuit 10.

The clock signal 2, the parallel data signal 3 and the burst clock signal 4 input from an external device are subjected to waveform shaping and level conversion in the receiver circuit 11 as necessary to operate the device. It becomes a signal for.

The burst detection circuit 12 detects the head of the data by the burst clock signal 4 and notifies the frame editing circuit 6 of the start of the data by a start signal 13. The start signal 13 determines the frame format reference position of the apparatus. Further, the start signal 13 is sent to the write address control circuit 1
4 is notified, the write address control circuit 14 supplies address data via the second selector circuit 16 so that writing is performed at a predetermined address of the memory circuit 15. The frame editing circuit 6 outputs a second selection signal 17 to the second selector circuit 16 so that the address data is supplied to the memory circuit 15.

The frame editing circuit 6 outputs the read address signal 18 generated by the frame editing circuit 6 according to the second selection signal 17 to the memory circuit 15 via the second selector circuit 16 to complete the writing. The parallel data signal 3 is read to obtain parallel digital data 19. The frame editing circuit 6 includes the parallel digital data 19 and the A / D conversion circuit 8
Of the first selector circuit 10 in order to selectively control the parallel A / D conversion data 9 which is the output signal of
The selection signal 20 is output. As a result, the output signal of the first selector circuit 10 is the multiplexed measurement data 21.
Becomes

The frame editing circuit 6 outputs the third selection signal 25 to the third selector circuit 24 in order to multiplex the measurement data 21 and the synchronization pattern data 23 which is the output signal of the synchronization pattern generating circuit 22. Output. As a result, the third selector circuit 24 outputs the frame format parallel data 26 which is an output signal. The frame format parallel data 26 is P / S
It becomes the input signal of the conversion circuit 27 and the frame editing circuit 6 described above.
The second control signal 28 and the rate clock signal 29 for determining the rate of the transmission signal are converted into serial data, and the serial data becomes the output signal 30 of the present apparatus formed in the specified frame format.

If the output positions of the burst clock signal 4 and the parallel data signal 3 from the external device change, the structure of the frame format may collapse and the data cannot be transmitted in the specified format.

[0009]

A telemeter device mounted on a flying vehicle sequentially monitors a change in the state of an external device and sends the data as information to a device such as the ground, and on the ground, data for later analysis of the operation. It is a device for collection. Therefore, even if the external device operates outside the specified range, this device is not affected, and there is a problem that it is desired to continue to output the data output by the external device.

Since the device is mounted on a flying body, the additional function to be incorporated in addition to the necessary function is device scale,
There are restrictions on the mounting area.

The present invention has been made to solve the above problems, and when a burst clock signal output from an external device is monitored and is output at a position outside the specified range, a dummy frame or The purpose is to insert dummy data, ensure the continuity of the data output by the external device, and obtain a device that does not affect the analysis work on the ground device.

[0012]

The telemeter device according to the present invention starts the operation of the reference position detection circuit by a start signal generated by a burst clock signal from an external device, and always starts this operation at the head position of the frame format. By monitoring the signal, when the cycle of the burst clock signal from the external device changes, the control of the selector circuit is controlled in frame units, and it is possible to insert a dummy frame and not to transmit data in the specified format, This is to ensure the continuity of the data output by the external device.

The telemeter device according to the present invention is
Start the operation of the reference position detection circuit by the start signal generated by the burst clock signal from the external device,
By constantly monitoring this start signal at the beginning position of the frame format, when the cycle of the burst clock signal from the external device changes, dummy data is inserted instead of digital data as the control operation of the selector circuit in frame units. In this way, it is possible to ensure the continuity of the data output by the external device without preventing the data from being transmitted in the prescribed format.

The telemeter device 3 according to the present invention
Starts the operation of the reference position detection circuit by the start signal generated by the burst clock signal from the external device, and constantly monitors this start signal at the head position of the frame format, so that the burst clock signal from the external device When the cycle of is changed, the control of the selector circuit is controlled on a frame-by-frame basis, and dummy frames are inserted on a frame-by-frame basis to prevent data from being transmitted in the specified format, ensuring the continuity of the data output by the external device Even if the clock signal from an external device can be stopped, by switching to the internal clock signal by switching to the internal clock signal, multiple analog signals that are signals other than the signal edited by the burst clock can be edited and embedded in the specified format on the ground. It is to be transmitted.

The telemeter device according to the present invention is
Start the operation of the reference position detection circuit by the start signal generated by the burst clock signal from the external device,
By constantly monitoring this start signal at the beginning position of the frame format, when the cycle of the burst clock signal from the external device changes, dummy data is inserted instead of digital data as the control operation of the selector circuit in frame units. In this way, it is possible to maintain the continuity of the data output by the external device without interrupting the transmission of data in the specified format and bursting by switching to the internal clock signal even when the clock signal from the external device is stopped. This is to edit a plurality of analog signals, which are signals other than the signals edited by the clock, and incorporate them into a specified format and transmit them to the ground.

The telemeter device according to the present invention is
Start the operation of the reference position detection circuit by the start signal generated by the burst clock signal from the external device,
By constantly monitoring this start signal at the start position of the frame format, if the cycle of the burst clock signal from the external device changes, the control of the tri-state circuit is controlled on a frame-by-frame basis, and a dummy frame is inserted and specified. This is to ensure the continuity of the data output by the external device without preventing the data from being transmitted in the format.

The telemeter device according to the present invention is
Start the operation of the reference position detection circuit by the start signal generated by the burst clock signal from the external device,
By constantly monitoring this start signal at the beginning position of the frame format, if the cycle of the burst clock signal from the external device changes, dummy data is inserted instead of digital data as the control operation of the tri-state circuit in frame units. It is possible to ensure the continuity of the data output by the external device without preventing the data from being transmitted in the specified format.

Further, the telemeter device according to the present invention is
Start the operation of the reference position detection circuit by the start signal generated by the burst clock signal from the external device,
By constantly monitoring this start signal at the start position of the frame format, if the cycle of the burst clock signal from the external device changes, the control of the tri-state circuit is controlled in frame units and dummy frames are inserted in frame units. However, it is possible to maintain the continuity of the data output by the external device without stopping the data transmission in the specified format, and even if the clock signal from the external device is stopped, it is possible to use the burst clock by switching to the internal clock signal. It is a signal that edits a plurality of analog signals other than the signal being edited and incorporates them into a specified format and transmits them to the ground.

The telemeter device according to the present invention is
Start the operation of the reference position detection circuit by the start signal generated by the burst clock signal from the external device,
By constantly monitoring this start signal at the beginning position of the frame format, if the cycle of the burst clock signal from the external device changes, dummy data is inserted instead of digital data as the control operation of the tri-state circuit in frame units. Control so that the data cannot be transmitted in the specified format, the continuity of the data output by the external device can be ensured, and even if the clock signal from the external device is stopped, by switching to the internal clock signal This is to edit a plurality of analog signals other than the signals edited by the burst clock, incorporate them into a specified format, and transmit them to the ground.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. 1 is a block diagram showing a first embodiment of the present invention. In the figure, 1 to 30 are the same as those of a conventional device.

In FIG. 1, a burst clock detection circuit 12 takes in a burst clock signal 4 and a clock signal from an external device, detects a start position of a burst, and outputs a start signal 13 to a frame editing circuit 6 as in the conventional device. The frame editing circuit 6 takes in the head information of the frame format from the start signal 13 and starts frame format generation. In this state, the timing of outputting the selection signal to each selector for editing the signal of the synchronization pattern data 23 indicating the head of the frame format of the apparatus, the A / D conversion data 9 and the parallel data signal 3 is determined. If a parallel data signal is input at the timing, the synchronization state is maintained and the same operation as the conventional device is performed.

The dummy frame control circuit 31 is provided to monitor the output position of the burst clock signal 4. When the output position of the burst clock signal 4 changes, whether the frame format similar to that of the conventional device can be constructed or not. Is a circuit for instructing the frame editing circuit 6 to output a dummy frame when it is determined that it is necessary to switch to the dummy frame. The identification code generation circuit 33 is a circuit provided for the purpose of allowing the receiving side to identify whether or not the output signal 30 of the present device is in a normal frame format, and it is an ordinary circuit at a specific position of the frame format. The data can be identified by using data different from that in the frame format. Dummy data generation circuit 3
Reference numeral 4 is a circuit for generating data to be inserted in place of the parallel A / D conversion data 9 and the parallel digital data 19 in the normal frame format, and generates fixed data whose content is not particularly specified.

The dummy frame control circuit 31 detects that the output position of the start signal 13 has changed, and outputs a flag signal 32 for requesting the frame editing circuit 6 to output a dummy frame. Upon receiving the flag signal 32, the frame editing circuit 6 stops the editing of the measurement data 21, which has been conventionally edited via the first selector circuit 10, and switches to the dummy frame. In order to output a dummy frame composed of fixed dummy data, the fourth selector circuit 35 selects the identification code 36 and the dummy data 37 which are the output signals of the identification code generation circuit 33 and the dummy data generation circuit 34. Selection signal 3
8 is output.

The dummy frame data 39 edited by the fourth selector circuit 35 is multiplexed with the sync pattern data 23 which is the output signal of the sync pattern generating circuit 22 instead of the measurement data 21, so that the third dummy frame data 39 is multiplexed. It is output to the selector circuit 24. The frame editing circuit 6 outputs a third selection signal 25 to the third selector circuit 24. As a result, the third selector circuit 24 outputs the frame format parallel data 26 which is an output signal. The frame format parallel data 26 becomes an input signal of the P / S conversion circuit 27 and the second control signal 2 of the frame editing circuit 6 is inputted.
8 and a rate clock signal 29 that determines the rate of the transmission signal, which is converted into serial data, which becomes the output signal 30 of the present apparatus formed in a prescribed frame format.

As a result, the output signal 30 of the apparatus automatically completes the switching operation to the dummy frame data 39. Further, in the dummy frame control circuit 31, since the output position of the burst clock signal 4 is constantly monitored, the control can be returned to the conventional editing operation if it is restored, and the ground equipment continues the normal receiving operation. can do.

Embodiment 2 FIG. 2 is a block diagram showing a second embodiment of the present invention. In FIG.
It is the same as the conventional device.

In FIG. 2, a burst clock detection circuit 12 takes in a burst clock signal 4 and a clock signal from an external device, detects the start position of the burst, and outputs a start signal 13 to the frame editing circuit 6 as in the conventional device. The frame editing circuit 6 takes in the head information of the frame format from the start signal 13 and starts frame format generation. In this state, the timing of outputting the selection signal to each selector for editing the signal of the synchronization pattern data 23 indicating the head of the frame format of the apparatus, the A / D conversion data 9 and the parallel data signal 3 is determined. If a parallel data signal is input at the timing, the synchronization state is maintained and the same operation as the conventional device is performed.

The dummy data control circuit 40 is provided to monitor the output position of the burst clock signal 4,
When the output position of the burst clock signal 4 changes, it is judged whether a frame format similar to that of the conventional apparatus can be constructed, and it is judged that it is necessary to switch to the dummy data instead of the parallel digital data 19 described above. 6 is a circuit for instructing 6 to output dummy data. The identification code generating circuit 33 outputs the output signal 3 of this device.
This is a circuit provided for the purpose of allowing the receiving device side to identify whether 0 is the normal frame format or not. By setting different data from the normal frame format at a specific position of the frame format, Can be identified. The dummy data generation circuit 34 is a circuit for generating data to be inserted in place of the parallel digital data 19 in the normal frame format, and generates fixed data whose data content is not particularly specified.

If the output position of the burst clock signal 4 changes, the dummy data control circuit 40 detects that the output position of the start signal 13 has changed and requests the frame editing circuit 6 to output dummy data. The signal 32 is output. Upon receiving the flag signal 32, the frame editing circuit 6 stops the editing of the parallel digital data 19 which is the output signal of the memory circuit 15 which is conventionally output via the fourth selector circuit 35, and stops the conversion to dummy data. Perform switching operation. In order to output dummy data composed of known dummy data, the fourth selector circuit 35 selects the identification code 36 and the dummy data 37 which are output signals of the identification code generation circuit 33 and the dummy data generation circuit 34. Output the selection signal 38 of. By this operation, the output signal of the fourth selector circuit 35 is the identification code 36 and the dummy data 37.
The dummy digital data 41 for which is selected is output to the first selector 10.

The first selector 10 measures the dummy digital data 41 edited by the fourth selector circuit 35 and the parallel A / D conversion data 9 converted by the A / D conversion circuit 8. Output as data 21. The measurement data 21 is the synchronization pattern generation circuit 22.
Is output to the third selector circuit 24 for multiplexing with the synchronization pattern data 23 which is the output signal of the.
The frame editing circuit 6 outputs a third selection signal 25 to the third selector circuit 24. As a result, the third selector circuit 24 outputs the frame format parallel data 26 which is an output signal. The frame format parallel data 26 becomes an input signal of the P / S conversion circuit 27 and is converted into serial data by the second control signal 28 of the frame editing circuit 6 and the rate clock signal 29 for determining the rate of the transmission signal.
The serial data becomes the output signal 30 of this device formed in a prescribed frame format.

As a result, the output signal 30 of the present apparatus automatically completes the switching operation to the dummy data. Further, in the dummy data control circuit 39, since the output position of the burst clock signal 4 is constantly monitored, the control can be returned to the conventional editing operation by returning, and the ground equipment continues the normal receiving operation. can do.

Embodiment 3. 3 is a block diagram showing a third embodiment of the present invention. In FIG. 3, 1 to 39 are:
This is the same as the first embodiment of the present invention.

The clock detection circuit 44 inputs the internal clock signal 43 from the oscillator 42 and monitors the clock signal 2 input from an external device. This clock signal 2
When the clock signal 2 is stopped or the period fluctuation deviates from the allowable range, the operation clock signal of the device is automatically switched to the internal clock signal 43 so that the operation of the device can be continued. I have to.

In FIG. 3, the oscillator 42 constantly supplies the internal clock signal 43 to the clock detection circuit 44. When the clock signal 2 is normally input in this state, the clock detection circuit 44 uses the external clock signal 2 as the internal operation clock signal 45.
To perform the conventional operation. Also, the clock signal 2
If the clock is stopped, the clock detection circuit 44 uses the internal operation clock signal 4 of the device in order to continue the operation of the device.
5, the internal clock signal 43 is controlled to be switched and the operation can be continued. When the clock signal 2 from the external device is restored, the clock detection circuit 44
The operation of returning the selected state of the internal clock signal 43 to the conventional selected state of the clock signal 2 is automatically performed.

Furthermore, even if the output position of the burst clock signal 4 changes, the operation described in the first embodiment of the present invention is not impaired.

Embodiment 4 FIG. FIG. 4 is a configuration diagram showing a fourth embodiment of the present invention. In FIG.
2 to 38, 40, 41 are the same as those in the second embodiment of the present invention.

In FIG. 4, the oscillator 42 constantly supplies the internal clock signal 43 to the clock detection circuit 44. When the clock signal 2 is normally input in this state, the clock detection circuit 44 uses the external clock signal 2 as the internal operation clock signal 45.
To perform the conventional operation. Also, the clock signal 2
If the clock is stopped, the clock detection circuit 44 uses the internal operation clock signal 4 of the device in order to continue the operation of the device.
5, the internal clock signal 43 is controlled to be switched and the operation can be continued. When the clock signal 2 from the external device is restored, the clock detection circuit 44
The operation of returning the selected state of the internal clock signal 43 to the conventional selected state of the clock signal 2 is automatically performed.

Furthermore, even if the output position of the burst clock signal 4 changes, the operation described in the second embodiment of the present invention is not impaired.

As a result, the output signal of this apparatus automatically completes the switching operation to the dummy frame data 39. Further, in the dummy frame control circuit 31, since the output position of the burst clock signal 4 is constantly monitored, the control can be returned to the conventional editing operation if it is restored, and the ground equipment continues the normal receiving operation. can do.

Embodiment 5. FIG. 5 is a configuration diagram showing a fifth embodiment of the present invention. In FIG.
To 15, 17 to 20, 22, 23, 25, 27 to 30 are the same as the conventional device.

In FIG. 5, the burst clock detection circuit 12 takes in the burst clock signal 4 and the clock signal from the external device, detects the start position of the burst, and outputs the start signal 13 to the frame editing circuit 6 as in the conventional device. The frame editing circuit 6 takes in the head information of the frame format from the start signal 13 and starts frame format generation. In this state, the data signal 3 parallel to the beginning of the frame format of this device
Is determined, and if a parallel data signal is input at this timing thereafter, the synchronization state is maintained and the editing operation is performed as in the conventional apparatus.

When editing the A / D conversion data 9, first
Control the first selection signal 20 in order to select the tri-state buffer 46, and when editing the data of the memory circuit 15, select the second tri-state buffer 47 to reverse the first selection signal 20. Control. As a result, the measurement data 21 is edited. Since the frame editing circuit 6 selects the third tri-state buffer 50,
The selection enable signal 49 controls the first enable 51 via the decoder circuit 48. The edit data 52 of the third tri-state buffer 50 selected by the fifth selection signal 49 is output to the fourth tri-state buffer 53. The fourth tri-state buffer 53 is
The synchronization pattern data 23 output via the fifth tri-state buffer 54 is multiplexed under the control of the third selection signal 25 to form frame format parallel data 26. The frame format parallel data 26
Becomes an input signal of the P / S conversion circuit 27, the parallel data is converted into serial data by the second control signal 28 of the frame editing circuit 6 and the rate clock signal 29 for determining the rate of the transmission signal, and the serial data is defined. The output signal 30 of the present apparatus is formed in the frame format.

If the output position of the burst clock signal 4 changes, the dummy frame control circuit 31 detects that the output position of the start signal 13 has changed, and requests the frame editing circuit 6 to output a dummy frame. The signal 32 is output. In the frame editing circuit 6 which has received the flag signal 32, the first tri-state buffer 46 and the second tri-state buffer 4 are
7. The editing of the measurement data 21 that has been edited via 7 is stopped, and the switching operation to the dummy frame is performed. In order to output a dummy frame composed of known dummy data, the second enable 55 via the decoder circuit 48 is controlled by the fifth selection signal 49 to select the identification code 36 via the sixth tri-state buffer 56. Next, the third enable 56 via the decoder circuit 48 is controlled by the fifth selection signal 49 to select the dummy data 37 via the seventh tri-state buffer 56 and output to the fourth tri-state buffer 53. The fourth tri-state buffer 53 is the fifth tri-state buffer 54.
The sync pattern data 23 output via the circuit is multiplexed under the control of the third selection signal 25 to form frame format parallel data 26. The frame format parallel data 26 becomes an input signal of the P / S conversion circuit 27, and a rate clock signal 29 for determining the rates of the second control signal 28 and the transmission signal of the frame editing circuit 6.
Thus, the parallel data forming the dummy frame is converted into serial data, and the serial data becomes the output signal 30 of the present apparatus formed in the prescribed frame format.

As a result, the output signal 30 of the apparatus is automatically switched to the dummy frame data 52. Further, in the dummy frame control circuit 31, since the output position of the burst clock signal 4 is constantly monitored, the control can be returned to the conventional editing operation if it is restored, and the ground equipment continues the normal receiving operation. can do.

Embodiment 6 FIG. 6 is a block diagram showing a sixth embodiment of the present invention. In FIG. 6, 1 to 9, 11 in FIG.
To 20, 21 to 23, and 25 to 30 are the same as the conventional device.

In FIG. 6, the burst clock detection circuit 12 takes in the burst clock signal 4 and the clock signal from the external device as in the conventional device, detects the start position of the burst, and outputs the start signal 13 to the frame editing circuit 6. The frame editing circuit 6 takes in the head information of the frame format from the start signal 13 and starts frame format generation. In this state, the data signal 3 parallel to the beginning of the frame format of this device
Is determined, and if a parallel data signal is input at this timing thereafter, the synchronization state is maintained and the same operation as the conventional device is performed.

When editing the data in the memory circuit 15, the first selection signal 49 causes the output signal of the decoder circuit 48 to select the third tri-state buffer 50.
Of the parallel digital data 19 is output as edit data 52 to the second tristate buffer 47 via the third tristate buffer 50. When editing the A / D conversion data 9, the first selection signal 20 is controlled to select the first tri-state buffer 46, and when editing the editing data 52, the second tri-state buffer 47 is selected. Therefore, the first selection signal 20 is controlled to the inverse logic. As a result, the measurement data 21 is edited. The frame editing circuit 6 multiplexes the sync pattern data 23 output via the fifth tri-state buffer 54 and the measurement data 21 under the control of the third selection signal 25 to form frame format parallel data 26. The frame format parallel data 26 becomes an input signal of the P / S conversion circuit 27, and a rate clock signal 29 for determining the rates of the second control signal 28 and the transmission signal of the frame editing circuit 6.
The parallel data is converted into serial data, and the serial data becomes the output signal 30 of the present apparatus formed in a prescribed frame format.

If the output position of the burst clock signal 4 changes, the dummy data control circuit 40 detects that the output position of the start signal 13 has changed, and requests the frame editing circuit 6 to output dummy data. The signal 32 is output. Upon receiving the flag signal 32, the frame editing circuit 6 stops editing the parallel digital data 19 which is the output signal of the memory circuit 15 output via the third tri-state buffer 50 and switches to dummy data. Take action. Fifth for outputting dummy data composed of known dummy data
Selection signal 49 for selecting the identification code 36 and the dummy data 37 which are the output signals of the identification code generating circuit 33 and the dummy data generating circuit 34, the second enable signal 55 to the decoder circuit 48 and the sixth tri-state buffer. At 56, the third enable signal 57 is output to the seventh tri-state buffer 58. By this operation, the identification code 36 and the dummy data 37 are provided as the edit data 52.
Is output as edit data 52 to the second tri-state buffer 47. When editing the A / D conversion data 9, the first selection signal 20 is controlled to select the first tri-state buffer 46, and the editing data 5
When editing 2, the second tri-state buffer 47
The first selection signal 20 is controlled to the inverse logic in order to select. As a result, the measurement data 21 is edited. The frame editing circuit 6 outputs the sync pattern data 23 and the measurement data 21 output via the fifth tri-state buffer 54.
Are multiplexed under the control of the third selection signal 25 to form frame format parallel data 26. The frame format parallel data 26 becomes an input signal of the P / S conversion circuit 27 and converts the parallel data into serial data by the second control signal 28 of the frame editing circuit 6 and the rate clock signal 29 which determines the rate of the transmission signal. Then, the serial data becomes the output signal 30 of the present apparatus formed in the specified frame format.

As a result, the output signal 30 of the present apparatus automatically completes the switching operation to the dummy data. Further, since the dummy data control circuit 40 constantly monitors the output position of the burst clock signal 4, if it is restored, the control can be returned to the conventional editing operation, and the ground device continues the normal receiving operation. can do.

Embodiment 7 FIG. 7 is a block diagram showing a seventh embodiment of the present invention. In FIG. 7, 1 to 9, 11 in FIG.
23 to 25, 34 to 36, 37, 39, 46 to 58 are the same as those in the fifth embodiment of the present invention.

In FIG. 7, the oscillator 42 constantly supplies the internal clock signal 43 to the clock detection circuit 44. When the clock signal 2 is normally input in this state, the clock detection circuit 44 uses the external clock signal 2 as the internal operation clock signal 45.
To perform the conventional operation. Also, the clock signal 2
If the clock is stopped, the clock detection circuit 44 uses the internal operation clock signal 4 of the device in order to continue the operation of the device.
5, the internal clock signal 43 is controlled to be switched and the operation can be continued. When the clock signal 2 from the external device is restored, the clock detection circuit 44
The operation of returning the selected state of the internal clock signal 43 to the conventional selected state of the clock signal 2 is automatically performed.

Furthermore, even if the output position of the burst clock signal 4 changes, the operation described in the fifth embodiment of the present invention is not impaired.

Embodiment 8 FIG. FIG. 8 is a configuration diagram showing an eighth embodiment of the present invention. In FIG.
From 23, 25 to 34, 36, 37, 46 to 58
Is the same as the sixth embodiment of the present invention.

In FIG. 8, the oscillator 42 constantly supplies the internal clock signal 43 to the clock detection circuit 44. When the clock signal 2 is normally input in this state, the clock detection circuit 44 uses the external clock signal 2 as the internal operation clock signal 45.
To perform the conventional operation. Also, the clock signal 2
If the clock is stopped, the clock detection circuit 44 uses the internal operation clock signal 4 of the device in order to continue the operation of the device.
5, the internal clock signal 43 is controlled to be switched and the operation can be continued. When the clock signal 2 from the external device is restored, the clock detection circuit 44
The operation of returning the selected state of the internal clock signal 43 to the conventional selected state of the clock signal 2 is automatically performed.

Furthermore, even if the output position of the burst clock signal 4 changes, the operation described in the sixth embodiment of the present invention is not impaired.

As a result, the output signal of this apparatus automatically completes the switching operation to the dummy frame data 39. Further, in the dummy frame control circuit 31, since the output position of the burst clock signal 4 is constantly monitored, the control can be returned to the conventional editing operation if it is restored, and the ground equipment continues the normal receiving operation. can do.

[0057]

According to the present invention, even if the cycle of a burst signal from an external device fluctuates in a device that multiplexes data and returns it to the ground, it is possible to correct the fluctuation value by detecting the fluctuation, and therefore, in frame units. It is possible to send a dummy frame and provide correct editing data to the ground equipment.

Further, according to the present invention, even if the cycle of the burst signal from the external device fluctuates in the device which multiplexes the data and sends it back to the ground, the fluctuation value is corrected by detecting the fluctuation and other than the analog signal. The dummy data can be transmitted in frame units to the above data, and correct editing data can be provided to the ground equipment.

According to the present invention, even if the cycle of the burst signal from the external device fluctuates in the device which multiplexes the data and returns it to the ground, the fluctuation value is corrected by detecting the fluctuation, so that the dummy frame is used for each frame. It is possible to send correct data to the ground device when the clock signal from the external device is lost and the dummy signal is automatically switched to the internal oscillator even when the clock signal from the external device is interrupted and the clock signal from the external device is restored. is there.

Further, according to the present invention, even if the cycle of the burst signal from the external device fluctuates in the device which multiplexes the data and returns it to the ground, the fluctuation value is corrected by detecting the fluctuation and other than the analog signal. It is possible to send dummy data in units of frame to the data of the above, and to automatically switch to the internal oscillator even when the clock signal from the external device is cut off. The correct editing data can be provided to the ground device when the clock signal is restored.

[Brief description of drawings]

FIG. 1 is a diagram showing a telemeter device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a telemeter device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a telemeter device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a telemeter device according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a telemeter device according to a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a telemeter device according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a telemeter device according to a seventh embodiment of the present invention.

FIG. 8 is a diagram showing a telemeter device according to an eighth embodiment of the present invention.

FIG. 9 is a diagram showing a conventional telemeter device.

[Explanation of symbols]

1 analog signal, 2 clock signal, 3 parallel data signal, 4 burst clock signal, 5 analog multiplexer, 6 frame editing circuit, 7 first control signal, 8 A / D conversion circuit, 9 A / D conversion data, 1
0 first selector circuit, 11 receiver circuit, 12
Burst detection circuit, 13 start signal, 14 write address control circuit, 15 memory circuit, 16 second selector circuit, 17 second selection signal, 18 read address signal, 19 parallel digital data, 20
First selection signal, 21 measurement data, 22 synchronization pattern generation circuit, 23 synchronization pattern data, 24 third selector circuit, 25 third selection signal, 24 frame format parallel data, 27 P / S conversion circuit,
28 second control signal, 29 rate clock signal, 3
0 output signal, 31 dummy frame control circuit, 32
Flag signal, 33 identification code generation circuit, 34 dummy data generation circuit, 35 fourth selector circuit, 36 identification code, 37 dummy data, 38 fourth selection signal, 39
Dummy frame data, 40 dummy data control circuit,
41 dummy digital data, 42 oscillator, 43 internal clock signal, 44 clock detection circuit, 45 internal operation clock signal, 46 first tri-state buffer, 47 second tri-state buffer, 48 decoder circuit, 49 fifth selection signal , 50 third tri-state buffer, 51 first enable, 52 edit data, 53 fourth tri-state buffer, 54
Fifth tristate buffer, 55 Second enable, 56 Sixth tristate buffer, 57 Third enable, 58 Seventh tristate buffer.

Claims (8)

[Claims] 1. An analog multiplexer for inputting an analog signal from an external device and time-division multiplexing, and a burst clock input with a continuous clock signal from another external device. Synchronizing with a parallel data signal and the parallel data signal. A receiver circuit for receiving a digital signal composed of a burst clock signal input by the following, a burst detection circuit for receiving the burst clock signal and outputting a start signal for determining a frame format reference position, and the clock A frame editing circuit that inputs a signal and the start signal to generate a frame format, and the start signal and the start signal of the frame format that are input to detect the deviation of the reference position and determine the dummy frame insertion on a frame-by-frame basis to edit the frame. Instruct the circuit to output a dummy frame A dummy frame control circuit, a write address control circuit for controlling generation of an address and a write enable signal to a memory circuit for writing the parallel data by the burst detection circuit, and the parallel data signal input in burst A memory circuit that temporarily stores and reads parallel data in accordance with a specified frame format, and a write / write operation of the memory circuit.
A second selector circuit for controlling the read address, an A / D conversion circuit for converting the output signal of the analog multiplexer from an analog to a digital signal, an output signal of the memory circuit and an output signal of the A / D conversion circuit. A first selector circuit selected by the control of the frame editing circuit, and an identification code generation for generating an identification code for identifying whether or not the dummy frame is a dummy frame when it is determined that the dummy frame is output by the control of the frame editing circuit. A circuit, a dummy data generation circuit for generating known dummy frame data for switching and outputting the output signal of the A / D conversion circuit and the output signal of the memory circuit during dummy frame, and the output of the first selector circuit Switch the signal to the output signal of the above identification code generation circuit and the output signal of the dummy data generation circuit A fourth selector circuit for performing a control, a sync pattern generation circuit for generating a sync pattern for indicating the leading data of the output of the telemeter device, a sync pattern data which is an output signal of the sync pattern generation circuit, and the fourth pattern. A third selector circuit that selects an output signal of the selector circuit to generate a prescribed frame format, and a P / S conversion circuit that converts the output signal of the third selector circuit from parallel data to serial data are provided. Telemeter device. 2. An analog multiplexer for inputting an analog signal from an external device and time-division multiplexing, and a continuous clock signal from another external device for burst input and synchronizing with a parallel data signal and the parallel data signal. A receiver circuit for receiving a digital signal composed of a burst clock signal input by the following, a burst detection circuit for receiving the burst clock signal and outputting a start signal for determining a frame format reference position, and the clock A frame editing circuit that inputs a signal and the start signal to generate a frame format, and the start signal and the start signal of the frame format that are input to detect the deviation of the reference position and judge the insertion of dummy data in frame units to edit the frame. Dummy that instructs the circuit to output dummy data -A data control circuit, a write address control circuit that controls the generation of an address and a write enable signal to a memory circuit for writing the parallel data by the burst detection circuit, and the parallel data signal that is input in bursts Circuit for accumulating and storing parallel data in accordance with a prescribed frame format, a second selector circuit for controlling the write / read address of the memory circuit, and converting the output signal of the analog multiplexer from analog to digital signal An A / D conversion circuit, an identification code generation circuit for generating an identification code for identifying whether or not the frame includes dummy data when it is determined to output dummy data under the control of the frame editing circuit, and a dummy Output of the above memory circuit during frame A dummy data generating circuit for generating known dummy data for switching and outputting signals, and a control for switching the output signal of the memory circuit between the output signal of the identification code generating circuit and the output signal of the dummy data generating circuit. 4 selector circuits, a first selector circuit for selecting the output signal of the A / D conversion circuit and the output signal of the fourth selector circuit under the control of the frame editing circuit, and for showing the leading data of the telemeter device output. A sync pattern generating circuit for generating a sync pattern, a sync pattern data which is an output signal of the sync pattern generating circuit, and an output signal of the first selector circuit to generate a prescribed frame format.
P / S for converting the output signals of the selector circuit and the third selector circuit from parallel data to serial data.
A telemeter device including a conversion circuit. 3. An analog multiplexer for inputting an analog signal from an external device and time-division multiplexing, and a burst clock input with a continuous clock signal from another external device. Synchronizing with a parallel data signal and the parallel data signal. A receiver circuit for receiving a digital signal composed of a burst clock signal input by the following, a burst detection circuit for receiving the burst clock signal and outputting a start signal for determining a frame format reference position, and the clock A frame editing circuit that inputs a signal and the start signal to generate a frame format, and the start signal and the start signal of the frame format that are input to detect the deviation of the reference position and determine the dummy frame insertion on a frame-by-frame basis to edit the frame. Instruct the circuit to output a dummy frame A dummy frame control circuit, a write address control circuit for controlling generation of an address and a write enable signal to a memory circuit for writing the parallel data by the burst detection circuit, and the parallel data signal input in burst A memory circuit that temporarily stores and reads parallel data in accordance with a specified frame format, and a write / write operation of the memory circuit.
A second selector circuit for controlling the read address, an A / D conversion circuit for converting the output signal of the analog multiplexer from an analog to a digital signal, an output signal of the memory circuit and an output signal of the A / D conversion circuit. A first selector circuit selected by the control of the frame editing circuit, and an identification code generation for generating an identification code for identifying whether or not the dummy frame is a dummy frame when it is determined that the dummy frame is output by the control of the frame editing circuit. A circuit, a dummy data generation circuit for generating known dummy frame data for switching and outputting the output signal of the A / D conversion circuit and the output signal of the memory circuit during dummy frame, and the output of the first selector circuit Switch the signal to the output signal of the above identification code generation circuit and the output signal of the dummy data generation circuit A fourth selector circuit for performing a control, a sync pattern generation circuit for generating a sync pattern for indicating the leading data of the output of the telemeter device, a sync pattern data which is an output signal of the sync pattern generation circuit, and the fourth pattern. A third selector circuit that selects an output signal of the selector circuit to generate a prescribed frame format, a P / S conversion circuit that converts the output signal of the third selector circuit from parallel data to serial data, and the clock. A telemeter device comprising: a clock detection circuit for detecting that a signal is lost; and an oscillator for generating the dummy frame when the clock signal is lost. 4. An analog multiplexer for inputting an analog signal from an external device and time-division multiplexing, and a burst clock input with a continuous clock signal from another external device. Synchronizing with a parallel data signal and the parallel data signal. A receiver circuit for receiving a digital signal composed of a burst clock signal input by the following, a burst detection circuit for receiving the burst clock signal and outputting a start signal for determining a frame format reference position, and the clock A frame editing circuit that inputs a signal and the start signal to generate a frame format, and the start signal and the start signal of the frame format that are input to detect the deviation of the reference position and judge the insertion of dummy data in frame units to edit the frame. Dummy that instructs the circuit to output dummy data -A data control circuit, a write address control circuit that controls the generation of an address and a write enable signal to a memory circuit for writing the parallel data by the burst detection circuit, and the parallel data signal that is input in bursts Circuit for accumulating and storing parallel data in accordance with a prescribed frame format, a second selector circuit for controlling the write / read address of the memory circuit, and converting the output signal of the analog multiplexer from analog to digital signal An A / D conversion circuit, an identification code generation circuit for generating an identification code for identifying whether or not the frame includes dummy data when it is determined to output dummy data under the control of the frame editing circuit, and a dummy Output of the above memory circuit during frame A dummy data generating circuit for generating known dummy data for switching and outputting signals, and a control for switching the output signal of the memory circuit between the output signal of the identification code generating circuit and the output signal of the dummy data generating circuit. 4 selector circuits, a first selector circuit for selecting the output signal of the A / D conversion circuit and the output signal of the fourth selector circuit under the control of the frame editing circuit, and for showing the leading data of the telemeter device output. A sync pattern generating circuit for generating a sync pattern, a sync pattern data which is an output signal of the sync pattern generating circuit, and an output signal of the first selector circuit to generate a prescribed frame format.
P / S for converting the output signals of the selector circuit and the third selector circuit from parallel data to serial data.
A telemeter device comprising: a conversion circuit; a clock detection circuit that detects that the clock signal is lost; and an oscillator that generates the dummy data insertion frame when the clock signal is lost. 5. An analog multiplexer for inputting an analog signal from an external device and performing time division multiplexing, and a burst clock input with a continuous clock signal from another external device. Synchronizing with a parallel data signal and the parallel data signal. A receiver circuit for receiving a digital signal composed of a burst clock signal input by the following, a burst detection circuit for receiving the burst clock signal and outputting a start signal for determining a frame format reference position, and the clock A frame editing circuit that inputs a signal and the start signal to generate a frame format, and the start signal and the start signal of the frame format that are input to detect the deviation of the reference position and determine the dummy frame insertion on a frame-by-frame basis to edit the frame. Instruct the circuit to output a dummy frame A dummy frame control circuit, a write address control circuit for controlling generation of an address and a write enable signal to a memory circuit for writing the parallel data by the burst detection circuit, and the parallel data signal input in burst A memory circuit that temporarily stores and reads parallel data in accordance with a specified frame format, and a write / write operation of the memory circuit.
A second selector circuit that controls the read address, an A / D conversion circuit that converts the output signal of the analog multiplexer from an analog to a digital signal, and a first tristate that controls the output signal of the A / D conversion circuit. A buffer, a second tri-state buffer for controlling the output signal of the memory circuit, a first tri-state buffer, and a third tri-state that inputs the multiplexed output signals of the second tri-state buffer A buffer, an identification code generation circuit for generating an identification code for identifying whether or not the dummy frame is a dummy frame when it is determined to output a dummy frame by the control of the frame editing circuit, and an output signal of the identification code generation circuit. A sixth tri-state buffer for controlling, and the A / D conversion circuit at the time of dummy frame A dummy signal generating circuit for generating known dummy frame data for switching between the output signal of the memory circuit and the output signal of the memory circuit; a seventh tri-state buffer for controlling the output signal of the dummy data generating circuit; Third tri-state buffer and sixth
Decoder circuit for selectively controlling the output signals of the tri-state buffer and the seventh tri-state buffer, the fourth tri-state buffer for inputting the multiplexed signal under the control of the decoder circuit, and the head data of the telemeter device output And a sync pattern generating circuit for generating a sync pattern for indicating
P-S conversion for multiplexing the output signals of the fourth tri-state buffer and the fifth tri-state buffer for inputting and converting the parallel data into serial data in order to generate a specified frame format. A telemeter device including a circuit. 6. An analog multiplexer for inputting an analog signal from an external device and time-division multiplexing, and inputting a continuous clock signal from another external device in a burst manner. Synchronizing with a parallel data signal and the parallel data signal. A receiver circuit for receiving a digital signal composed of a burst clock signal input by the following, a burst detection circuit for receiving the burst clock signal and outputting a start signal for determining a frame format reference position, and the clock A frame editing circuit that inputs a signal and the start signal to generate a frame format, and the start signal and the start signal of the frame format that are input to detect the deviation of the reference position and judge the insertion of dummy data in frame units to edit the frame. Dummy that instructs the circuit to output dummy data -A data control circuit, a write address control circuit that controls the generation of an address and a write enable signal to a memory circuit for writing the parallel data by the burst detection circuit, and the parallel data signal that is input in bursts Memory circuit for storing parallel data according to a specified frame format, a second selector circuit for controlling the write / read address of the memory circuit, and a third trie circuit for controlling the output signal of the memory circuit. An output signal of the state buffer, an identification code generation circuit for generating an identification code for identifying whether or not the dummy data is dummy data when it is determined to output dummy data under the control of the frame editing circuit, and the output signal of the identification code generation circuit. Sixth to control
A tri-state buffer, a dummy data generation circuit for generating known dummy data for switching and outputting the output signal of the memory circuit at the time of dummy data, and a seventh trie for controlling the output signal of the dummy data generation circuit. A state buffer, a decoder circuit for selectively controlling output signals of the third tristate buffer, the sixth tristate buffer, and the seventh tristate buffer, and a signal multiplexed by control of the decoder circuit are input. A second tri-state buffer, an A / D conversion circuit that converts the output signal of the analog multiplexer from an analog to a digital signal, a first tri-state buffer that controls the output signal of the A / D conversion circuit, and First tri-state buffer and second tri-state buffer Fourth tri-state buffer for inputting a signal multiplexed by the above, a sync pattern generating circuit for generating a sync pattern for indicating the head data of the output of the telemeter device, and a sync pattern data which is an output signal of the sync pattern generating circuit. And a fifth tri-state buffer for controlling the output signal of the second tri-state buffer and the output signals of the fourth and third tri-state buffers to generate a prescribed frame format are multiplexed and input, and serialized from parallel data. A telemeter device having a P / S conversion circuit for converting data. 7. An analog multiplexer for inputting an analog signal from an external device and time-division multiplexing, and a burst clock input with a continuous clock signal from another external device. Synchronizing with a parallel data signal and the parallel data signal. A receiver circuit for receiving a digital signal composed of a burst clock signal input by the following, a burst detection circuit for receiving the burst clock signal and outputting a start signal for determining a frame format reference position, and the clock A frame editing circuit that inputs a signal and the start signal to generate a frame format, and the start signal and the start signal of the frame format that are input to detect the deviation of the reference position and determine the dummy frame insertion on a frame-by-frame basis to edit the frame. Instruct the circuit to output a dummy frame A dummy frame control circuit, a write address control circuit for controlling generation of an address and a write enable signal to a memory circuit for writing the parallel data by the burst detection circuit, and the parallel data signal input in burst A memory circuit that temporarily stores and reads parallel data in accordance with a specified frame format, and a write / write operation of the memory circuit.
A second selector circuit that controls the read address, an A / D conversion circuit that converts the output signal of the analog multiplexer from an analog to a digital signal, and a first tristate that controls the output signal of the A / D conversion circuit. A buffer, a second tri-state buffer for controlling the output signal of the memory circuit, a first tri-state buffer, and a third tri-state that inputs the multiplexed output signals of the second tri-state buffer A buffer, an identification code generation circuit for generating an identification code for identifying whether or not the dummy frame is a dummy frame when it is determined to output a dummy frame by the control of the frame editing circuit, and an output signal of the identification code generation circuit. A sixth tri-state buffer for controlling, and the A / D conversion circuit at the time of dummy frame A dummy signal generating circuit for generating known dummy frame data for switching between the output signal of the memory circuit and the output signal of the memory circuit; a seventh tri-state buffer for controlling the output signal of the dummy data generating circuit; Third tri-state buffer and sixth
Decoder circuit for selectively controlling the output signals of the tri-state buffer and the seventh tri-state buffer, the fourth tri-state buffer for inputting the multiplexed signal under the control of the decoder circuit, and the head data of the telemeter device output And a sync pattern generating circuit for generating a sync pattern for indicating
P-S conversion for multiplexing the output signals of the fourth tri-state buffer and the fifth tri-state buffer for inputting and converting the parallel data into serial data in order to generate a specified frame format. A telemeter device comprising: a circuit; a clock detection circuit for detecting that the clock signal is lost; and an oscillator for generating the dummy frame when the clock signal is lost. 8. An analog multiplexer for inputting an analog signal from an external device and time-division multiplexing, and a burst clock input with a continuous clock signal from another external device. Synchronizing with a parallel data signal and the parallel data signal. A receiver circuit for receiving a digital signal composed of a burst clock signal input by the following, a burst detection circuit for receiving the burst clock signal and outputting a start signal for determining a frame format reference position, and the clock A frame editing circuit that inputs a signal and the start signal to generate a frame format, and the start signal and the start signal of the frame format that are input to detect the deviation of the reference position and judge the insertion of dummy data in frame units to edit the frame. Dummy that instructs the circuit to output dummy data -A data control circuit, a write address control circuit that controls the generation of an address and a write enable signal to a memory circuit for writing the parallel data by the burst detection circuit, and the parallel data signal that is input in bursts Memory circuit for storing parallel data according to a specified frame format, a second selector circuit for controlling the write / read address of the memory circuit, and a third trie circuit for controlling the output signal of the memory circuit. An output signal of the state buffer, an identification code generation circuit for generating an identification code for identifying whether or not the dummy data is dummy data when it is determined to output dummy data under the control of the frame editing circuit, and the output signal of the identification code generation circuit. Sixth to control
A tri-state buffer, a dummy data generation circuit for generating known dummy data for switching and outputting the output signal of the memory circuit at the time of dummy data, and a seventh trie for controlling the output signal of the dummy data generation circuit. A state buffer, a decoder circuit for selectively controlling output signals of the third tristate buffer, the sixth tristate buffer, and the seventh tristate buffer, and a signal multiplexed by control of the decoder circuit are input. A second tri-state buffer, an A / D conversion circuit that converts the output signal of the analog multiplexer from an analog to a digital signal, a first tri-state buffer that controls the output signal of the A / D conversion circuit, and First tri-state buffer and second tri-state buffer Fourth tri-state buffer for inputting a signal multiplexed by the above, a sync pattern generating circuit for generating a sync pattern for indicating the head data of the output of the telemeter device, and a sync pattern data which is an output signal of the sync pattern generating circuit. And a fifth tri-state buffer for controlling the output signal of the second tri-state buffer and the output signals of the fourth and third tri-state buffers to generate a prescribed frame format are multiplexed and input, and serialized from parallel data. Telemeter device including P / S conversion circuit for converting to data, clock detection circuit for detecting interruption of the clock signal, and oscillator for generating the dummy data insertion frame when the clock signal is interrupted .