JPH09205591A - Timing pulse generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a memory capacity by obtaining a timing pulse repeated in a horizontal direction and a timing pulse repeated in a vertical direction from separate ROMs. SOLUTION: Pulses SH1 , SH2 repeated in a horizontal direction are outputted from a horizontal ROM circuit 65 and a pulse SH3 specifying a vertical transfer period, that is, a period not outputting horizontal transfer clocks H1, H2 is outputted. Furthermore, a pulse Sv1 repeating in a vertical direction at a low level corresponding to a read period of a CCD solid-state image pickup element 3 for odd and even numbered fields is outputted from a vertical ROM circuit 69. Thus, the horizontal repetitive pulses SH1 -SH3 are obtained from the horizontal ROM circuit 65 and the vertical repetitive pulse Sv1 is obtained from the vertical ROM circuit 69 in this way, then the data quantity written in each ROM of the horizontal ROM circuit 65 and the vertical ROM circuit 69 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing pulse generation circuit that generates a timing pulse for controlling the operation of a CCD image pickup device.

[0002]

2. Description of the Related Art FIG. 13 shows an example of a CCD solid-state imaging device. The example shown in the figure is an example of an interline transfer method.

In FIG. 1, reference numeral 1 denotes a CCD device;
Is an output terminal of the charge detection signal. Also, the CCD device 1
In the figure, 3 is a CCD solid-state imaging device, 4 is a light receiving unit, 5 is a transfer gate, 6 is a vertical shift register, 7 is a horizontal shift register, and 8 is a charge detection unit.

The vertical shift register 6 has a terminal 9
Fourteen-phase vertical transfer clock V1 as shown in FIGS.
.About.V4 are supplied, the signal charges accumulated in the light receiving section 4 are transferred to the vertical shift register 6, and the signal charges thus transferred to the vertical shift register 6 are transferred to the horizontal shift register 7. That is, the vertical transfer clock V1
And V3, the level V _L, V _H, a ternary-level clock with a V _T, the vertical transfer clock V2 and V4,
Level V _L, is a binary-level clock with a V _H.
The vertical transfer clock V1 becomes the level V _T is in the first vertical blanking period of the odd field, the vertical transfer clock V3 becomes the level V _T is in the first vertical blanking period of the even field. 14A and 14B show a vertical synchronization pulse VD and a horizontal synchronization pulse HD, respectively.

FIG. 15 shows the relationship among the light receiving section 4, the transfer gate 5, and the vertical shift register 6. As shown in the figure, the vertical shift register 6 has electrodes Va, Vb, and V at half the pitch of the light receiving elements SA and SB of the light receiving unit 4.
c and Vd are formed. In this case, the vertical shift register 6
Electrodes Vb and Vd of the vertical shift register 6 are arranged so as to correspond to the light receiving elements SB and SA of the light receiving section 4, respectively, while the electrodes Va and Vc of the vertical shift register 6 are provided to both the light receiving elements SA and SB of the light receiving section 4, respectively. It is arranged to straddle. Then, the above-described four-phase vertical transfer clocks V1 to V4 are supplied to the electrodes Va to Vd of the vertical shift register 6.

In such a configuration, the signal charge accumulated in the light receiving elements SA and SB during the period in which the vertical transfer clock V1 is at the level VT within the first vertical blanking period of the odd field is transmitted through the transmission gate 5. Then, it is transferred to the portion corresponding to the electrode Va of the vertical shift register 6. After that, the data is transferred to the horizontal shift register 7 by the vertical shift register 6 for each scanning line. FIGS. 16A to 16F correspond to FIG.
Time points t1 of the vertical transfer clocks V1 to V4 shown in 7A to 7D
Although the transfer positions of the signal charges at t6 to t6 are shown, as is apparent from this figure, the wells of the potential are sequentially moved, and the signal charges transferred to the portion of the electrode Va of the vertical shift register 6 are transferred. (Illustrated by a minus circle) is transferred vertically. Also, the first of the even field period the vertical transfer clock V3 becomes the level V _T in the vertical blanking period, the signal charges accumulated in the light receiving element SB and SA is the vertical shift register 6 through the transfer gate 5 The data is transferred to a portion corresponding to the electrode Vc. After that, as in the case of the odd field described above, the vertical shift register 6
Is transferred one scanning line at a time.

Returning to FIG. 13, the horizontal shift register 7 has terminals 1 and 11 connected to the horizontal shift register 7 as shown in FIGS.
Two-phase horizontal transfer clocks H1 and H2 having a pixel cycle, for example, a 70 ns cycle are supplied, and the signal charges are sequentially taken out via the charge detection unit 8.

The output end of the charge detection unit 8 is grounded via the capacitor 12 and is connected to the source of the FET 13, and its drain is supplied with the DC voltage E _R. A reset pulse PG (shown in FIG. 18D) synchronized with the horizontal transfer clocks H1 and H2 is supplied from a terminal 14 to the gate of the FET 13 via a capacitor 15. The connection point between the charge detection unit 8 and the capacitor 12 is connected to the gate of the FET 16, the drain of the FET 16 is supplied with the DC voltage E, and the source thereof is connected with the output terminal 2.

In the above configuration, the reset pulse PG
Is high level, the FET 13 is turned on,
The capacitor 12 is charged up to the voltage E _{R and} reaches the reset level. On the other hand, the FET 13 is turned off during the period when the reset pulse PG is at a low level, and the voltage across the capacitor 12 decreases in accordance with the signal charge from the charge detection unit 8. Therefore, the charge detection output voltage V _O as shown in FIG. 18E is output to the output terminal 2. E _P in FIG. 18E is a precharge level, level following the precharge level is the signal level.

[0010] is treated as follows to detect and output an output signal S _O than the output voltage V _O, the reset noise N _R to be different levels for each reset riding on the signal level portion removed To be done. That is, when the ride is reset noise N _R to the signal level portion is defined by noting reset noise N _R of the same level to the precharge level portion rides. In Figure 18E, the broken line shows a state in which the reset noise N _R is riding.

In FIG. 13, the output voltage V _O from the output terminal 2 is supplied to the sample hold circuit 21 which constitutes the output circuit 20. A sampling pulse SHD (shown in FIG. 18G) corresponding to the signal level period is supplied to the sample hold circuit 21 from the terminal 26 to sample and hold the signal level portion of the output voltage V _O. Then, the hold output H _S is supplied to the inverting input terminal of the operational amplifier 22.

The output voltage V _O is also supplied to the sample hold circuit 23. A sampling pulse SH _P (illustrated in FIG. 18F) corresponding to the precharge level period is supplied to the sample hold circuit 23 from the terminal 27, and the precharge level portion of the output voltage V _O is sampled and held. Then, the hold output H _N1
Are further supplied to the sample hold circuit 24. The sampling pulse SHD is supplied to the sample-hold circuit 24 from the terminal 26, and the hold output H _N1 is sampled and held. Then, the hold output H _N2 is supplied to the non-inverting input terminal of the operational amplifier 22.

Here, jumping pulses appear on the hold outputs H _S , H _N1 and H _N2 in correspondence with the sampling pulses, respectively.

[0014] In the above configuration, the output voltage V to _O when the reset noise N _R different levels for each reset rests as shown in broken line in FIG. 18E, the sample-hold circuits 21 and 23 are not shown , 24 also have reset noise N _{R on} the hold outputs H _S , H _N1 and H _N2 . Therefore, the reset noise N _R can be removed by taking the difference between the hold outputs H _S and H _N1 . However, the hold outputs H _S and H _N1 are the output voltage V _O
Because of the sampling at different times
When a phase difference is generated at the point of time when the dive pulse is output and the difference between the hold outputs H _S and H _N1 is simply taken, the dive pulse appears as it is. In this example, since the hold output H _N1 is further sampled and held by the sampling pulse SHD as described above, the jump pulse in the hold output H _N2 is in phase with the jump pulse in the hold output H _S.

Therefore, at the output terminal 25 derived from the operational amplifier 22, the reset noise N _R is removed, and the output signal S _O in which the jump pulse during the sample hold is sufficiently suppressed is obtained.

The vertical transfer clocks V1 to V4 and the horizontal transfer clocks H1 and H supplied to the image pickup apparatus shown in FIG.
2, reset pulse PG, sampling pulse SHD,
The SHP is formed with a configuration as shown in FIG. That is, reference numeral 31 denotes a timing generation circuit. The timing generation circuit 31 is supplied with a frequency signal S1 having a frequency of, for example, 8 fsc (where fsc is a color subcarrier frequency and is 3.58 MHz in the NTSC system) from the crystal oscillator 32. You. Then, a frequency signal S2 having a frequency of 4 fsc is generated from the timing generation circuit 31,
This frequency signal S2 is supplied to the synchronization signal generator 33. In this synchronizing signal generator 33, a vertical synchronizing pulse VD and a horizontal synchronizing pulse HD (shown in FIGS. 14A and 14B) are formed based on the frequency signal S2, and these synchronizing pulse V
The D and HD are supplied to the timing generation circuit 31.

From the timing generation circuit 31, a sensor gate signal XSG (shown in FIG. 14F) for specifying a period (readout period) in which the signal charge is transferred from the light receiving portion 4 of the CCD solid-state image pickup device 3 to the vertical shift register 6 and the vertical direction. Transfer clocks V1 'to V4' (shown in FIGS. 14G to J) are generated and supplied to the vertical clock driver 34, respectively. The vertical clock driver 34 supplies the vertical transfer clocks V1 to V4 (illustrated in FIGS. 14K to 14N) to the terminal 9 of the CCD device 1. Further, a pulse XPG (shown in FIG. 18C) is generated from the timing generation circuit 31 and is supplied to a reset pulse driver 35 configured by an inverter. From the reset pulse driver 35, a reset pulse PG (shown in FIG. 18D) is generated. Is supplied to the terminal 14 of the CCD device 1. Further, from the timing generation circuit 31, the horizontal transfer clocks H1 and H2 (see FIG.
(Shown in A and B) is generated, and this horizontal transfer clock H
1, 1 and H2 are supplied to the terminals 10 and 11 of the CCD device 1 through the horizontal clock driver 36. Further, the timing generation circuit 31 outputs sampling pulses SHD, S
HP (shown in FIGS. 18F and 18G) is generated and the output circuit 2
0 terminals 26 and 27. In FIG. 18, T _PG indicates the delay time by the reset pulse driver 35, and T _IM1 and T _IM2 indicate the delay time by the CCD device 1.

[0018]

By the way, in the timing generating circuit 31, the vertical transfer clocks V1 'to V1.
4 ', a circuit for generating a timing pulse such as the sensor gate signal XSG is configured by using a logic circuit, for example. With such a configuration, the timing pulse to be generated is uniquely determined by its logical configuration,
When changing or modifying the timing pulse to be generated, it is not easy because a new design needs to be made at the time of changing or modifying. Therefore, it has been considered to generate a timing pulse using a ROM as shown in FIG. 20 so that the generated timing pulse can be easily changed and corrected without such troublesomeness. In FIG. 20, reference numeral 41 is a counter, and 42 is a ROM. Timing pulses P1, P2, P3, ...
.. is written, the count output of the counter 41 is supplied as an address signal to the ROM 42, and the pulses P1, P2, P are output from the ROM 42.
3, ... Is output.

According to the example of FIG. 20, since the timing pulse that repeats in the horizontal direction and the timing pulse that repeats in the vertical direction are obtained from the common ROM 42, the capacity of the ROM 42 becomes enormous. For example, in the case of the NTSC system, 2fsc = 455f _H (f
_H is the horizontal frequency) and 525 lines /
Since there is a frame relationship, the frequency of the clock CLK supplied to the clock terminal CK of the counter 41 is 2 fsc.
, The data for generating one timing pulse is 455 × 525 = 238875 bits. Therefore, the capacity of the ROM 42 requires N × 238875 bits when N timing pulses are generated. Therefore, the capacity of the ROM 42 is set to 262144 bits corresponding to one timing pulse, and at this time, it is sufficient for the address counter to specify the address of 262144, and the counter 41 is set to an 18-bit counter.

An object of the present invention is to take such a point into consideration and to make it possible to reduce the memory capacity.

[0021]

In the timing pulse generation circuit of the present invention, a read address is controlled by a first address counter controlled by a first reference pulse of a horizontal period and the output of the first address counter. First R to be
OM means, a second address counter controlled by a second reference pulse having a frequency sufficiently higher than the horizontal frequency, and a second ROM whose read address is controlled by the output of the second address counter. Means for obtaining a first timing pulse and a second timing pulse from the first ROM means and the second ROM means, respectively, the second ROM means comprising: , A first R in which logic level data is stored
OM, and a second ROM in which holding period data representing a period for holding the level of the logic level data is stored, the first ROM is controlled to generate the second timing pulse, and The second address counter is
The second reference pulse is counted, and the second ROM is counted.
A first counter for generating an output pulse based on an output result from the first counter, and a second count controlled by an output from the first counter, the output of the second counter including the first counter. ROM address and above second
The address of the ROM is controlled.

According to such a timing pulse generating circuit, the following operations are performed. A timing pulse that is repeated in the vertical direction is obtained from the first ROM, and the second R
Since the timing pulse that is repeated in the horizontal direction is obtained from the OM, the first and second ROMs can be configured with a small capacity.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a timing generation circuit. In the figure, reference numeral 51 denotes an oscillator. A frequency signal S1 having a frequency of, for example, 8 fsc from the oscillator 51 is supplied to a terminal 61 of a timing generation circuit 60. Further, a vertical synchronizing pulse VD and a horizontal synchronizing pulse HD are respectively supplied from a synchronizing signal generator (not shown) to terminals 62 and 63 of the timing generating circuit 60, and these synchronizing pulses VD and HD (FIGS. 14A and 14B) are supplied.
(Shown in FIG. 3) is supplied to the synchronizing circuit 64.

Reference numeral 65 is a horizontal ROM circuit. The frequency signal S1 supplied to the terminal 61 is supplied to the frequency divider 67 via the frequency divider 66, and the 2fsc frequency signal output from the frequency divider 67 is supplied to the horizontal ROM circuit 65 as a clock CLKH. Is done. Further, a reset pulse P _RH having a horizontal cycle is generated from the synchronizing circuit 64, and this reset pulse P _RH is supplied to the horizontal ROM circuit 65. Then, from the horizontal ROM circuit 65, pulses S _H1 and S _{H that} are repeated in the horizontal direction as shown in FIGS.
_H2 is output and a pulse S for specifying a period during which the horizontal transfer clocks H1 and H2 are not output during the vertical transfer period.
_H3 is output.

The horizontal ROM circuit 65 is constructed, for example, as shown in FIG. In the figure, reference numeral 651 denotes a 7-bit counter constituting an address counter. The clock CLKH is supplied to the clock terminal CK of the counter 651, the reset pulse P _RH is supplied to the reset terminal RE. The 7-bit count output of the counter 651 is supplied to the ROM 652 as an address signal. At each address of the ROM 652, data of a timing pulse that repeats in the horizontal direction is written. For the NTSC system, there is a relation of 2fsc = 455f _H, data for generating the original one timing pulse from the frequency of the clock CLKH is 2 fsc becomes 455 bits. However, in consideration of noise in the video signal, most of the timing pulses change within the horizontal blanking period. In this example, only data before and after such a change is written to the ROM 652. For example, the data written in the ROM 652 to generate one timing pulse is 128 bits. As described above, since the data written to the ROM 652 to generate one timing pulse that repeats in the horizontal direction is 128 bits, the address counter only needs to be able to specify 128 addresses. Be composed. Note that RO
Since only data before and after the timing pulse changes is written in M652, the data is read out and output at the corresponding timing. The counting operation is controlled.

The horizontal ROM circuit 65 is constructed, for example, as shown in FIG. In the figure, 651 'is an 8-bit counter. The clock terminal CK of the counter 651 ', the clock CLKH is supplied to its reset terminal RE, a reset pulse P _RH is supplied. The counter 651 'is supplied with data DCK which determines the interval and indicates the number n of clocks CLKH, and the counter 651' is set to an n-ary counter.

652 'is a 5-bit counter. The carry (carry output) of the counter 651 'is supplied to the clock terminal CK of the counter 652'.
A reset pulse P _RH is supplied to the reset terminal RE. The 5-bit count output of the counter 652 'is stored in the address ROM 653' and the data ROM 654 '.
Is supplied as an address signal.

At each address of the address ROM 653 ', data DCK indicating the number n of the clocks CLKH that determine the interval from the time when the timing pulse changes to the next time is written. Also, the data R
Of the timing pulse data, only the data at the time of change is written in each address of the OM 654 '.

From the data ROM 654 ', in practice,
The pulses S _{H1 to} S _H3 are output, but here,
For simplification of explanation, it is assumed that timing pulses P1 and P2 as shown in FIGS. 4A and 4B are generated. In this case, the addresses X, X + 1, X of the address ROM 653 '
At +2, as shown in FIG.
"0", "15", and "6" are written. Further, as shown in FIG. 6, "1", "1" and "0" are written as the data for the pulse P1 in the addresses X, X + 1 and X + 2 of the data ROM 654 ', and at the same time as the data for the pulse P2. "1", "0", and "0" are written.

The data DCK output from the address ROM 653 'is the 8-bit counter 651' described above.
Is supplied to.

In the configuration as shown in FIG. 3, the 5-bit counter 65 is reset by, for example, being reset at the time point T _1.
The count output of 2'becomes "X", and the address ROM6
Since the data DCK output from 53 'is "10", the 8-bit counter 651' is set to a decimal counter, and the timing pulses P1 and P2 output from the data ROM 654 'are at the high level "1". "
And the high level "1".

Next, the 8-bit counter 651 'has 10 bits.
Since it is set in the decimal counter, the clock CLKH
8-bit counter 65 at the time T ₂ when 10 pieces are supplied
Carry is output from 1 ', and at this time T ₂ , the count output of the 5-bit counter 652' becomes "X + 1",
Since the data DCK output from the address ROM 653 'is "15", the 8-bit counter 651' has 15
The data ROM 65 is set in the binary counter.
Timing pulses P1 and P2 output from 4'are
High level "1" and low level "0" respectively. next,
8-bit counter 651 'is, because it is set to 15 binary counter, clock CLKH are 15 supplied at T ₃ 8-bit counter 651 is' outputs a carry from, at which time T ₃ 5-bit counter 652' Counter output becomes "X + 2", and the address ROM65
Since the data DCK output from 3'is "6",
The 8-bit counter 651 'is set to a hexadecimal counter, and the timing pulses P1 and P2 output from the data ROM 654' are low level "0" and low level "0", respectively. Hereinafter, the operation is repeated as described above. Therefore, from the data ROM 654 ',
Timing pulses P1 and P2 as shown in FIGS.
Is obtained. That is, as in the example of FIG. 3, the horizontal ROM
Even if the circuit 65 is configured, the pulses S _{H1 to} S _H3 can be obtained.

Further, the horizontal ROM circuit 65 is shown in FIG.
It is configured as shown in FIG. In the figure, 651 ″ is 8
It is a bit counter. The clock CLKH is supplied to the clock terminal CK of the counter 651 ", and the reset pulse P _RH is supplied to the reset terminal RE. The 8-bit count output of the counter 651" is supplied to a comparator. 655 ". Also,
The data DCK output from the address ROM 653 'is supplied to the comparator 655 ". When the count output of the counter 655" matches the data DCK, the coincidence detection pulse is output from the comparator 655 ". The coincidence detection pulse is supplied to the clock terminal CK of the 5-bit counter 652 '. The counter 651 "is reset every time the coincidence detection pulse is output. Otherwise, the configuration is the same as in the example of FIG.

Also in this FIG. 7 example, as is clear from the configuration, the same operation as in the example of FIG. 3 is performed.

Returning to FIG. 1, 69 is a vertical ROM circuit. From the synchronization circuit 64, the clock CLKV of the horizontal cycle
And a reset pulse P _{RV of a} frame period are generated, and the clock CLKV and the reset pulse P _RV are supplied to the vertical ROM circuit 69. And this vertical ROM
From the circuit 69, as shown in FIG. 14E, a pulse _SV1 that repeats in the vertical direction and goes low in response to the readout period of the CCD solid-state imaging device 3 in the odd and even fields is output.

The vertical ROM circuit 69 is constructed, for example, as shown in FIG. In the figure, 691 is sufficient if a 5-bit counter address forming the address counter can be designated.
It consists of. Since only the data before and after the timing pulse changes are written in the ROM 692,
In order to read out and output this data at the corresponding timing, the counting operation of the counter 691 is controlled by a control signal generated from the synchronizing circuit 64 (not shown), for example.

Returning to FIG. 1, the horizontal ROM circuit 65
The pulses S _H1 and S _H2 output from the vertical ROM circuit 69 and the pulse S _V1 output from the vertical ROM circuit 69 are
In this vertical clock circuit 68, vertical transfer clocks V1 'to V4' (shown in FIGS. 14G to J) and a sensor gate signal XSG (shown in FIG. 14F) are formed and supplied to terminals 70 and 71, respectively. You.

Further, the frequency signal S supplied to the terminal 61
1 is converted into a frequency signal S2 'having a frequency of 4 fsc by a frequency divider 72, and then supplied to a phase adjusting circuit 74 via a gate circuit 73. Since the pulse _SH3 output from the horizontal ROM circuit 65 is supplied to the gate circuit 73 as a gate pulse, the phase adjustment circuit 74 is a vertical transfer period and a period during which the horizontal transfer clocks H1 and H2 are not output. So that the frequency signal S2 'is not supplied.

In the phase adjusting circuit 74, the frequency signal S
2'from horizontal transfer clocks H1 and H2 (shown in FIGS. 18A and 18B) and reset pulses SHP and SHD (see FIGS. 18F and 18G).
Are formed), and the phases are adjusted respectively. in this case,
The phase adjustment of the horizontal transfer clocks H1 and H2 is performed in consideration of the group delay in the horizontal clock driver described later.

The phase adjusting section is performed by using an inverter array in which inverters 91 are connected in series as shown in FIG. That is, the extension time (propagation delay time) of the inverter is used. In this case, in order to stably reproduce the delay time, the characteristics of the respective inverters 91 are exactly the same, and the wiring length between the respective inverters 91 is made the same, so that the capacitance attached to the output of the respective inverters 91 is obtained. (Which is an element that determines the delay time) is made constant. At this time, the wiring is made the shortest in order to eliminate the variation in the process (particularly the variation in the capacitance of the wiring). Further, each inverter row is treated as one cell including the layout of the inverters 91 and the wiring length between the inverters 91. That is, each inverter row is
They have the same shape and are arranged close to each other with the same characteristics. In each of the inverter trains, the phase is adjusted by changing the point at which the output is taken out. In FIG. 9, 9
2 is an output buffer.

Although not described above, the entire timing generation circuit 60 is formed as an IC on the same substrate.
The wiring is a multilayer wiring. The wiring of the phase adjustment unit is the wiring of the uppermost layer, and is made of so-called 2Al. Therefore, by changing one 2Al mask, the phase is adjusted to match the external circuit conditions.

Further, the reset pulse XPG and sampling pulses SHP, S whose phases have been adjusted by the phase adjusting circuit 74 are used.
HD is supplied to terminals 75, 76, and 77, respectively. The horizontal transfer clocks H1 and H2 whose phases have been adjusted by the phase adjustment circuit 74 are supplied to terminals 79 and 80 via horizontal clock drivers 781 and 782, respectively. In this case, the horizontal clock drivers 781 and 782 are respectively shown in FIG.
As shown in FIG. 0, inverters I _{1 to} I ₅ are connected in series. In this case, the inverters I _{1 to} I ₅ are respectively connected to the P-channel MOSFET Q _{P as} shown in FIG.
According to consist is connected to the N-channel MOSFET Q _N is an inverter I ₁ and I _5, FE
Both TQ _P and Q _N are formed such that the channel width is increased by about three times (the channel length is substantially constant), and the drive capability is gradually increased.

Returning to FIG. 1, the frequency signal S2 having a frequency of 4 fsc output from the frequency divider 66 is supplied to the terminal 81.

FIG. 12 is a timing generator circuit 6 of the example of FIG.
FIG. 19 shows a CCD solid-state imaging device when 0 is used, and portions corresponding to FIG. 19 are denoted by the same reference numerals.

As described above, according to this example, the horizontal repeating pulses S _{H1 to} S _H3 are obtained from the horizontal ROM circuit 65, and the vertical repeating pulses S _V1 are obtained from the vertical ROM circuit 69. , ROMs 652, 65 of the horizontal ROM circuit 65 and the vertical ROM circuit 69
The amount of data written to 3 ', 654', 692 is reduced, and the capacity of the ROM used can be reduced.

Further, the horizontal ROM circuit 65 and the vertical ROM
According to the circuit 69 configured as shown in FIGS. 2 and 8, respectively, only data before and after the timing pulse changes are written in the ROMs 652 and 692.
The amount of data to be written is further reduced, and the ROM 65
2 and 692 can be made smaller.

According to the horizontal ROM circuit 65 configured as shown in FIGS. 3 and 7, the address ROM is
The data DCK of the inverter between the timings of the change of the timing pulse is written into
Since only the data at the timing of the change of the timing pulse is written in M654 ', the amount of write data is reduced, and the capacity of the ROMs 653' and 654 'can be reduced.

Further, the entire timing generation circuit 60 is formed as an IC on the same substrate to form a multilayer wiring. Since the wiring of the phase adjustment circuit 74 is made of 2Al, the phases of the horizontal transfer clocks H1 and H2, the reset pulse XPG, and the sampling pulses SHP and SHD are changed to a phase that matches the external circuit conditions by changing one 2Al mask. Can be adjusted, and the phase can be easily adjusted.

Further, horizontal clock drivers 781 and 78
2 are formed on the same substrate as the timing generating circuit 60, so that the sampling pulses SHP and SHD and the horizontal transfer clocks H1 and H
The phase relationship with 2 becomes constant, and the sampling in the output circuit 20 can be performed accurately by only considering the delay time in the CCD device 1.

The preset pulse driver 35 may be formed on the same substrate as the timing generation circuit 60. However, if the level of the reset pulse PG is not sufficient, the reset will be insufficient. Therefore, in this example, in order to make the level of the reset pulse PG sufficient, the circuit configuration becomes simpler if it is configured as an external circuit that operates with a separate power source, so the timing generation circuit 60 is intentionally used.
Are not formed on the same substrate.

[0051]

According to the present invention described above, the timing pulse which is repeated in the horizontal direction and the timing pulse which is repeated in the vertical direction are obtained from separate ROMs.
The amount of data written in the ROM can be reduced and R
The capacity of the OM can be significantly reduced. Note that RO
Since the timing pulse is obtained from M, ROM
It is possible to easily change and correct the timing pulse only by changing the data.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a timing generation circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a horizontal ROM circuit according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a horizontal ROM circuit according to an embodiment of the present invention.

FIG. 4 is a diagram for explaining the example of FIG. 3;

FIG. 5 is a diagram showing data in an address ROM according to the embodiment of the present invention.

FIG. 6 is a diagram showing data in a data ROM according to the embodiment of the present invention.

FIG. 7 is a configuration diagram of a horizontal ROM circuit according to an embodiment of the present invention.

FIG. 8 is a configuration diagram of a vertical ROM circuit according to an embodiment of the present invention.

FIG. 9 is a configuration diagram of a phase adjusting unit according to an embodiment of the present invention.

FIG. 10 is a configuration diagram of a horizontal clock driver according to an embodiment of the present invention.

FIG. 11 is a configuration diagram of an inverter according to an embodiment of the present invention.

FIG. 12 is a configuration diagram of a CCD solid-state imaging device according to an embodiment of the present invention.

FIG. 13 is a configuration diagram of a conventional CCD solid-state imaging device.

FIG. 14 is a diagram showing a conventional vertical transfer clock.

FIG. 15 is a diagram showing a relationship between a conventional light receiving section, a transfer gate, and a vertical shift register.

FIG. 16 is an explanatory diagram of a conventional vertical shift register.

FIG. 17 is an explanatory diagram of a conventional vertical shift register.

FIG. 18 is a diagram showing a conventional horizontal transfer clock and the like.

FIG. 19 is a configuration diagram of a conventional CCD solid-state imaging device.

FIG. 20 is a configuration diagram of an example of a conventional timing generation circuit.

[Explanation of symbols]

60 timing generation circuit, 64 synchronization circuit, 65 horizontal ROM circuit, 68 vertical clock circuit, 69 vertical RO
M circuit, 74 Phase adjustment circuit, 781, 782 Horizontal clock driver

Claims (1)

[Claims] 1. A first address counter controlled by a first reference pulse of a horizontal cycle, and a first ROM whose read address is controlled by an output of the first address counter.
Means, a second address counter controlled by a second reference pulse having a frequency sufficiently higher than the horizontal frequency, and a second ROM means in which the read address is controlled by the output of the second address counter. And has the above first
A timing pulse generation circuit for obtaining a first timing pulse and a second timing pulse from the ROM means and the second ROM means, respectively, wherein the second ROM means stores logical level data. A first ROM and a second ROM in which holding period data representing a period for holding the level of the logic level data is stored.
Of the ROM is controlled to generate the second timing pulse, the second address counter counts the second reference pulse, and the second ROM
A first counter for generating an output pulse based on an output result from the second counter, and a second counter controlled by an output from the first counter.
And a timing pulse generation circuit in which the address of the first ROM and the address of the second ROM are controlled by the output of the second counter.