JPH09205085A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure an active region having specified width without increasing the number of steps or cost by removing an insulation film from the reactive region by etching. SOLUTION: An oxide 105 and a nitride 104 are deposited on a semiconductor substrate 101. The oxide 105 and nitride 104 are then removed from an isolation region 103 such that they are left only in an active region 102. The semiconductor substrate 101 is then oxidized to form an isolation oxide 106 and the nitride 104 is removed from the active region 102. Subsequently, the oxide 106 is removed completely, by etching, from the active region 102 and an active region having a specified width is formed with an isolation region 103 being formed by the remaining oxide 106. According to the method, a fine isolation region can be formed without increasing the number of steps.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a method of manufacturing a semiconductor device using the LOCOS oxidation method.

[0002]

2. Description of the Related Art Conventionally, a LOCOS oxidation method has been used as a method for forming an element isolation region on a semiconductor substrate.
The LOCOS oxidation method will be described with reference to FIGS. 5A to 5C, but before that, the configuration shown in the figure will be described. In these drawings, 101 is a semiconductor substrate, 102 is an active portion, 103 is an element isolation region, 104 is a nitride film serving as a mask for element isolation, and 105 is a stress formed in the substrate after forming an oxide film. Is an oxide film as a pad oxide film, and 106 is an oxide film as an insulating film for element isolation.

To explain the LOCOS oxidation method, first, as shown in FIG. 5 (a), an oxide film 105 is deposited on the semiconductor substrate 101 by, for example, 10 nm, and then a nitride film 104 is deposited by 200 nm, for example. After that, for example, by masking with a photoresist and dry etching, the oxide film 105 and the nitride film 104 are left in the region to be the active portion 102, and the element isolation region 10 is formed.
For No. 3, the oxide film 105 and the nitride film 104 are removed.

Next, the semiconductor substrate 101 is heated in a mixed atmosphere of oxygen and hydrogen to oxidize it. At this time, as shown in FIG.
1 where the nitride film 104 is deposited (active portion 102)
Is not oxidized, but the region (element isolation region 103) from which the nitride film 104 has been removed is selectively oxidized to form an oxide film 106 as an element isolation insulating film.

After that, as shown in FIG. 5C, the nitride film 104 and the oxide film 1 thereunder are wet-etched.
05 is removed, and the active portion 102 is formed on the surface of the semiconductor substrate 101.
And the element isolation region 103 are formed. A method of forming the element isolation portion 103 on the surface of the semiconductor substrate 101 in this manner is a LOCOS oxidation method.

By the way, in the CMOS device, after the element isolation region 103 is formed on the surface of the semiconductor substrate 101,
Well implantation for forming an impurity region of the same or opposite conductivity type as the semiconductor substrate 101 in the semiconductor substrate 101, punch-through stop implantation for locally forming a high concentration impurity region to suppress the short channel effect of a transistor, Channel stop implantation for forming a high-concentration impurity region for improving the isolation voltage by increasing the impurity concentration locally so as not to short-circuit the source / drain of adjacent elements and suppressing the expansion of the depletion layer from both sides. And Vt implantation for threshold value adjustment and the like are performed.

This injection step will be described with reference to FIGS. 6 (a) to 6 (c). First, as shown in FIG. 6A, after forming the element isolation region 103 on the surface of the semiconductor substrate 101,
The active portion 10 is formed by oxidizing the semiconductor substrate 101.
A protective oxide film 109 having a thickness of, for example, about 10 nm is formed on the second surface. The protective oxide film 109 is formed to prevent impurities from being mixed into the semiconductor substrate 101 during the subsequent ion implantation 110 or to prevent the introduction of defects by the ion implantation 110.

Next, as shown in FIG. 6B, various ion implantations are performed.

Thereafter, as shown in FIG. 6C, the protective oxide film 109 is removed by wet etching to expose the surface of the semiconductor substrate 101 again. Especially oxide film 106
6B, the peak position 111 of the impurity concentration distribution is located immediately below the oxide film 106 so as to have the effect as a channel stopper, and a transistor formed later may be used. The purpose of simplifying the process is to also serve as a punch through stop for suppressing the short channel effect.

[0010]

However, in the formation of the element isolation region 103 by the LOCOS oxidation method as described above, as shown in FIG. 5B, the nitride film 104 is formed.
So-called bird's beak 1 that is oxidized just below the edge of the
Since it contains 08, if you aim for miniaturization, this bird's beak 1
The length of 08 cannot be ignored as compared with the separation width, which causes a problem that it is difficult to achieve miniaturization. For example, the separation width is 0.25 μm, the nitride film thickness is 200 nm,
If the oxide film thickness is 400 nm, the length of the bird's beak 108 becomes 0.13 μm or more, and the bird's beak 108 enters the entire surface of the active portion 102, so that the nitride film 104 is completely pushed up by the oxide film 106 and floats.
Therefore, even after the nitride film 104 is removed, the active portion 10
The surface of the semiconductor substrate 101 in the region 2 becomes the oxide film 106.
, Which makes it difficult to form an element in that region.

Therefore, in recent years, in order to shorten the length of the bird's beak 108, as shown in FIG.
A sidewall 10 made of a nitride film 104 or the like on the sidewall 4
A method of forming 7 before oxidation has been proposed. However, this method increases the steps such as the deposition of the nitride film 104 and the etch back, and therefore, a simple LOCOS is required.
There is a problem that the cost increases as compared with the oxidation method. Further, when such a side wall 107 is used, both ends are pressed by the side wall 107, so that there arises a problem that the oxide film 106 cannot be formed to a sufficiently desired thickness. .

On the other hand, in the CMOS device, the formation of the protective isolation film 109 for ion implantation for various purposes subsequent to the formation of the element isolation region 103 is
There is a problem that the cost is increased because the number of steps is increased.

Further, as shown in FIG. 8, when the wide element isolation region 113 and the narrow element isolation region 114 are formed, the narrow element isolation region 114 is kept while suppressing the junction leak. In order to secure the isolation breakdown voltage of the element isolation region 11 having a large width, a mask process for masking the element isolation region 113 having a large width with the resist mask 112 is increased, and the element isolation region 11 having a narrow width is formed.
Therefore, it is necessary to additionally perform the channel stop implantation 115 only on the fourth channel.

Similarly, in a DRAM, for example, as shown in FIG. 9, memory cell portion 117 pulls the substrate bias negative in order to secure its charge retention characteristic, while peripheral circuit portion 116 operates at high speed. Therefore, the substrate bias is not subtracted. At this time, since the substrate bias is not drawn in the peripheral circuit section 116, a sufficient isolation breakdown voltage cannot be secured with the same channel stop injection amount as in the memory cell section 117. Therefore, the memory cell portion 117 is set to the resist mask 11
Adopting the mask process of masking with 2, the peripheral circuit section 1
Only 16 need to perform an additional channel stop implant 119. In these cases, there is a problem that the cost increases because the number of steps increases, or the separation width must be designed wide in order to suppress the number of steps, and eventually the chip size increases.

The present invention has been made in view of the above points, and an object thereof is to provide sufficient element isolation capability, various types of injection such as well injection, and a channel stop injection amount without increasing the number of steps. It is to provide a method of manufacturing a semiconductor device that can be changed.

[0016]

In order to achieve the above object, in the first means for solving the problems of the present invention, first, an oxide film and a nitride film are sequentially deposited on a semiconductor substrate. Next, the oxide film and the nitride film in the element isolation region are removed so that the oxide film and the nitride film remain only in the region that becomes the active portion. Then, the semiconductor substrate is oxidized to form an insulating film for element isolation, and then the nitride film in the region to be the active portion is removed. After that, by etching the insulating film, the insulating film is removed so that the insulating film does not remain in the region that becomes the active portion to form an active portion of a predetermined width, and the remaining insulating film forms the element isolation region. It is characterized by forming.

A second solving means of the present invention is characterized in that, in the first solving means, after the nitride film in the region which becomes the active portion is removed, ion implantation is carried out to the insulating film on the semiconductor substrate.

According to a third solution of the present invention, in a method of manufacturing a semiconductor device in which element isolation regions having different widths are formed on a semiconductor substrate, first, an oxide film and a nitride film are sequentially deposited on the semiconductor substrate. . Then, the oxide film and the nitride film in the element isolation regions having different widths are removed so that the oxide film and the nitride film remain only in the region that becomes the active portion. Then, the semiconductor substrate is oxidized to form an element isolation insulating film, and then the nitride film in the active region is removed. After that, the peak position of the impurity concentration distribution is located below the insulating film in the narrow element isolation region, while in the wide element isolation region, the implantation energy existing in the insulating film causes the first element isolation region to be separated. Perform the first channel stop injection. After that, the second channel stop implantation for element isolation is performed with the implantation energy where the peak position of the impurity concentration distribution is located below both insulating films of the wide element isolation region and the narrow element isolation region. Is characterized by.

According to a fourth solution of the present invention, in a method of manufacturing a semiconductor device in which element isolation regions having different widths are formed on a semiconductor substrate, first, an oxide film and a nitride film are sequentially deposited on the semiconductor substrate. . Then, the oxide film and the nitride film in the element isolation regions having different widths are removed so that the oxide film and the nitride film remain only in the region that becomes the active portion. Then, the semiconductor substrate is oxidized to form an element isolation insulating film, and then the nitride film in the active region is removed. After that, the first channel stop implantation for element isolation is performed with the implantation energy whose peak position of the impurity concentration distribution is located below both insulating films of the wide element isolation region and the narrow element isolation region. . After that, the peak position of the impurity concentration distribution is located below the insulating film in the narrow element isolation region, while in the wide element isolation region, the second element isolation region is formed by the implantation energy existing in the insulating film. It is characterized in that the channel stop injection is performed for the second time.
That is, the fourth solution means is the same as the third solution means except that the step of channel stop implantation is reversed.

According to a fifth solution of the present invention, in a method of manufacturing a semiconductor device in which element isolation regions having different widths are formed on a semiconductor substrate, first, an oxide film and a nitride film are sequentially deposited on the semiconductor substrate. . Then, the oxide film and the nitride film in the element isolation regions having different widths are removed so that the oxide film and the nitride film remain only in the region that becomes the active portion. Then, the semiconductor substrate is oxidized to form an element isolation insulating film, and then the nitride film in the active region is removed. Then, the first channel stop implantation for element isolation is performed with the implantation energy where the peak position of the impurity concentration distribution is located below both insulating films in the wide element isolation region and the narrow element isolation region. After that, the both insulating films are flattened. After that, the second channel stop implantation for element isolation is performed with the implantation energy where the peak position of the impurity concentration distribution is located below both insulating films in the wide element isolation region and the narrow element isolation region. Characterize.

With the above arrangement, in the first solution means of the present invention, the number of steps is increased and the cost is not increased.
A fine element isolation region can be formed on the surface of the semiconductor substrate.

In the second solving means of the present invention, the mixture of impurities and the introduction of defects at the time of ion implantation subsequent to the formation of the element isolation region are suppressed without increasing the number of steps.

In the third to fifth means for solving the problems of the present invention, different channel stop implantation can be performed for each region without employing a mask process which causes an increase in the number of processes.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1A to 1D are process drawings of a manufacturing method according to a first embodiment of the present invention. To explain the manufacturing procedure, first, FIG. ), An oxide film 105 for reducing stress after oxidation and a nitride film 104 are sequentially deposited on a semiconductor substrate 101, and then the oxide film 105 and the nitride film 104 are formed only in a region to be an active portion 102. The oxide film 105 in the element isolation region 103 is left so as to remain.
Then, the nitride film 104 is removed, and a nitride film mask region for element isolation using the LOCOS oxidation method is formed.

Then, the semiconductor substrate 101 is oxidized in a mixed gas of hydrogen and oxygen at about 1100 ° C. for about 2 hours. As a result, as shown in FIG.
The region without 4 is oxidized and an oxide film 106 is formed as an insulating film for element isolation. At this time, the so-called bird's beak 10 is slightly oxidized just below the edge of the nitride film 104.
8 will be included. As the device becomes finer, the active portion 102
When the area of ² is reduced to, for example, about 0.5 um ² , the amount of the bird's beak 108 entering relatively increases and reaches almost the central portion of the nitride film 104.
Is almost lifted by the oxide film 106.

Thereafter, as shown in FIG. 1C, after forming the oxide film 106, the active portion 10 used as a mask.
The second nitride film 104 is removed by, for example, wet etching.

After that, as shown in FIG. 1D, the oxide film 106 is etched. As a result, the oxide film 10
The film thickness of 6 decreases. This wet etching time is based on the oxide film 1 used to reduce stress in the past.
Compared with the case of removing 04, the bird's beak 108 extended for about 2 minutes and expanded into the area of the active portion 102.
The oxide film 106, which is the invasion part of the
The surface of the semiconductor substrate 101 at 02 is exposed. As a result, the oxide film 106 recedes, and the active portion 102
Area can be ensured to be a predetermined width, and the element isolation region 103 can be formed by the remaining oxide film 106.

Therefore, in the first embodiment, the oxide film 106 can be made to reach a desired film thickness sufficiently as compared with the case where a minute element isolation is formed by using a sidewall for a nitride film, As a result, it is possible to form a semiconductor element isolation that is fine and can provide a sufficient isolation breakdown voltage without increasing the number of steps.

(Second Embodiment) FIGS. 2 (a) to 2 (e) are process drawings of a manufacturing method according to a second embodiment of the present invention. To explain the manufacturing procedure, first, FIG. ), An oxide film 105 for reducing stress after oxidation and a nitride film 104 are sequentially deposited on a semiconductor substrate 101, and then the oxide film 105 and the nitride film 104 are formed only in a region to be an active portion 102. The oxide film 105 in the element isolation region 103 is left so as to remain.
Then, the nitride film 104 is removed, and a nitride film mask region for element isolation using the LOCOS oxidation method is formed.

Then, the semiconductor substrate 101 is oxidized in a mixed gas of hydrogen and oxygen at about 1100 ° C. for about 2 hours. As a result, as shown in FIG.
The region without 4 is oxidized and an oxide film 106 is formed as an insulating film for element isolation. At this time, the so-called bird's beak 10 is slightly oxidized just below the edge of the nitride film 104.
8 will be included. As the device becomes finer, the active portion 102
When the area of ² is reduced to, for example, about 0.5 um ² , the amount of the bird's beak 108 entering relatively increases and reaches almost the central portion of the nitride film 104.
Is almost lifted by the oxide film.

Thereafter, as shown in FIG. 2C, after forming the oxide film 106, the active portion 10 used as a mask.
The nitride film 104 in the region to be 2 is removed by, for example, wet etching.

After that, as shown in FIG. 2D, after removing the nitride film 104 in the region to be the active portion 102, ion implantation 301 is performed on the oxide film 106 on the semiconductor substrate 101. That is, after the nitride film 104 is removed, the oxide film 10 in the state where the bird's beak 108 is formed is subsequently formed.
Ion implantation for well formation, punch through stop formation, channel stop formation and threshold voltage control is carried out using 6 as it is as a protective oxide film for preventing impurity mixture and defect introduction.

After that, as shown in FIG. 2 (e),
After performing the ion implantation 301, the oxide film 106 is made to recede by wet etching as in the first embodiment, the oxide film 106 formed in the active portion 102 is removed, and the surface of the semiconductor substrate 101 of the active portion 102 is exposed. Let Particularly, by utilizing the film thickness of the oxide film 106, as shown in FIG. 2D, the peak position 111 of the impurity concentration distribution is set to the oxide film 106.
In order to simplify the process, it is possible to position the substrate immediately below the substrate to serve as a channel stopper while also serving as a punch through stop for suppressing a short channel effect of a transistor to be formed later. This is the same as that described in (b).

As described above, in the second embodiment, the bird's beak 108 is deliberately infiltrated so that the region to be the active portion 102 is sufficiently covered with the oxide film 106, whereby the ion implantation 301 is performed. The cost can be reduced by eliminating the protective oxidation step performed before the step.

(Third Embodiment) FIGS. 3A to 3E are process drawings of a manufacturing method according to a third embodiment of the present invention. To explain the manufacturing procedure, first, FIG. ), An oxide film 105 for reducing stress after oxidation and a nitride film 104 are deposited on the semiconductor substrate 101, and the nitride film 104 and the oxide film 105 are left in the region to be the active portion 102.
By removing both of the element isolation regions 103, a nitride film mask region for element isolation using the LOCOS oxidation method is formed. It is assumed that elements having different isolation widths exist in the semiconductor substrate 101, and are roughly divided into a wide element isolation region 113 and a narrow element isolation region 114.

Next, as shown in FIG. 3 (b), the semiconductor substrate 101 is heated to about 110 in a mixed gas of hydrogen and oxygen, for example.
It is oxidized at 0 ° C. for about 2 hours. As a result, the region without the nitride film 104 is oxidized, and the oxide film 1 is used as an insulating film for element isolation.
06 will be formed.

After that, as shown in FIG. 3C, the nitride film used as the oxidation mask is removed by wet etching. The oxide film 106, which is an element isolation insulating film, has a film thickness of a wide element isolation region 113 and a narrow element isolation region 11.
3C, in FIG. 3C, the film thickness of the wide element isolation region 113 is Tox1, and the narrow element isolation region 11 is
The film thickness of No. 4 is indicated by Tox2. Then, for example, the element isolation width of the wide element isolation region 113 is 1.0 μm, and the element isolation width of the narrow element isolation region 114 is 0.3 μm.
In the case of um, the film thickness Tox2 of the oxide film 106 in the element isolation region 114 having a narrow width is equal to that of the element isolation region 11 having a large width.
The film thickness Tox1 of the oxide film 106 of No. 3 is reduced to about 70%.

Then, as shown in FIG. 3D, after removing the nitride film 104, a first channel stop implantation 115 is performed in order to improve the element isolation breakdown voltage.
The acceleration energy of this ion implantation is set so that the peak 403 of the impurity concentration distribution is located immediately below the oxide film 106 formed in the narrow element isolation region 114. At this time, in the wide element isolation region 113, the peak position 403 of the concentration distribution of the impurities introduced by this ion implantation.
Is located in the oxide film 106, and the semiconductor substrate 1
The concentration of impurities reaching 01 is 1/100 or less.
That is, the channel stopper is introduced only in the narrow element isolation region 114.

After that, as shown in FIG. 3E, a second channel stop implantation 404 is successively performed in order to improve the breakdown voltage of the element isolation formed in the wide element isolation region 113. The energy of this ion implantation is set so that the peak 405 of the impurity concentration distribution is located immediately below the oxide film 106 formed in the wide element isolation region 113. At this time, in the narrow element isolation region 114, the peak position 405 of the concentration distribution of the impurities introduced by this ion implantation becomes considerably deeper than the bottom of the oxide film 106, so that a channel stop for element isolation in this region is formed. Has no effect as Therefore, it is possible to prevent the concentration from increasing more than necessary and increasing the junction leak at the separation portion.

As described above, in the third embodiment, by utilizing the difference in the film thickness of the insulating oxide film due to the difference in the element isolation width, different positions can be obtained without adding a mask process. It is possible to perform a plurality of channel stop injections in which the peak position of the concentration is set.

The same result can be obtained by reversing the ion implantation steps of the first channel stop implantation 115 and the second channel stop implantation 404 performed in the third embodiment. Is something that can be done. Further, similar results can be obtained when the number of types of isolation widths of the element isolation regions is more than two.

(Fourth Embodiment) FIGS. 4A to 4D are process diagrams of a manufacturing method according to a fourth embodiment of the present invention. To explain the manufacturing procedure, first, FIG. ), In the DRAM, an oxide film 106 which is an insulating film for element isolation is formed. Since the steps up to the formation of the oxide film 106 are the same as those in the third embodiment, the steps up to that point are omitted. Then, the film thickness Tox1 of the oxide film 106 in the peripheral circuit portion 116 having a generally wide element isolation width becomes thicker than the film thickness Tox2 of the oxide film 106 in the memory cell portion 117. For example, the element isolation width in the peripheral circuit section 116 is 1.0
um, the element isolation width of the memory cell section 117 is 0.25 um
In this case, the film thickness Tox2 is about 7 compared to the film thickness Tox1.
0%.

Next, as shown in FIG. 4B, the first channel stop implantation 119 is performed. The implantation energy is set so that the peak position 501 of the impurity concentration distribution is located directly below the oxide film 106 of the peripheral circuit section 116. At this time, in the memory cell portion 117, the film thickness Tox2 of the oxide film 106 is thin, so that the peak position 5 of the impurity concentration distribution is 5.
01 is located considerably deeper than the bottom of the oxide film 106 and does not affect the element isolation region of the memory cell part 117.

After that, as shown in FIG. 4C, in order to improve the processing accuracy in the subsequent process, the surface of the semiconductor substrate 101 is subjected to, for example, CMP (chemical mechanical) after element isolation formation.
polishing) method or the like.

Then, as shown in FIG. 4D, the second
The channel stop injection 503 is performed for the second time. The energy of this ion implantation is the oxide film 1 of the memory cell portion 117.
It is set so that the peak 504 of the impurity concentration distribution is located immediately below 06. In general, between the narrow element isolation width and the wide element isolation width, the difference in film thickness is due to the difference in the film thickness above the substrate surface, and the film thickness of the oxide film present in the substrate is Almost independent of element isolation width. Therefore, although the peak position 504 of the impurity concentration distribution of the second channel stop implantation 503 is set in accordance with the narrow element isolation of the memory cell section 117, the peripheral circuit section 116 also has the element isolation oxide film 106. Will be located immediately below, and the channel separation for element isolation of the peripheral circuit section 116 will be the same as that performed a total of two times including the first time.

By the way, in the DRAM, the memory cell unit 1
The substrate potential of 17 is kept at a slightly negative potential to improve its charge retention characteristics, and the source / drain regions of the transistors serving as the transfer gates of the memory cell portion 117 have a low concentration. Since the channel stop concentration of 117 is required to reduce the junction leak, the impurity concentration is set as low as possible for the channel stop of the memory cell portion 117. However, in the peripheral circuit section 116, the substrate potential is set to 0 V because the circuit operates at high speed. Therefore, the isolation breakdown voltage becomes low. Therefore, in order to improve the isolation breakdown voltage, it is necessary to additionally perform channel stop implantation. Therefore,
By using this embodiment, it is possible to increase the concentration of only the peripheral circuit unit 116 and improve the breakdown voltage while suppressing the memory cell unit 117 to the required minimum channel stop concentration without any masking step.

In each of the above embodiments, the same effect can be obtained not only when the nitride film used as the oxidation mask has a multi-layer structure such as a two-layer structure of a nitride film and polycrystalline silicon, but not only the nitride film single layer. Is something that can be done. Further, the same effect can be obtained without the stress reducing oxide film.

[0049]

As described above, according to the first aspect of the present invention, the insulating film is removed by etching so that the insulating film does not remain in the region that becomes the active portion.
The bird's beaks that enter when forming fine separations by the OS oxidation method can be set back from the region serving as the active portion, without increasing the number of steps and increasing the cost.
The width of the active portion can be ensured to be a predetermined width.

According to the second aspect of the present invention, after the nitride film in the region which becomes the active portion is removed, ions are implanted into the insulating film on the semiconductor substrate, so that the element isolation region can be formed without increasing the number of steps. It is possible to suppress the introduction of impurities and the introduction of defects during the subsequent ion implantation.

According to the present invention of claims 3 to 5, since the peak position of the impurity concentration portion with respect to the element isolation regions having different widths is controlled by the channel stop implantation, the mask process which increases the number of processes is adopted. Instead, different channel stop implants can be performed for each region.

[Brief description of drawings]

1A to 1D are manufacturing process diagrams of a semiconductor device according to a first embodiment.

2A to 2E are manufacturing process diagrams of a semiconductor device according to a second embodiment.

3A to 3E are manufacturing process diagrams of a semiconductor device according to a third embodiment.

4A to 4D are manufacturing process diagrams of a semiconductor device according to a fourth embodiment.

5A to 5C are manufacturing process diagrams of a conventional semiconductor device.

6A to 6C are manufacturing process diagrams of a semiconductor device having an ion implantation process of a conventional example.

FIG. 7 is a process drawing of a sidewall formation on an end portion of a nitride film in a manufacturing process of a semiconductor device.

FIG. 8 is a channel stop implantation process diagram when the element isolation regions have different widths.

FIG. 9 is a channel stop injection process diagram for a peripheral circuit portion in a DRAM.

[Explanation of symbols]

101 semiconductor substrate 102 active part 103 element isolation region 104 nitride film 105 oxide film 106 oxide film (insulating film for element isolation) 108 bird's beak 111 peak position of impurity concentration distribution 113 wide element isolation part formation region 114 narrow element isolation Part forming region 115,119 First channel stop implantation 301 Ion implantation 403, 405, 501, 504 Impurity concentration distribution peaks 404, 503 Second channel stop implantation

Claims (5)

[Claims] 1. An oxide film and a nitride film are sequentially deposited on a semiconductor substrate, and then the oxide film and the nitride film in an element isolation region are removed so that the oxide film and the nitride film remain only in a region serving as an active portion. After that, the semiconductor substrate is oxidized to form an insulating film for element isolation, and then the nitride film in the region to be the active portion is removed, and then the insulating film is etched to form a region to be the active portion. A method of manufacturing a semiconductor device, comprising: removing an insulating film so that an insulating film does not remain on the substrate, forming an active portion having a predetermined width, and forming an element isolation region with the remaining insulating film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein after the nitride film in the region to be the active portion is removed, ions are implanted into the insulating film on the semiconductor substrate. 3. A method of manufacturing a semiconductor device in which element isolation regions having different widths are formed on a semiconductor substrate, wherein an oxide film and a nitride film are sequentially deposited on the semiconductor substrate, and then the oxide film and the nitride film are formed. The oxide film and the nitride film in the element isolation regions having different widths are removed so that the film remains only in the active region, and then the semiconductor substrate is oxidized to form an element isolation insulating film, and then the active layer is removed. After that, the nitride film in the region to be formed is removed, and thereafter, the peak position of the impurity concentration distribution is located below the insulating film in the narrow element isolation region, while it is located in the insulating film in the wide element isolation region. The first channel stop implantation for element isolation is performed by the existing implantation energy, and then the peak position of the impurity concentration distribution is located below both insulating films in the wide element isolation region and the narrow element isolation region. The method of manufacturing a semiconductor device characterized by an implantation energy of location perform a second round of channel stop implantation for isolation. 4. A method of manufacturing a semiconductor device in which element isolation regions having different widths are formed on a semiconductor substrate, wherein an oxide film and a nitride film are sequentially deposited on the semiconductor substrate, and then the oxide film and the nitride film are formed. The oxide film and the nitride film in the element isolation regions having different widths are removed so that the film remains only in the active region, and then the semiconductor substrate is oxidized to form an element isolation insulating film, and then the active layer is removed. After removing the nitride film in the region to be isolated, the peak position of the impurity concentration distribution is separated by the implantation energy located below both insulating films in the wide element isolation region and the narrow element isolation region for element isolation. The first channel stop implantation is performed, and then the peak position of the impurity concentration distribution is located below the insulating film in the narrow element isolation region, while it is located in the insulating film in the wide element isolation region. The method of manufacturing a semiconductor device characterized by an implantation energy of standing performing the second channel stop implantation for isolation. 5. A method of manufacturing a semiconductor device in which element isolation regions having different widths are formed on a semiconductor substrate, wherein an oxide film and a nitride film are sequentially deposited on the semiconductor substrate, and then the oxide film and the nitride film are formed. The oxide film and the nitride film in the element isolation regions having different widths are removed so that the film remains only in the active region, and then the semiconductor substrate is oxidized to form an element isolation insulating film, and then the active layer is removed. After removing the nitride film in the region to be isolated, the peak position of the impurity concentration distribution is separated by the implantation energy located below both insulating films in the wide element isolation region and the narrow element isolation region for element isolation. After the first channel stop implantation is performed, the both insulating films are flattened, and thereafter, the peak positions of the impurity concentration distribution are determined to be wide in the element isolation region and narrow in the element isolation region. Below The method of manufacturing a semiconductor device characterized by an implantation energy of location perform a second round of channel stop implantation for isolation.