JPH09191104A - Single electronic element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enclose carriers in quantum dots even at a high temperature by forming tunnel barriers having narrow widths and large energy barriers in the top cover of a V-groove. SOLUTION: A source 106 and a drain 107 exist at the end section of a thin silicon wire 100 and a gate 108 exists on the silicon wire 100 with an insulating film 104 in between. Two V-grooves 105 are formed at the central part of the top cover of the silicon wire 100 so that the wire 100 cannot be cut by the grooves 105. An inverted layer in the small area between the grooves 105 becomes a quantum dot structure between potential barriers. The grooves 105 have sharp shapes at their bottom sections and, since the potential barriers formed in the bottom sections have small widths, electrons supplied from the source 106 can tunnel to the quantum dot structure. In addition, the electrons injected into quantum dots can tunnel to the drain 107 side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single electronic device, and more particularly to a single electronic device that operates by moving one electron.

[0002]

2. Description of the Related Art Conventionally, a single electronic device capable of operating at a high temperature and having a controlled microstructure is known (Y. Takahash
i et.al, IEDM Technical Digest, p. 938, 1994). FIG. 6 shows a configuration diagram of an example of a conventional single-electron element described in this document. FIG. 6 (a) is a top view and FIG. 6 (b) is FIG.
FIG. 3A is a sectional view taken along line AA ′ of FIG.

As shown in FIGS. 1A and 1B, in order to manufacture this conventional single electronic device, first, an insulating film 604 is formed on a semiconductor substrate 605, and a single film is further formed thereon. 30nm thick SOI with crystalline silicon film
After forming the source 601 and the drain 603 by a known method using the substrate, the source 601 and the drain 603 are formed.
And a length of 50 nm between the source 601 and the drain 603,
Thermal processing is performed after processing a thin wire having a width of 30 nm by using plasma etching. This thermal oxidation is for narrowing the width of the thin wire end with respect to the central portion of the thin wire and for the gate 602 formed later
This is done to prevent short circuit between the wire and the thin wire.

Due to this thermal oxidation, the center of the thin line portion between the source 601 and the drain 603 is 606 in FIGS. 6 (a) and 6 (b).
As shown by, due to the stress associated with the volume expansion during the thermal oxidation, the oxidation rate is small, and the thin wire has a shape in which the center swells in the width direction and the thickness direction, respectively. After that, the gate 602 is formed through the insulating film 604 by a known method.

In this structure, when a voltage is applied to the gate 602 to induce an inversion layer in the thin wire, the thin wire central portion 60
Since the oxide film thickness is thicker at the thin wire end than in No. 6, the threshold voltage becomes larger. In addition, the fine wire has a smaller fine line width and is more likely to be pinched off than the fine line central portion 606. Therefore, the end of the thin line acts as a potential barrier, and a quantum dot is formed in the central part 606 of the thin line. Since the size of this quantum dot is as small as several tens of nm, electrostatic energy is relatively large, and Coulomb oscillation is observed even at room temperature.

[0006]

In the conventional single-electron device described above, the width of the thin wire end is narrowed with respect to the thin wire central portion 606 by utilizing the stress associated with the thermal oxidation, so that the potential barrier is provided in this region. Had formed. However, since this region has a spread of several tens of nm or more and a wide potential barrier width, tunneling in the barrier was impossible unless the barrier height was low. For this reason, there is a problem in that the trapping of charges in the quantum dots is incomplete, which makes it difficult to operate the device at high temperatures.

[0007] The present invention has been made in view of the above points,
It is an object of the present invention to provide a single electronic device capable of high temperature operation and miniaturization.

[0008]

In order to achieve the above object, a single electronic device of the present invention has a semiconductor layer on a first insulator layer and a second semiconductor layer overlying the semiconductor layer. In the single-electron device in which the semiconductor layer is present, the gate is formed on the second insulating layer, and the drain and the source are formed in the semiconductor layer, the semiconductor layer has a plurality of V The structure is such that it is processed into a thin wire having a groove, and at least one of the width and the thickness of the thin wire is smaller in the V groove portion than in the peripheral portion.

Here, the V groove is formed so as not to cut the thin wire or so as to cut the thin wire. Further, the fine line may have a high impurity concentration and degenerate, and the fine line may be cut by the V groove.

In the present invention, at least one of the width and the thickness of the fine line is smaller in the V groove portion of the semiconductor layer processed into the fine line shape than in the peripheral portion, so that the width of the V groove apex portion is narrow and energy is reduced. A tunnel barrier having a large barrier can be formed, and the facing area between the quantum dot and the thin line portion sandwiching the tunnel barrier can be reduced.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a block diagram of a first embodiment of a single electronic device according to the present invention, in which FIG.
The figure (b) shows the sectional view on the AA 'line of the figure (a). A silicon thin wire 100 having a width of several nm to several 100 nm and a length of several nm to several μm, which is obtained by processing an SOI substrate having a thickness of several nm to several hundred nm in which an insulating film 102 is formed on a semiconductor substrate 101. A source 106 and a drain 107 made of an n ⁺ diffusion layer are present at the ends, and further, on the thin wire 100 via an insulating film 104 having a thickness of several nm to several 100 nm.
There is a gate 108.

The gate 108 overlaps the source 106 and the drain 107. On the upper surface of the central part of the thin wire 100, V having a width and a depth of several nm to several hundred nm is formed.
Two grooves 105 are formed at intervals of several nm to several 100 nm. In addition, the V-groove 105 allows the thin wire 1
00 has a structure that is not cut.

The above structure can be realized by the following manufacturing method. First, as shown in FIG. 1B, an insulating film 102 is formed on a semiconductor substrate 101, and a thickness of several nm to several 100 nm and a boron concentration of 10 ¹⁴ to 10 10 are formed on the insulating film 102.
S with an upper silicon layer of ¹⁸ cm ^-3 and plane orientation (100)
An OI substrate is prepared. Next, the upper silicon layer of the SOI substrate is oxidized to form a silicon oxide film having a thickness of several nm to several tens nm.

Next, a positive resist for electron beam drawing is applied on the silicon oxide film, and electron beam irradiation is performed to form a pattern having a width of several nm to several 100 nm and a length width of several nm to several 100 nm, to several nm. Two lines are drawn at intervals of several hundred nm. However, the direction of the fine line must be exactly aligned with the (110) direction. Using the positive resist as a mask, the silicon oxide film on the upper silicon layer is removed by reactive ion etching (RIE), and then the positive resist is removed.

Thereafter, the upper silicon layer (semiconductor substrate 103) is etched using hydrazine with the silicon oxide film masked with the positive resist as a mask. Hydrazine is an anisotropic etchant, (1
The etching rates of the (00) plane and the (110) plane are (11
Since it is significantly larger than the 1) plane, the V-groove structure 105 shown in FIG. 1 having the (111) plane as the side surface is formed. Since the angle of the apex of the V groove 105 is fixed at 70 degrees, it is possible to prevent the apex of the V groove 105 from reaching the lower portion of the upper silicon layer (semiconductor substrate 103) by adjusting the electron beam drawing width. It is possible.

Next, the upper silicon layer (semiconductor substrate 10
3) After removing the upper silicon oxide film with HF, a negative electron beam resist is applied on the upper silicon layer and electron beam irradiation is performed to obtain a width of several nm to several 100 nm and a length of several nm. A resist pattern of several μm is formed so as to be orthogonal to the V groove structure.

Next, using this resist pattern as a mask, the upper silicon layer (semiconductor substrate 103) is formed by RIE.
Is processed to form a silicon thin wire. After that, the thin silicon wire is thermally oxidized by several nm to several tens of nm to cover the entire thin silicon wire with a silicon oxide film (insulating film 104). However, by adjusting the amount of oxidation, it is necessary to prevent the silicon thin wire from being cut at the V groove forming portion.

Next, a resist is applied, and patterning is performed by electron beam or photolithography so that the resist remains only in the central portion of the fine line. Then, using the resist as a mask, n-type impurities of phosphorus (P) or arsenic (As) are ion-implanted to form n ⁺ -type regions at the ends of the thin wires, and the source 106 and the drain 107 are formed. Then 900 ° C
Nitrogen (N ₂ ) for 10 to 60 minutes at a temperature of ~ 1100 ° C
By annealing in the atmosphere, the implanted ions in the source 106 and the drain 107 are activated.
After that, aluminum (Al) is vapor-deposited to a thickness of about 100 to 1000 nm, a resist is patterned by electron beam or photolithography, and then aluminum is processed by RIE to form a gate 108.

Next, the device operation in the first embodiment will be described. When a positive voltage is applied to the gate 108, an inversion layer is induced on the surface of the silicon thin wire 100, but at the V groove 105 part, the thin wire is thin and pinch off, so that a potential barrier is formed. Since two V-grooves 105 are formed adjacent to each other, the inversion layer in the minute region between the V-grooves 105 has a quantum dot structure sandwiched by potential barriers.

V-groove 1 formed by anisotropic etching
05 The tip structure is sharp, and the potential barrier width formed in this region is small, so that electrons supplied from the source 106 can tunnel to the quantum dot structure. Also, the electrons injected into the quantum dots can be tunneled to the drain 107 side in the same manner. Furthermore, if the quantum dots are sufficiently small and this charging energy is sufficiently larger than the thermal energy at the measurement temperature, the Coulomb blockade phenomenon becomes observable.

In the device structure of the first embodiment, since the potential of the quantum dot can be modulated by the voltage of the gate 108, a single electron transistor capable of controlling the flow of a single electron from the source 106 to the drain 107. The structure is realized.

(Second Embodiment) FIG. 2 is a configuration diagram of a second embodiment of a single electronic device according to the present invention. FIG. 2 (a) is a top view and FIG. 2 (b) is the same. A sectional view taken along the line AA ′ of FIG. A silicon thin wire 200 having a width of several nm to several 100 nm and a length of several nm to several μm, which is obtained by processing an SOI substrate having a thickness of several nm to several hundreds nm in which an insulating film 202 is formed on a semiconductor substrate 201. The source 206 and the drain 207, which are n ⁺ diffusion layers, are present at the ends,
A gate 208 exists over the thin wire with an insulating film 204 having a thickness of several nm to several hundreds nm interposed.

The gate 208 also overlaps the source 206 and the drain 207. The width and depth of V are several nm to several hundreds nm on the upper surface and side surface of the central portion of the thin wire.
Two grooves 205 are formed at intervals of several nm to several 100 nm. In addition, the V-groove 205 has a structure in which the thin wire is not cut.

The above structure can be realized by the following manufacturing method. First, as shown in FIG. 2B, an insulating film 202 is formed on a semiconductor substrate 201, and a thickness of several nm to several 100 nm and a boron concentration of 10 ¹⁴ to 10 10 are formed on the insulating film 202.
S with an upper silicon layer of ¹⁸ cm ^-3 and plane orientation (100)
An OI substrate is prepared. Next, a negative resist for electron beam drawing is applied on the upper silicon layer of the SOI substrate,
By performing electron beam irradiation, a width of several nm to several 100 nm,
A resist pattern with a length and width of several nm to several hundred nm is formed (1
10) direction.

Next, using this negative resist pattern as a mask, the upper silicon layer (semiconductor substrate 2) is formed by RIE.
03) is performed and the silicon thin wire 200 is formed.
Next, the upper silicon layer is oxidized to have a thickness of several nm to several tens nm.
Is formed. A positive resist for electron beam drawing is applied on the silicon oxide film, and electron beam irradiation is performed to obtain a width of several nm to several 100 nm and a length of several nm to several 1
Two 00 nm patterns are drawn at intervals of several nm to several 100 nm. However, the length direction is made to coincide with the direction orthogonal to the silicon thin wire 200. Next, using this positive resist as a mask, the silicon oxide film on the upper surface and side surfaces of the upper silicon layer is removed by RIE, and then the positive resist is removed.

After that, the upper surface and the side surface of the upper silicon layer (semiconductor substrate 203) are etched using hydrazine as a mask with the silicon oxide film masked with the positive resist. Hydrazine is an anisotropic etchant, and the etching rates of the (100) plane and the (110) plane are significantly higher than that of the (111) plane.
1) A V-shaped groove structure 205 is formed in FIG. Since the apex angle of the V groove 205 is fixed at 70 degrees, the V groove 205 can be adjusted by adjusting the electron beam drawing width.
Thus, it is possible to prevent the thin line from being cut below the upper silicon layer (semiconductor substrate 203).

After that, the thin silicon wire 200 is set to several nm to several 1
Thermal oxidation is performed to 0 nm, and the entire thin silicon wire is covered with a silicon oxide film (insulating film 204). However, by adjusting the amount of oxidation, it is necessary to prevent the silicon thin wire from being cut at the V groove forming portion.

Next, a resist is applied, and patterning is performed by electron beam or photolithography so that the resist remains only in the central portion of the fine line. After that, phosphorus or arsenic is ion-implanted using the resist as a mask, and n is applied to the end of the thin wire.
^{A +} type region is formed to serve as the source 206 and the drain 207. Then, at a temperature of 900 ° C to 1100 ° C, 10
The implanted ions in the source 206 and drain 207 are activated by annealing in a nitrogen (N ₂ ) atmosphere for ˜60 minutes. After this 100 aluminum
Approximately 1000 nm is vapor-deposited, the resist is patterned by electron beam or photolithography, and then RI
Aluminum is processed by E to form the gate 208.

Next, the device operation in the second embodiment will be described. When a positive voltage is applied to the gate 208, an inversion layer is induced on the surface of the silicon thin wire 200, but pinching off occurs at the V-groove 205 portion because the thin wire is thin and a potential barrier is formed. V groove 205
Are formed adjacent to each other, the inversion layer in the minute region between the V grooves 205 has a quantum dot structure sandwiched by potential barriers.

V-groove 2 formed by anisotropic etching
05 The structure of the tip is sufficiently sharp and the potential barrier width formed in this region is sufficiently small.
The electrons supplied from 06 can have a quantum dot structure. Further, the electrons injected into the quantum dots can similarly be tunneled to the drain 207 side. Furthermore, if the quantum dots are sufficiently small and this charging energy is sufficiently larger than the thermal energy at the measurement temperature, the Coulomb blockade phenomenon becomes observable.

In the device structure of the second embodiment, the potential of the quantum dot can be modulated by the voltage of the gate 208, so that the flow of a single electron from the source 206 to the drain 207 can be controlled by a single electron transistor. The structure is realized. Furthermore, in this second embodiment,
The facing area between the quantum dot and the tunnel barrier is the first
Since it is smaller than the embodiment described above, the charging energy is large and the device can operate at a higher temperature.

(Third Embodiment) FIG. 3 is a sectional view of a third embodiment of a single electronic device according to the present invention. An insulating film 302 is formed on a semiconductor substrate 301 and has a thickness of n
A source 306 and a drain 307 each made of an n ⁺ diffusion layer are present at the end of a silicon thin wire having a width of several nm to several 100 nm and a length of several nm to several μm, which is obtained by processing an SOI substrate of m to several 100 nm. , Thickness of several nm to several 1 on thin wire
The gate 308 exists through the insulating film 304 of 00 nm.

The gate 308 overlaps with the source 306 and the drain 307. The width and depth of V are several nm to several hundreds nm on the upper surface and side surface of the central portion of the thin wire.
Two grooves 305 are formed at intervals of several nm to several hundred nm. The thin wire has a structure cut by the V groove 305.

The above structure can be realized by the following manufacturing method. First, the insulating film 302 is formed on the semiconductor substrate 301.
Is formed, and the thickness is further several nm to several 100 n.
m, boron concentration 10 ¹⁴ to 10 ¹⁸ cm ⁻³ , plane orientation (10
An SOI substrate having an upper silicon layer of 0) is prepared. Next, the upper silicon layer of this SOI substrate is oxidized to form a silicon oxide film having a thickness of several nm to several 100 nm.
Subsequently, a positive resist for electron beam drawing is applied on the silicon oxide film, and electron beam irradiation is performed to form a pattern having a width of several nm to several 100 nm and a length width of several nm to several 100 nm, from several nm to several 100 nm. Two lines are drawn at intervals. However, the direction of the fine line must be exactly aligned with the (110) direction.

Next, using the positive resist as a mask, the silicon oxide film on the upper silicon layer is removed by RIE, and then the positive resist is removed. Then, the upper silicon layer is etched with hydrazine using the silicon oxide film as a mask. Hydrazine is an anisotropic etchant, and has (100) plane and (11) plane.
Since the etching rate of the (0) plane is significantly higher than that of the (111) plane, a V-shaped groove structure having the (111) plane as a side surface is formed. Since the angle of the apex of the V groove is fixed at 70 degrees, the cutting width of the lower portion of the upper silicon layer can be adjusted by adjusting the electron beam drawing width.

Next, the upper silicon layer (semiconductor substrate 30
3) After removing the upper silicon oxide film with HF, a negative electron beam resist is applied on the upper silicon layer and electron beam irradiation is performed to obtain a width of several nm to several 100 nm and a length of several nm. A resist pattern of several μm is formed so as to be orthogonal to the V groove structure.

Next, using this resist pattern as a mask, the upper silicon layer (semiconductor substrate 303) is formed by RIE.
Is processed to form a silicon thin wire. After that, the silicon thin wire is thermally oxidized by several nm to several tens of nm to cover the entire silicon thin wire with a silicon oxide film (insulating film 304). However, the silicon thin wire must be cut at the V-groove forming portion by adjusting the amount of oxidation.

Next, a resist is applied, and patterning is performed by electron beam or photolithography so that the resist remains only in the central portion of the fine line. After that, phosphorus or arsenic is ion-implanted using the resist as a mask, and n is applied to the end of the thin wire.
^{A +} type region is formed to serve as a source 306 and a drain 307. Then, at a temperature of 900 ° C to 1100 ° C, 10
The implanted ions in the source 306 and drain 307 are activated by annealing in a nitrogen (N ₂ ) atmosphere for ˜60 minutes. After this aluminum (Al)
Is evaporated to about 100 to 1000 nm, a resist is patterned by electron beam or photolithography, and then aluminum is processed by RIE to form a gate 308.
To form

Next, the device operation in the third embodiment will be described. When a positive voltage is applied to the gate 308, an inversion layer is induced on the surface of the silicon thin wire, but the inversion layer is completely cut by the two V grooves 305. 2
The inversion layer region between the two V-grooves 305 is sandwiched between silicon oxide films to form a quantum dot structure.

When the cut length under the upper silicon layer is short and the potential barrier width formed by the silicon oxide film is sufficiently small, the electrons supplied from the source 306 can tunnel to the quantum dot structure. In addition, the electrons injected into the quantum dots can similarly be tunneled to the drain 307 side. Furthermore, if the quantum dots are sufficiently small and this charging energy is sufficiently larger than the thermal energy at the measurement temperature, the Coulomb blockade phenomenon becomes observable.

In the device structure of the third embodiment, since the potential of the quantum dot can be modulated by the voltage of the gate 308, a single electron that can control the flow of a single electron from the source 306 to the drain 307. A transistor structure is realized. Furthermore, in the third embodiment,
Since the thin wire is completely separated by the V-groove 305, the height of the tunnel barrier is high, carrier confinement in the quantum dot is complete, and operation at a higher temperature is expected as compared with the first embodiment. .

(Fourth Embodiment) FIG. 4 shows the present invention.
Figure 4 shows a sectional view of a fourth embodiment of a single electronic device. Semi-conductor
Insulating film 402 formed on body substrate 401, thickness number n
An electrically degenerated SOI substrate with a size of m to several 100 nm
Width of several nm to several hundred nm, number of length
At the end of the silicon thin wire of nm to several μm, n⁺ From the diffusion layer
There is a source 406 and a drain 407 on the thin line.
Through an insulating film 404 having a thickness of several nm to several hundred nm,
There is a gate 408.

The gate 408 overlaps the source 406 and the drain 407. A V groove 405 having a width and a depth of several nm to several hundreds nm is formed on the upper surface of the central portion of the thin wire.
Are formed with an interval of several nm to several 100 nm. Further, the thin wire has a structure cut by the V groove 405.

The above structure can be realized by the following manufacturing method. First, the insulating film 402 is formed on the semiconductor substrate 401.
Is formed, and the thickness is further several nm to several 100 n.
m, boron concentration 10 ¹⁹ to 10 ²⁰ cm ⁻³ , plane orientation (10
An SOI substrate having an upper silicon layer of 0) is prepared. Next, the upper silicon layer of this SOI substrate is oxidized to form a silicon oxide film having a thickness of several nm to several 100 nm.
Subsequently, a positive resist for electron beam drawing is applied on the silicon oxide film, and electron beam irradiation is performed to form a pattern having a width of several nm to several 100 nm and a length width of several nm to several 100 nm, from several nm to several 100 nm. Two lines are drawn at intervals. However, the direction of the fine line must be exactly aligned with the (110) direction.

Next, using the positive resist as a mask, the silicon oxide film on the upper silicon layer is removed by RIE, and then the positive resist is removed. Then, the upper silicon layer is etched with hydrazine using the silicon oxide film as a mask. Hydrazine is an anisotropic etchant, and has (100) plane and (11) plane.
Since the etching rate of the (0) plane is significantly higher than that of the (111) plane, 405 in FIG.
A V-shaped groove structure shown by is formed. Since the angle of the apex of the V groove 405 is fixed to 70 degrees, it is possible to adjust the cutting width of the lower portion of the upper silicon layer by adjusting the electron beam drawing width.

Next, the upper silicon layer (semiconductor substrate 40
3) After removing the upper silicon oxide film with HF, a negative electron beam resist is applied on the upper silicon layer and electron beam irradiation is performed to obtain a width of several nm to several 100 nm and a length of several nm. A resist pattern of several μm is formed so as to be orthogonal to the V groove structure.

Next, using this resist pattern as a mask, the upper silicon layer (semiconductor substrate 403) is formed by RIE.
Is processed to form a silicon thin wire. After that, the thin silicon wire is thermally oxidized by several nm to several tens of nm to cover the entire thin silicon wire with a silicon oxide film (insulating film 404). However, the silicon thin wire must be cut at the V-groove forming portion by adjusting the amount of oxidation.

Next, a resist is applied, and patterning is performed by electron beam or photolithography so that the resist remains only in the central portion of the fine line. After that, phosphorus or arsenic is ion-implanted using the resist as a mask, and n is applied to the end of the thin wire.
^{A +} type region is formed to serve as a source 406 and a drain 407. Then, at a temperature of 900 ° C to 1100 ° C, 10
By annealing in N ₂ atmosphere for ~ 60 minutes,
Activation of the implanted ions in the source 406 and the drain 407 is performed. After this, add 100 to 100 aluminum.
A gate electrode 408 is formed by vapor-depositing about 0 nm, patterning a resist by electron beam or photolithography, and then processing aluminum by RIE.

Next, the device operation in the fourth embodiment will be described. Since the silicon thin wire of this embodiment is formed of a degenerate semiconductor,
Even if the voltage is not applied to 08, the carrier density is sufficiently large and the film has conductivity. Therefore, this embodiment is different from the above-described first, second, and third embodiments in that it is not necessary to induce an inversion layer on the surface of the thin wire by the gate voltage, and thus it is possible to operate with both positive and negative gate voltages. Has the advantage of being.

Further, in this embodiment, the thin wire is completely cut by the two V grooves 405, so that the two V grooves 4 are formed.
The thin line region between 05 is sandwiched between silicon oxide films to form a quantum dot structure. Further, when the cut length under the upper silicon layer is small and the potential barrier width formed by the silicon oxide film is sufficiently small, the electrons supplied from the source 406 can be tunneled to the quantum dot structure.

Further, the electrons injected into the quantum dots can similarly be tunneled to the drain 407 side.
Furthermore, if the quantum dots are sufficiently small and this charging energy is sufficiently larger than the thermal energy at the measurement temperature, the Coulomb blockade phenomenon becomes observable.

Therefore, in the device structure of the fourth embodiment, since the potential of the quantum dot can be modulated by the voltage of the gate 408, a single electron flow from the source 406 to the drain 407 can be controlled. An electronic transistor structure is realized.

(Fifth Embodiment) FIG. 5 is a configuration diagram of a second embodiment of a single electronic device according to the present invention. FIG. 5 (a) is a top view and FIG. 5 (b) is the same. A sectional view taken along the line AA ′ of FIG. A silicon thin wire 500 having a width of several nm to several 100 nm and a length of several nm to several μm, which is obtained by processing an SOI substrate having a thickness of several nm to several hundred nm, in which an insulating film 502 is formed on a semiconductor substrate 501. The source 506 and the drain 507, which are n ⁺ diffusion layers, are present at the ends,
A gate 508 is provided over the thin wire with an insulating film 504 having a thickness of several nm to several hundreds nm interposed therebetween.

The gate 508 overlaps the source 506 and the drain 507. The width and depth of V are several nm to several hundreds nm on the upper surface and side surface of the central portion of the thin wire.
Three grooves 505 are formed at intervals of several nm to several hundred nm. In addition, the V-groove 205 has a structure in which the thin wire is not cut.

The above structure can be realized by the following manufacturing method. First, as shown in FIG. 5B, an insulating film 502 is formed on a semiconductor substrate 501, and a thickness of several nm to several hundred nm and a boron concentration of 10 ¹⁴ to 10 10 are formed on the insulating film 502.
S with an upper silicon layer of ¹⁸ cm ^-3 and plane orientation (100)
An OI substrate is prepared. Next, the upper silicon layer of this SOI substrate is oxidized to form a silicon oxide film having a thickness of several nm to several 100 nm.

Next, a positive type resist for electron beam drawing is applied on the silicon oxide film, and electron beam irradiation is performed to obtain a width of several nm to several 100 nm and a length of several nm to several 100 n.
Three m patterns are drawn at intervals of several nm to several 100 nm. However, the direction of the thin line must be exactly aligned with the (110) direction. Next, using this positive resist as a mask, the silicon oxide film on the upper silicon layer is removed by RIE, and then the positive resist is removed.

Thereafter, the upper silicon layer (semiconductor substrate 503) is etched using hydrazine with the silicon oxide film masked with the positive resist as a mask. Hydrazine is an anisotropic etchant, (1
The etching rates of the (00) plane and the (110) plane are (11
Since it is significantly larger than the 1) plane, the V-groove structure 505 shown in FIG. 5 having the (111) plane as the side surface is formed. Since the angle of the apex of the V groove 505 is fixed to 70 degrees, the apex of the V groove 505 can be prevented from reaching the lower portion of the upper silicon layer (semiconductor substrate 503) by adjusting the electron beam drawing width. It is possible.

Next, the upper silicon layer (semiconductor substrate 50
3) After removing the upper silicon oxide film with HF, a negative electron beam resist is applied on the upper silicon layer and electron beam irradiation is performed to obtain a width of several nm to several 100 nm and a length of several nm. A resist pattern of several μm is formed so as to be orthogonal to the V groove structure.

Next, using this resist pattern as a mask, the upper silicon layer (semiconductor substrate 503) is formed by RIE.
Is processed to form a silicon thin wire. After that, the thin silicon wire is thermally oxidized by several nm to several tens of nm to cover the entire thin silicon wire with a silicon oxide film (insulating film 504). However, by adjusting the amount of oxidation, it is necessary to prevent the silicon thin wire from being cut at the V groove forming portion.

Next, a resist is applied, and patterning is performed by electron beam or photolithography so that the resist remains only in the central portion of the fine line. After that, phosphorus or arsenic is ion-implanted using the resist as a mask, and n is applied to the end of the thin wire.
^{A +} type region is formed to serve as a source 506 and a drain 507. Then, at a temperature of 900 ° C to 1100 ° C, 10
By annealing in N ₂ atmosphere for ~ 60 minutes,
Activation of the implanted ions in the source 506 and the drain 507 is performed. After this, add 100 to 100 aluminum.
The gate 508 is formed by depositing about 0 nm and patterning the resist by electron beam or photolithography, and then processing the aluminum by RIE.

Next, the device operation in the fifth embodiment will be described. When a positive voltage is applied to the gate 508, an inversion layer is induced on the surface of the silicon thin wire, but at the V groove 505 part, the thin wire is thin and pinch off to form a potential barrier. Since three V-grooves 505 are formed adjacent to each other, the inversion layer in the two minute regions between the V-grooves 505 has a quantum dot structure sandwiched by potential barriers.

Since the structure of the V groove 505 tip portion formed by using the anisotropic etching of this embodiment is sufficiently sharp and the potential barrier width formed in this region is sufficiently small, it is supplied from the source 506. The generated electrons can tunnel to the quantum dot structure. Also, the electrons injected into the quantum dots can be tunneled to the drain 507 side in the same manner. Furthermore, if the quantum dots are sufficiently small and this charging energy is sufficiently larger than the thermal energy at the measurement temperature, the Coulomb blockade phenomenon becomes observable.

Therefore, in the device structure of the fifth embodiment, the potential of the quantum dot can be modulated by the voltage of the gate 508, so that a single electron flow from the source 506 to the drain 507 can be controlled. An electronic transistor structure is realized. Furthermore, in this embodiment, since two quantum dots are connected in series, co-tunneling is suppressed, and a clearer on / off of the current can be realized by the gate voltage.
Similarly, a structure in which a plurality of quantum dots are arranged in series can be realized.

[0064]

EXAMPLES Next, examples of each embodiment will be described. An SOI substrate having an upper silicon layer having a thickness of 50 nm and a boron concentration of 10 ¹⁵ cm ⁻³ was used for manufacturing the device of the first embodiment shown in FIG. Using electron beam lithography and hydrazine, two V-groove structures each having a width of 20 nm and a length of 1 μm were formed on the surface of the upper silicon layer at intervals of 20 nm. After that, the upper silicon layer is processed by electron beam lithography and RIE, and the cap is 20 nm and the length is 1 μm.
m thin line pattern was formed. After that, the insulating film 104 was formed by oxidizing the thin wire by 10 nm. The source 106 and the drain 107 were formed by implanting 1E16 cm ^-2 of As with energy of 20 keV and annealing for 30 minutes in a N ₂ atmosphere at 900 ° C. Gate 1
For 08, aluminum having a thickness of 100 nm is used, and RI
Patterning was performed at E.

In the single-electron device manufactured as described above, when a positive voltage is applied to the gate 108 with a voltage of 50 mV applied between the source 106 and the drain 107, periodic drain current oscillation occurs. Was observed. This vibration is due to single electron tunneling,
It was possible to observe clearly up to a temperature of about 10K.

Next, an example of the second embodiment shown in FIG. 2 will be described. In manufacturing the device of the second embodiment, an SOI substrate having an upper silicon layer having a thickness of 50 nm and a boron concentration of 10 ¹⁵ cm ⁻³ is used, the upper silicon layer is processed by electron beam lithography and RIE, and a width of 2 is obtained.
A fine line pattern having a length of 0 nm and a length of 1 μm was formed. Then, using electron beam lithography and hydrazine, a width of 20
Two V-groove structures each having a thickness of 1 nm and a length of 1 μm were formed on the upper surface and the side surface of the thin wire at intervals of 20 nm. After this, thin line 10n
The insulating film 204 was formed by m-oxidation. As the source 206 and the drain 207, 1E16 cm ⁻² of As was implanted with an energy of 20 keV and N _{2 at} 900 ° C.
It was formed by annealing for 30 minutes in the atmosphere. Aluminum having a thickness of 100 nm is used for the gate 208,
Patterning was performed by RIE.

In the single-electron device manufactured as described above, when a positive voltage is applied to the gate 208 while a voltage of 50 mV is applied between the source 206 and the drain 207, a periodic drain current Vibration was observed.
This vibration was caused by single electron tunneling, and could be clearly observed up to a temperature of about 25 K, which is higher than the operating temperature of the first embodiment.

Next, an example of the third embodiment shown in FIG. 3 will be described. An SOI substrate having an upper silicon layer with a thickness of 10 nm and a boron concentration of 10 ¹⁵ cm ⁻³ was used for manufacturing the device of the third embodiment. Width 20nm, length 1μ using electron beam lithography and hydrazine
Two V-groove structures of m were formed on the surface of the upper silicon layer at intervals of 20 nm. The V groove 305 reaches the bottom of the upper silicon layer, and a 6 nm gap is formed in the lower portion of the upper silicon layer.

Thereafter, the upper silicon layer is processed by electron beam lithography and RIE, and the width is 20 nm and the length is 1 μm.
m thin line pattern was formed. After that, the thin film was oxidized by 10 nm to form the insulating film 304. Further, the source 306 and the drain 307 were formed by implanting 1E16 cm ⁻² of As with energy of 20 keV and annealing for 30 minutes in a N ₂ atmosphere at 900 ° C. Gate 3
For 08, aluminum having a thickness of 100 nm is used, and RI
Patterning was performed at E.

In the single electron device of the third embodiment manufactured as described above, the source 306 and the drain 3
With a voltage of 50 mV applied between 07 and 30,
When a positive voltage was applied to No. 8, periodic drain current oscillation was observed. This vibration is due to single-electron tunneling, and could be clearly observed up to a temperature of about 50 K, which is higher than the operating temperature of the first embodiment.

Next, an example of the fourth embodiment shown in FIG. 4 will be described. An SOI substrate having an upper silicon layer having a thickness of 10 nm and a boron concentration of 10 ¹⁹ cm ⁻³ was used for manufacturing the device of the fourth embodiment. Width 20nm, length 1μ using electron beam lithography and hydrazine
Two V grooves 405 of m were formed on the surface of the upper silicon layer at intervals of 20 nm. The V groove 405 reaches the bottom of the upper silicon layer, and a 6 nm gap is formed in the lower portion of the upper silicon layer.

After that, the upper silicon layer is processed by electron beam lithography and RIE, and the width is 20 nm and the length is 1 μm.
m thin line pattern was formed. After that, the insulating film 404 was formed by oxidizing the thin wire by 10 nm. Further, the source 406 and the drain 407 were formed by implanting 1E16 cm ⁻² of As with energy of 20 keV and annealing for 30 minutes in a N ₂ atmosphere at 900 ° C. Gate 4
For 08, aluminum having a thickness of 100 nm is used, and RI
Patterning was performed at E.

In the single-electron device of the fourth embodiment manufactured as described above, the source 406 and the drain 4
With a voltage of 50 mV applied between 07, gate 40
When a positive or negative voltage was applied to No. 8, periodic oscillation of drain current was observed. This vibration is due to single-electron tunneling, and could be clearly observed up to a temperature of about 50 K, which is higher than the operating temperature of the first embodiment.

Next, an example of the fifth embodiment shown in FIG. 5 will be described. An SOI substrate having an upper silicon layer with a thickness of 50 nm and a boron concentration of 10 ¹⁵ cm ⁻³ was used for manufacturing the device of the fifth embodiment. Width 20nm, length 1μ using electron beam lithography and hydrazine
Five V-groove structures of m were formed on the surface of the upper silicon layer at intervals of 20 nm. After this, electron beam lithography and RI
The upper silicon layer was processed by E to form a fine line pattern having a width of 20 nm and a length of 1 μm. After this, thin line 10n
The insulating film 504 was formed by m-oxidation.

The source 506 and the drain 507 are
It was formed by implanting 1E16 cm ⁻² of As with energy of 20 keV and annealing for 30 minutes in a N ₂ atmosphere at 900 ° C. Aluminum having a thickness of 100 nm was used for the gate 508, and patterning was performed by RIE.

In the single electron device of the fifth embodiment manufactured as described above, the source 506 and the drain 5
With a voltage of 250 mV applied between 07, gate 5
When a positive voltage was applied to 08, periodic drain current oscillation was observed. In the structure of this embodiment, the quantum dots are connected in series, and co-tunneling is performed.
ing) is suppressed, the oscillation of the drain current becomes clearer, and the operating temperature is higher than that of the first embodiment.
I was able to confirm the operation up to 5K.

The present invention is not limited to the above-described embodiments and examples, and the single electronic device of the present invention can be realized by using the method shown below. For example, S
Instead of the OI substrate, an SOS substrate or a substrate obtained by annealing the polysilicon on the oxide film to single crystal may be used. Further, in each of the embodiments, the dopant in the upper silicon layer is a p-type impurity, but n
It may be a type impurity. However, in this case, the conductivity type of the source, drain and inversion layer is p-type.

In addition to hydrazine, KOH, tetramethylammonium hydroxide, ethylenediamine, ammonia, etc. can be used as the anisotropic etchant for forming the V-groove structure. Further, in each of the embodiments, the oxide film on the upper part of the thin wire is formed by using thermal oxidation, but it can also be formed by a chemical vapor deposition (CVD) method. Further, as the insulating film, a nitride film may be used instead of the oxide film. As the material of the gate, other than aluminum, other metal materials such as doped polysilicon and tungsten may be used. Although silicon has been described above as the thin wire material, the present structure can be realized by using a material other than silicon, such as a compound semiconductor.

[0079]

As described above, in the single-electron device of the present invention, since a tunnel barrier having a narrow width and a large energy barrier can be formed at the apex of the V groove, carriers can be confined in the quantum dots even at high temperature. Has the advantage of being possible. In addition, since the facing area between the quantum dot and the thin line portion sandwiching the tunnel barrier is small, the capacitance of the quantum dot can be reduced, and the device can operate at high temperature.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of a single electronic device of the present invention, (a) is a top structural diagram, (b) is A- of (a).
FIG. 9 is a cross-sectional structural view taken along the line A ′.

2A and 2B are configuration diagrams of a second embodiment of a single electronic device of the present invention, FIG. 2A is a top view and FIG. 2B is a sectional view taken along line AA ′.

FIG. 3 is a sectional structural view of a third embodiment of a single electronic device of the present invention.

FIG. 4 is a sectional structural view of a fourth embodiment of a single electronic device of the present invention.

5A and 5B are configuration diagrams of a single electronic device according to a fifth embodiment of the present invention, in which FIG. 5A is a top view and FIG. 5B is A- of FIG.
It is a cross-section figure in A '.

FIG. 6 is a block diagram of an example of a conventional single-electron element, (a)
Is a top structural view, and (b) is a cross-sectional structural view taken along the line AA ′ of (a).

[Explanation of symbols]

100, 200, 500 Thin silicon wires 101, 201, 301, 401, 501 Semiconductor substrate 102, 104, 202, 204, 302, 304, 4
02, 404, 502, 504 Insulating film 103, 203, 303, 403, 503 Semiconductor substrate 105, 205, 305, 405, 505 V-groove 106, 206, 306, 406, 506 Source 107, 207, 307, 407, 507 Drain 108, 208, 308, 408, 508 gate

Claims (4)

[Claims] 1. A semiconductor layer is present on the first insulator layer,
A second insulator layer is present overlying the semiconductor layer,
A single-electron device in which a gate is formed on the second insulator layer and a drain and a source are formed on the semiconductor layer, wherein the semiconductor layer has a thin linear shape having a plurality of V-grooves at a central portion. A single electron element characterized in that at least one of the width and the thickness of the thin wire in the V groove portion is smaller than that in the peripheral portion. 2. The single electronic device according to claim 1, wherein the V groove is formed so as not to cut the thin wire. 3. The single electronic device according to claim 1, wherein the V groove is formed so as to cut the thin wire. 4. The single-electron device according to claim 1, wherein the thin wire has a high impurity concentration and is degenerated, and the thin wire is cut by the V groove.