JPH09199718A - Semiconductor integrated circuit device and its fabrication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fine-making technique of a power MOSFET of a lateral double diffusion structure. SOLUTION: A channel potential clamping semiconductor layer (p-type semiconductor layer 2p, n-type semiconductor layer 2n) is formed around a power MOS part, and power is supplied from the semiconductor layer through a substrate to a channel layer (n-type channel layer 3n, p-type channel layer 3p) of a power MOSFET (p channel type MOSFET ( Qpd), n channel type MOSFET (Qnd). Hereby, there is no need of a channel potential clamping semiconductor layer formed next to a source region (10, 16) inside the channel layer, and the occupation area of the channel layer (p-type channel layer 2p, n-type channel layer 2n) is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a lateral double diffused metal oxide (MOSFET) having a lateral double diffusion structure.
The present invention relates to a technique effective when applied to a semiconductor integrated circuit device having a semiconductor field effective transistor.

[0002]

2. Description of the Related Art A MOSFET as a power element has a large breakdown resistance, thermal stability and gain, and has a simple power amplification structure. Therefore, a power device for a switching power supply, a power device for controlling an electric motor, a power device for a vehicle, etc. It is widely used in devices and the like, and in recent years, miniaturization has been advanced in order to realize even higher performance.

As a MOSFET for a power device of this type, there is a "SM Sze, Physics of Semiconductor Device".
S. Wiley, New York, 1981 ”, and a lateral double diffusion structure MOSFET (DMOS) is known.

The above-mentioned lateral double diffusion structure MOSFET is
For example, in the n-channel type, an n-type source region is formed inside the p-type channel layer formed on the main surface of the semiconductor substrate,
Further, a p ⁺ type semiconductor layer is formed adjacent to the source region. The semiconductor layer of the p ⁺ -type is connected to the common electrode and the source region, a fixed potential of the source region potential is supplied to the channel layer through the semiconductor layer of the electrode and the p ⁺ -type There is.

The operation of this MOSFET is the same as that of a normal MOSFET having no lateral double-diffused structure. When a voltage higher than the threshold voltage for the channel layer is applied to the gate electrode, the electrons that are carriers become sources. The region flows into the drain region through the channel layer.

[0006]

As described above, in the conventional lateral double-diffused MOSFET, the source region and the semiconductor layer for fixing the channel potential are formed adjacent to each other inside the channel layer. Therefore, it is necessary to secure a mask alignment margin for both, and the occupied area of the channel layer becomes larger accordingly.

For the above-mentioned reason, the miniaturization of the device size is restricted in the conventional lateral double-diffused MOSFET.
It is difficult to realize high performance such as reduction of on-resistance. Further, if a large number of MOSFETs are connected in parallel for the purpose of increasing current capacity or reducing series resistance, the chip size becomes large.

An object of the present invention is to provide a horizontal double diffusion structure MO
It is to provide a technique capable of miniaturizing an SFET.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In the semiconductor integrated circuit device of the present invention, the second conductive type source region is formed inside the first conductive type channel layer formed on the main surface of the semiconductor substrate, and is formed on the main surface of the semiconductor substrate. MOSF of lateral double diffusion structure for supplying a fixed potential from the first semiconductor region of the first conductivity type to the channel layer
In a semiconductor integrated circuit device such as a power device including a plurality of ETs, the first conductivity type first semiconductor region is formed in a region separated from the plurality of MOSFETs, and each channel of the plurality of MOSFETs is formed. A second semiconductor region of the first conductivity type is formed in the lower part of the layer and the lower part of the first semiconductor region, and the respective channels of the plurality of MOSFETs are formed from the first semiconductor region through the second semiconductor region. A fixed potential is supplied to the layer.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a source region having a conductivity type different from that of the channel layer is formed inside the channel layer formed on the main surface of the semiconductor substrate, and the source region is formed on the main surface of the semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device comprising a plurality of lateral double-diffused MOSFETs for supplying a potential to the channel layer from a first semiconductor region having the same conductivity type as the channel layer, comprising: Forming a first conductivity type buried layer on a main surface of a two conductivity type semiconductor substrate, and then growing a first conductivity type epitaxial layer on the semiconductor substrate, (b) a main surface of a first region of the epitaxial layer A step of forming a first semiconductor region of a first conductivity type whose bottom is in contact with the buried layer, (c)
After forming a plurality of MOSFET gate electrodes on the main surface of the second region of the epitaxial layer, which is separated from the first region, impurities of the first conductivity type are ion-implanted on the main surface of the second region of the epitaxial layer. Type in the above M's
Forming a first conductivity type channel layer of the OSFET,
(D) Impurities of the second conductivity type are ion-implanted into the main surface of the second region of the epitaxial layer to form the plurality of M's.
Forming a source region and a drain region of the OSFET; (e) patterning the conductive film deposited on the epitaxial layer to form electrodes connected to the source region and the drain region of the plurality of MOSFETs; And a step of forming an electrode connected to the first semiconductor region.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a source region having a conductivity type different from that of the channel layer is formed inside the channel layer formed on the main surface of the semiconductor substrate, and the source region is formed on the main surface of the semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device comprising a plurality of lateral double-diffused MOSFETs for supplying a potential to the channel layer from a first semiconductor region having the same conductivity type as that of the channel layer, comprising: (a) a second conductivity type Forming a second-conductivity-type buried layer on the main surface of the semiconductor substrate, and growing a first-conductivity-type epitaxial layer on the semiconductor substrate, (b) forming a second-conductivity-type buried layer on the main surface of the first region of the epitaxial layer. Forming a second conductivity type first semiconductor region whose bottom portion is in contact with the buried layer; (c) a plurality of MOSFEs on the main surface of the second region of the epitaxial layer, which is separated from the first region. After forming the gate electrode of the second conductivity type impurity is ion-implanted into the main surface of the second region of said epitaxial layer, said plurality of MOSFET
Forming a channel layer of the second conductivity type, (d) source region and drain region of the plurality of MOSFETs by ion-implanting impurities of the first conductivity type into the main surface of the second region of the epitaxial layer. Forming step (e)
Patterning the conductive film deposited on the epitaxial layer to form the source regions of the plurality of MOSFETs;
And a step of forming an electrode connected to each of the drain regions and an electrode connected to the first semiconductor region.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a block diagram showing the overall structure of the power device of this embodiment, FIG. 2 is an overall circuit diagram of this power device, and FIG. 3 is a cross-sectional view of the main part of a semiconductor substrate on which this power device is formed. It is a figure.

As shown in FIG. 1, the power device according to the present embodiment is a power MOS formed on a semiconductor substrate 1.
Section, bias circuit section and logic section. The power MOS section is an n-channel type MOS shown in FIG.
FET (Qnd) and p-channel MOSFET (Qp
d) are provided in plurality, and form the output stage of the circuit shown in FIG. Multiple n-channel type MOSFE
T (Qnd) and multiple p-channel MOSFETs
Each of (Qpd) is regularly arranged in a predetermined direction and connected in parallel with each other. On the other hand, the bias circuit section and the logic section are the n-channel MOS shown in FIG.
A plurality of FETs (Qn), p-channel MOSFETs (Qp), and npn-type bipolar transistors (Qb) are provided, and these elements constitute a circuit.

As shown in FIG. 1, a semiconductor layer 2 is arranged around the power MOS portion so as to surround the power MOS portion. The semiconductor layer 2 is an n-channel MOS shown in FIG.
A p-type semiconductor layer 2p for supplying a fixed potential (for example, power supply potential) to the p-type channel layer 3p of the FET (Qnd), and p
Channel type MOSFET (Qpd) n-type channel layer 3n
And an n-type semiconductor layer 2n for supplying a fixed potential (for example, GND) to.

As shown in FIG. 3, an n-type epitaxial layer 5 is formed on a semiconductor substrate 1 made of p-type single crystal silicon. This n-type epitaxial layer 5 is
In order to increase the breakdown voltage of the power MOS (for example, 15 V or more), it is formed with a relatively thick film thickness.

N-channel type MOSFE of the power MOS section
T (Qnd) and p-channel MOSFET (Qpd)
A channel potential fixing p-type semiconductor layer 2p and an n-type semiconductor layer 2n, and a bias circuit portion and a logic portion n.
Channel type MOSFET (Qn), p channel type MOSF
ET (Qp) and npn type bipolar transistor (Q
Each of b) is formed in the active region surrounded by the field oxide film 6 on the main surface of the n-type epitaxial layer 5.

N-channel type MOSFE of the power MOS section
T (Qnd) is composed of the gate electrode 7, the gate oxide film 8, the drain region (n-type semiconductor region) 9, the source region (n-type semiconductor region) 10 and the p-type channel layer 3p, and is inside the p-type channel layer 3p. It has a lateral double diffusion structure in which the source region 10 is formed. The drain electrode 11 is connected to the drain region 9, and the source electrode 1 is connected to the source region 10.
2 are connected. Below the p-type channel layer 3p is a p ⁺ -type buried layer 13p, a part of which is electrically connected to the p-type channel layer 3p and the other part of which is electrically connected to the p-type semiconductor substrate 1. Has been formed.

An electrode 14 is connected to the p-type semiconductor layer 2p for fixing the channel potential, which is arranged around the power MOS section. A predetermined potential is supplied to the p-type semiconductor layer 2p through this electrode 14. Below the p-type semiconductor layer 2p is a p ⁺ -type buried layer 13p, a part of which is electrically connected to the p-type semiconductor layer 2p and the other part of which is electrically connected to the p-type semiconductor substrate 1. Has been formed.

With the above configuration, an n-channel type MOSF
The p-type channel layer 3p of ET (Qnd) and the p-type semiconductor layer 2p for fixing the channel potential are electrically connected via the p ⁺ -type buried layer 13p and the p-type semiconductor substrate 1.

P-channel type MOSFE of the power MOS section
T (Qpd) is a gate electrode 7, a gate oxide film 8, a drain region (p-type semiconductor region) 15, a source region (p-type semiconductor region) 16, a drift layer (p ⁻ type semiconductor layer) 17 and an n-type channel layer. 3n, and has a lateral double diffusion structure in which the source region 16 is formed inside the n-type channel layer 3n. A drain electrode 18 is connected to the drain region 15, and a source electrode 19 is connected to the source region 16. The bottom of the n-type channel layer 3n is formed at a position deeper than the bottom of the drift layer 17, and is electrically connected to the n-type epitaxial layer 5. Also, a p-channel type MO
An n ⁺ type buried layer 13n is formed at the bottom of the n type epitaxial layer 5 in the region where the SFET (Qpd) is formed.

An electrode 20 is connected to the n-type semiconductor layer 2n for fixing the channel potential, which is arranged around the power MOS section. A predetermined potential is supplied to the n-type semiconductor layer 2n through the electrode 20. The bottom of the n-type semiconductor layer 2n is
It reaches the n ⁺ type buried layer 13n formed at the bottom of the n type epitaxial layer 5.

With the above configuration, a p-channel type MOSF
The n-type channel layer 3n of ET (Qpd) and the n-type semiconductor layer 2n for fixing the channel potential are electrically connected via the n ⁺ -type buried layer 13n and the n-type epitaxial layer 5.

The n-channel MOSFET (Qn) in the bias circuit section and the logic section is composed of the n-type epitaxial layer 5
Is formed on the main surface of the p-type well 4p formed in a part of
The gate electrode 21, the gate oxide film 8 and a pair of n-type semiconductor regions (source region, drain region) 22, 22 are formed. An electrode 2 is provided on each of the n-type semiconductor regions 22.
3 are connected.

The p-channel MOSFET (Qp) in the bias circuit portion and the logic portion is composed of the n-type epitaxial layer 5
Is formed on the main surface of the n-type well 4n formed on the other part of the gate electrode 21, the gate oxide film 8 and the pair of p-type semiconductor regions (source region, drain region) 24, 24. . An electrode 25 is connected to each of the p-type semiconductor regions (source region, drain region) 24.

Bias circuit section and logic section npn
The type bipolar transistor (Qb) is a collector region composed of an n type epitaxial layer 5 and an n ⁺ type buried layer 13n formed at the bottom of the n type epitaxial layer 5, n
Base region (p-type semiconductor region) 27 formed in another part of the type epitaxial layer 5 and emitter region (n-type semiconductor region) 28 formed inside the base region 27.
It is composed of Further, a collector extraction region (n-type semiconductor region) 26 is formed on the other part of the n-type epitaxial layer 5.
Are formed. A collector electrode 29 is connected to the collector extraction region 26, a base electrode 30 is connected to the base region 27, and an emitter electrode 3 is connected to the emitter region 28.
1 is connected. The npn-type bipolar transistor (Qb) and the n-channel type MOSFET (Qn) and p-channel type MOSFET (Qp) are a field oxide film 6 and a p-type semiconductor region formed in the n-type epitaxial layer 5 therebelow. 32 and the p ⁺ -type buried layer 13p are electrically isolated from each other.

As described above, the power device according to the present embodiment has the p-channel MOSFET (Q
pd) n-type channel layer 3n is electrically connected to the n-type epitaxial layer 5 and the n-type epitaxial layer 5
And a lower part of the n-type semiconductor layer 2n for fixing the channel potential arranged around the power MOS part, respectively, to form the n ⁺ -type buried layer 13n so that the n-type channel layer 3n and the n-type semiconductor layer 2n are formed. By electrically connecting via the n ⁺ type buried layer 13n and the n type epitaxial layer 5,
A predetermined potential is supplied to the n-type channel layer 3n.

Thus, when the n-type semiconductor layer for fixing the channel potential is arranged adjacent to the source region 16 inside the n-type channel layer 3n of the p-channel MOSFET (Qpd), the source region 16 is required. Since a mask alignment margin between the n-type semiconductor layer and the n-type semiconductor layer becomes unnecessary, the area occupied by the n-type channel layer 3n can be reduced accordingly, and the p-channel MOSFET (Qpd) can be miniaturized.

FIG. 4A shows the p-channel type MOSF.
Drain region 15 of ET (Qpd) and n-type channel layer 3n
FIG. 3B is a plan view showing a pattern of the source region 16 formed on the inner side of FIG. Reference numeral 33 in the figure
Indicates a contact hole connecting the source region 16 and the source electrode 19, and reference numeral 34 indicates a contact hole connecting the drain region 15 and the drain electrode 18.

On the other hand, FIG. 5 is a plan view (a) and a sectional view (b) in which an n-type semiconductor layer 2n 'for fixing a channel potential is arranged adjacent to the source region 16 inside the n-type channel layer 3n. ). As shown in the figure, in this case, in addition to the contact hole 33 that connects the source region 16 and the source electrode 19, a contact hole 35 for forming the n-type semiconductor layer 2n ′ by ion implantation is required. Therefore, it is necessary to secure an alignment margin for the two contact holes 33 and 35, and the amount corresponding to this alignment margin is
The area of the n-type channel layer 3n becomes large.

Further, the power device of this embodiment is
The p ⁺ -type buried layer 13p is formed under the p-type channel layer 3p of the n-channel MOSFET (Qnd) in the power MOS section and under the p-type semiconductor layer 2p for fixing the channel potential, which is arranged around the power MOS section. To form the p-type channel layer 3p and the p-type semiconductor layer 2p into the p ⁺ -type buried layer 13
By electrically connecting via the p-type and p-type semiconductor substrate 1, a predetermined potential is supplied to p-type channel layer 3p.

Thus, when the p-type semiconductor layer for fixing the channel potential is arranged adjacent to the source region 10 inside the p-type channel layer 3p of the n-channel MOSFET (Qnd), the source region 10 is required. Since a mask alignment margin between the p-type semiconductor layer and the p-type semiconductor layer becomes unnecessary, the area occupied by the p-type channel layer 3p can be reduced accordingly, and the n-channel MOSFET (Qnd) can be miniaturized.

Next, a method of manufacturing the power device of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 6, a p-type semiconductor substrate 1 is prepared, and a p-type impurity (boron) is formed on a part of its main surface.
Then, an n-type impurity (phosphorus) is ion-implanted into the other part to form the p ⁺ -type buried layer 13p and the n ⁺ -type buried layer 13n.

Next, as shown in FIG. 7, after growing the n-type epitaxial layer 5 on the semiconductor substrate 1, a p-type impurity (boron) is ion-implanted into a part of the n-type epitaxial layer 5, The p-type semiconductor layer 2p for fixing the channel potential and the p-type semiconductor region 32 for element isolation are simultaneously formed. Further, an n-type impurity (phosphorus) is ion-implanted into another part of the n-type epitaxial layer 5 to simultaneously form the n-type semiconductor layer 2n for fixing the channel potential and the collector extraction region 26 of the npn-type bipolar transistor (Qb). Form.

Next, as shown in FIG. 8, p-type impurities (boron) are ion-implanted in a part of the n-type epitaxial layer 5 and n-type impurities (phosphorus) are ion-implanted in the other part, respectively, and p
The type well 4p and the n-type well 4n are formed. Then, after the field oxide film 6 for element isolation is formed on the surface of the n-type epitaxial layer 5 by using the LOCOS method, the gate oxide film 8 is formed on the surface of the active region surrounded by the field oxide film 6.

Next, as shown in FIG. 9, a p-type impurity (boron) is added to a part of the n-type epitaxial layer 5 in the region where the p-channel MOSFET (Qpd) of the power MOS portion is formed.
Drift layer (p ⁻ type semiconductor region)
After forming 17, the laminated film (polycide film) of the polycrystalline silicon film and the tungsten silicide film deposited by the CVD method is patterned to form the gate electrode 7 and the p-channel type of the n-channel MOSFET (Qnd) of the power MOS part. The gate electrode 7 of the MOSFET (Qpd) is formed.

Next, as shown in FIG.
Part of the n-type epitaxial layer 5 is ion-implanted with p-type impurity (boron) and the other part is ion-implanted with n-type impurity (phosphorus), respectively, to form the p-type channel layer 3p of the n-channel MOSFET (Qnd). And p-channel MOSFET
The (Qpd) n-type channel layer 3n is formed. The n-type impurities are ion-implanted with energy such that the bottom of the n-type channel layer 3n is deeper than the drift layer 17.
In order to simplify the process, the p-type impurity is added to the n-type epitaxial layer 5 in the bias circuit section and the logic section.
Of the npn bipolar transistor (Qb) is formed at the same time by ion-implanting a part of the.

Next, as shown in FIG. 11, n is formed in a part of the base region 27 of the npn bipolar transistor (Qb).
Type impurity (phosphorus) is ion-implanted to form the emitter region 2
After forming 8, a laminated film (polycide film) of a polycrystalline silicon film and a tungsten silicide film deposited by the CVD method
Are patterned to form the gate electrode 21 of the n-channel MOSFET (Qn) and the gate electrode 21 of the p-channel MOSFET (Qp) in the bias circuit portion and the logic portion.
To form

Next, as shown in FIG. 12, power MOS
P-type impurity (boron) is ion-implanted in a part of the n-type epitaxial layer 5 of the above portion, and (phosphorus) is ion-implanted in the other part thereof, respectively, to form a drain region 15, a source region 16 and a p-channel MOSFET (Qpd). n-channel type MOSFE
A drain region 9 and a source region 10 of T (Qnd) are formed. Further, in order to simplify the process, the p-type impurities are ion-implanted also in a part of the n-type epitaxial layer 5 in the bias circuit portion and the logic portion, so that the p-channel MO layer is formed.
The p-type semiconductor region (source region, drain region) 24 of the SFET (Qp) is simultaneously formed. Further, the n-type impurities are also ion-implanted into another part of the n-type epitaxial layer 5 to simultaneously form the n-type semiconductor region (source region, drain region) 22 of the n-channel MOSFET (Qn).

In this case, since the p-type impurity ion implantation is performed using the gate electrode 7 of the p-channel MOSFET (Qpd) as a mask, the lateral diffusion length from the gate end of the source region 16 and the n-type channel layer. The effective channel length determined by the distance from one end of 3n is the gate electrode 7
Is defined in a self-aligning manner. Similarly, the n-type impurity ion implantation is performed in the n-channel MOSFET.
Since the gate electrode 7 of (Qnd) is used as a mask,
The effective channel length of the n-channel MOSFET (Qnd) is also defined in self-alignment with the gate electrode 7.

Thus, the p-channel MOSFET
(Qpd) effective channel length and n-channel MOSF
Since the effective channel length of ET (Qnd) can be reduced, the p-channel MOSFET (Qpd) and the n-channel MOSFET (Qnd) can be miniaturized.

After that, a silicon oxide film is deposited on the semiconductor substrate 1 by the CVD method, a contact hole is formed in the silicon oxide film, and then an Al film is deposited on the silicon oxide film by, for example, the sputtering method and patterned. Then, the electrodes (electrodes 14, 20, 23, 25, drain electrodes 11, 18, source electrodes 12, 19, collector electrode 2)
By forming 9, the base electrode 30 and the emitter electrode 31), the power device of the present embodiment shown in FIG. 3 is substantially completed.

Although the invention made by the present inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say,

For example, in the embodiment shown in FIG. 13, an n-type semiconductor region 40n and an n ⁺ -type buried layer 13n are formed under the drain region 9 of an n-channel MOSFET (Qnd) to form a p-channel MOSFET (Qpd). Of the p-type semiconductor region 40p and the p ⁺ -type buried layer 13p below the drain region 15 of the n-type epitaxial layer 5
Has a relatively low breakdown voltage (for example, 7 V or less)
It can be applied to a power MOSFET. In this case, the n-type semiconductor region 40n and the p-type semiconductor region 40p
Is simultaneously formed with the n-type well and the p-type well of the bias circuit section and the logic section, whereby the process can be simplified.

The embodiment shown in FIGS. 14 and 15 is
In each case, the drift layer 17 of the p-channel MOSFET (Qpd) is formed at a position deeper than the n-type channel layer 3n. In these examples, the drift layer 17 is formed separately from the n-type channel layer 3n (FIG. 14), or the n-type buried layer 41 is formed between the n-type channel layer 3n and the n ⁺ -type buried layer 13n. (FIG. 15), the n-type channel layer 3n and the n ⁺ -type buried layer 13n are connected to each other.

In the above-mentioned embodiment, the case where the present invention is applied to the n-channel type and p-channel type power MOSFETs has been described. However, the present invention is applied to only the p-channel type power MOSFET or the n-channel type power MOSFET. It can also be applied to a power MOSFET.

[0050]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the semiconductor layer for fixing the channel potential is formed around the power MOS portion, and power is supplied from this semiconductor layer to the channel layer of the power MOSFET through the substrate. Can be made smaller. As a result, the power MOSFET can be miniaturized, so that the performance of the power device including the power element can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a power device according to an embodiment of the present invention.

FIG. 2 is an overall circuit diagram of a power device that is an embodiment of the present invention.

FIG. 3 is a main-portion cross-sectional view of a semiconductor substrate showing a power device according to an embodiment of the present invention.

FIG. 4A is a plan view showing a pattern of a drain region of a MOSFET and a source region formed inside a channel layer of a power device that is an embodiment of the present invention; FIG. It is also a sectional view.

5A is a plan view in the case where a semiconductor layer for fixing a channel potential is arranged adjacent to a source region inside a channel layer, and FIG. 5B is a sectional view of the same.

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the power device according to the embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the power device according to the embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the power device according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view of essential parts of a semiconductor substrate showing a method for manufacturing a power device that is an embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a power device that is an embodiment of the present invention.

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the power device according to the embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the power device according to the embodiment of the present invention.

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a power device according to another embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a power device according to another embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a power device according to another embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate 2 semiconductor layer (back gate layer) 2p p-type semiconductor layer 2n n-type semiconductor layer 2n ′ n-type semiconductor layer 3p p-type channel layer 3n n-type channel layer 4p p-type well 4n n-type well 5 n-type epitaxial layer 6 field oxide film 7 gate electrode 8 gate oxide film 9 drain region (n-type semiconductor region) 10 source region (n-type semiconductor region) 11 drain electrode 12 source electrode 13p p ⁺ type buried layer 13n n ⁺ type buried layer 14 electrode 15 Drain region (p-type semiconductor region) 16 Source region (p-type semiconductor region) 17 Drift layer (p ⁻ type semiconductor layer) 18 Drain electrode 19 Source electrode 20 Electrode 21 Gate electrode 22 n-type semiconductor region (source region, drain region) 23 electrode 24 p-type semiconductor region (source region, drain region) 25 electrode 26 Extender region (n-type semiconductor region) 27 Base region (p-type semiconductor region) 28 Emitter region (n-type semiconductor region) 29 Collector electrode 30 Base electrode 31 Emitter electrode 32 p-type semiconductor region 33 Contact hole 34 Contact hole 35 Contact hole 40p p-type semiconductor region 40n n-type semiconductor region 41 n-type buried layer Qb npn-type bipolar transistor Qn n-channel MOSFET Qnd n-channel MOSFET Qp p-channel MOSFET Qpd p-channel MOSFET

Claims (9)

[Claims] 1. A first conductivity type first region formed on the main surface of the semiconductor substrate by forming a second conductivity type source region inside the first conductivity type channel layer formed on the main surface of the semiconductor substrate.
A semiconductor integrated circuit device comprising a plurality of lateral double-diffused MOSFETs for supplying a potential from a semiconductor region to the channel layer, wherein the first conductivity type first semiconductor region is separated from the plurality of MOSFETs. A second conductive region of the first conductivity type is formed under the channel layer and the lower part of the first semiconductor region of each of the plurality of MOSFETs, and the second semiconductor region is interposed therebetween. A semiconductor integrated circuit device characterized in that a potential is supplied from the first semiconductor region to each channel layer of the plurality of MOSFETs. 2. The semiconductor integrated circuit device according to claim 1, wherein the first semiconductor region of the first conductivity type is arranged along an outer periphery of a circuit block composed of the plurality of MOSFETs. Semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 2, wherein the plurality of MOSFETs are connected in parallel. 4. The semiconductor integrated circuit device according to claim 1, wherein the plurality of MOSFETs form an output stage of a power device. 5. The semiconductor integrated circuit device according to claim 1, wherein the plurality of MOSFETs are n-channel MI.
A semiconductor integrated circuit device comprising an SFET and a p-channel type MISFET. 6. The semiconductor integrated circuit device according to claim 1, wherein the second semiconductor region of the first conductivity type is a buried layer for element isolation. 7. A source region having a conductivity type different from that of the channel layer is formed inside a channel layer formed on the main surface of the semiconductor substrate, and a source region having the same conductivity type as the channel layer formed on the main surface of the semiconductor substrate is formed. A method of manufacturing a semiconductor integrated circuit device comprising a plurality of lateral double-diffused MOSFETs for supplying a potential from one semiconductor region to the channel layer,
(A) The first surface is formed on the main surface of the first or second conductivity type semiconductor substrate.
After forming the conductive type buried layer, a first layer is formed on the semiconductor substrate.
Growing a conductive type epitaxial layer, (b) forming a first conductive type first semiconductor region whose bottom is in contact with the buried layer on the main surface of the first region of the epitaxial layer, (c) After forming the gate electrodes of the plurality of MOSFETs on the main surface of the second region separated from the first region of the epitaxial layer, the second electrode of the epitaxial layer is formed.
Ion-implanting impurities of the first conductivity type into the main surface of the region,
Forming a first conductivity type channel layer of the plurality of MOSFETs, and (d) ion-implanting a second conductivity type impurity into the main surface of the second region of the epitaxial layer to form a plurality of MOSFETs of the plurality of MOSFETs. Forming a source region and a drain region; (e) patterning the conductive film deposited on the epitaxial layer to form the plurality of M
A method of manufacturing a semiconductor integrated circuit device, comprising: forming an electrode connected to each of a source region and a drain region of an OSFET; and an electrode connected to the first semiconductor region. 8. A source region having a conductivity type different from that of the channel layer is formed inside a channel layer formed on the main surface of the semiconductor substrate, and a source region having the same conductivity type as the channel layer formed on the main surface of the semiconductor substrate is formed. A method of manufacturing a semiconductor integrated circuit device comprising a plurality of lateral double-diffused MOSFETs for supplying a potential from one semiconductor region to the channel layer,
(A) a step of forming a second conductivity type buried layer on the main surface of the second conductivity type semiconductor substrate and then growing a first conductivity type epitaxial layer on the semiconductor substrate; (b) a first of the epitaxial layers Forming a second semiconductor region of the second conductivity type whose bottom is in contact with the buried layer on the main surface of the region;
(C) After forming the gate electrodes of a plurality of MOSFETs on the main surface of the second region of the epitaxial layer separated from the first region, the second conductivity type is formed on the main surface of the second region of the epitaxial layer. Ion-implanting impurities to form second-conductivity-type channel layers of the plurality of MOSFETs; (d) ion-implanting impurities of the first-conductivity-type into the main surface of the second region of the epitaxial layer. Forming a source region and a drain region of the plurality of MOSFETs, (e) patterning a conductive film deposited on the epitaxial layer to form the plurality of MOSFETs.
And a step of forming an electrode connected to each of the source region and the drain region of T and an electrode connected to the first semiconductor region. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the ion implantation of impurities for forming the channel layer is performed by the plurality of MOSFEs.
A method of manufacturing a semiconductor integrated circuit device, wherein the gate electrode of T is used as a mask.