JPH0917953A - Protector for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the breakage of a device itself and an inner circuit by lessening the parasitic capacity in the case that a signal in normal voltage range is applied to a pad, and increasing the parasitic capacity only in the case that the abnormal voltage by static electricity of negative polarity is applied to the pad, so as to absorb energy of static electricity. SOLUTION: A second lightly doped diffusion layer 40 is provided under a pad 8, and this second lightly doped diffusion layer 40 and a first lightly doped diffusion layer 30 are provided apart. A second diffusion layer 16 is provided within the first lightly doped layer 30. Apart from this, a first diffusion resistor 4 is provided, and apart from this first diffusion resistor 4, a first diffusion layer 6 is provided. The second metallic wiring 18 to connect with the pad 8 is provided to cover a part of these between the second lightly doped diffusion layer 40 and the first lightly doped diffusion layer 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection device for protecting a semiconductor device from a high voltage such as static electricity applied to a pad of the semiconductor device.

[0002]

2. Description of the Related Art Generally, a protection device is used to protect an internal circuit of a semiconductor device from a high voltage such as static electricity.

FIG. 7 is a circuit diagram showing an example of an input circuit including a general pad, a protection device, and an internal circuit. FIG.
The circuit configuration of the input circuit will be described with reference to the circuit diagram of FIG.

The pad 8 is connected to the anode terminal of the protection diode 5a that constitutes the protection device 7 and one terminal of the first diffusion resistor 4 that constitutes the protection device. The other terminal of the diffusion resistor 4 is connected to the protection device 7
Is connected to the anode terminal of the protection diode 5n forming the internal circuit 3, the gate of the P-channel transistor 1 forming the internal circuit 3, and the gate of the N-channel transistor 2 forming the internal circuit 3.

The first power supply 9 is connected to one terminal of the P-channel transistor 1 forming the internal circuit 3 and the cathode terminals of the protection diodes 5a ... 5n forming the protection device 7, The power source 10 is connected to one terminal of the N-channel transistor 2 that constitutes the internal circuit 3.

Further, the other terminal of the P-channel transistor 1 forming the internal circuit 3 has an N terminal forming the internal circuit 3.
It is connected to the other terminal of the channel transistor 2.

FIG. 8 is a plan view showing the pattern layout of the conventional protection device 7 shown in FIG.
FIG. 9 is a cross-sectional view showing a state of a cross section taken along the line CC of FIG. 8. The configuration of a conventional protection device will be described with reference to FIGS. 8 and 9.

The protective device shown in FIG. 8 includes a P-type first diffusion resistor 4 for forming a region of a conductive impurity different from the N-type semiconductor substrate 60 on the N-type semiconductor substrate 60 shown in FIG.
An N-type first diffusion layer 6 formed around the P-type first diffusion resistor 4 separated from the P-type first diffusion resistor 4 with the same conductive impurities as those of the N-type semiconductor substrate 60; It consists of.

With the above structure, the P-type first diffusion resistor 4 and the N-type semiconductor substrate 60 form the PN junction protection diodes 5a ... 5n shown in FIG.

Next, the connection state of each constituent element of the conventional protection device shown in FIG. 8 will be described. The pad 8 is connected to the second metal wiring 18, and the second metal wiring 18 is connected to the P-type first diffusion resistor 4 through the second contact hole 22 for etching the insulating film 59 shown in FIG. It is connected to one terminal.

The other terminal of the P type first diffusion resistor 4 is connected to the third metal wiring 28 through the third contact hole 32 for etching the insulating film 59 shown in FIG. The metal wiring 28 of the internal circuit 3 and the gate of the P-channel transistor 1 forming the internal circuit 3 shown in FIG.
Is connected to the gate of the N-channel transistor 2.

Further, the first metal wiring 19 corresponding to the first power supply 9 shown in FIG. 7 has the N-type first diffusion through the first contact hole 12 for etching the insulating film 59 shown in FIG. It is connected to layer 6.

Static electricity consisting of a voltage of several KV to several tens of KV has positive and negative polarities, and the protection device must protect the internal circuit from this static electricity. Next, the operation of the conventional protection device will be described with reference to FIGS.

First, when static electricity of positive polarity is applied to the pad 8, the positive static electricity reaches the P type first diffusion resistor 4 from the pad 8 through the second metal wiring 18.

The protection device comprises a P-type first diffused resistor 4 and an N-type semiconductor substrate 60 shown in FIG.
Since 5n is formed, when a static electricity of positive polarity is applied to the pad 8, a forward operation is performed and N shown in FIG.
A current flows through the semiconductor substrate 60 of the N type, and the current flows through the first diffusion layer 6 of the N type to the first metal wiring 19.

Therefore, the protection diodes 5a ... 5
Since n is clamped by the threshold voltage value in the forward direction, no voltage higher than the threshold voltage in the forward direction is applied to the internal circuit 3 shown in FIG.

On the other hand, when the negative static electricity is applied to the pad 8, the negative static electricity is applied from the pad 8 to the second metal wiring 18
To reach the P-type first diffused resistor 4.

However, a forward current does not flow through the protection diodes 5a ... 5n like static electricity of positive polarity, and the PN junction between the P-type first diffused resistor 4 and the N-type semiconductor substrate 60 is A current flows where it exceeds the breakdown voltage, protecting the internal circuits.

The P type first diffused resistor 4 inserted in series between the pad 8 and the internal circuit 3 shown in FIG. 7 functions as a resistance element and appears in the third metal wiring 28. It has a role of lowering the voltage, that is, the voltage applied to the internal circuit 3 shown in FIG.

[0020]

FIG. 10 is an equivalent circuit diagram showing a parasitic capacitance in a conventional protection device. By the way, parasitic capacitances C1 and C2 shown in FIG. 10 are parasitically connected to the circuit configurations shown in FIGS.

The parasitic capacitance C1 is the parasitic capacitance of the pad 8. That is, the pad 8 shown in FIG. 9 is used as one electrode,
This is the insulating layer capacitance between the field oxide film 58 and the insulating film 59, using the N-type semiconductor substrate 60 as the other electrode.

The parasitic capacitance C2 is the parasitic capacitance of the protection device 7. That is, it is a PN junction capacitance in which the P-type first diffusion resistor 4 is used as one electrode and the N-type semiconductor substrate 60 is used as the other electrode.

The electrostatic breakdown withstand capability, which is the ability to protect the internal circuit of a semiconductor device from a high voltage such as static electricity, is generally related to the capacity of the protective device. The larger the capacity of this protective device, the greater the electrostatic breakdown withstand capability. .

It is considered that this is because a part of the energy of static electricity applied to the semiconductor device from the outside is absorbed by this capacitance.

As a concrete example, when the area of the P-type first diffused resistor 4 shown in FIGS. 8 and 9 is increased, the P-type first diffused resistor 4 and the N-type semiconductor substrate 60 are formed. Between P
Since the area of the N-junction increases, the parasitic capacitance C2 also increases, and the electrostatic breakdown withstand capacity also increases.

However, the larger the capacity of the input circuit of the semiconductor device, the lower the circuit operating speed of the semiconductor device. The designer of the semiconductor device has to design the circuit focusing on the fact that the circuit operation speed of the semiconductor device and the electrostatic breakdown withstanding capability are in a contradictory relationship, and the design constraint becomes large. There is also a fundamental problem that it cannot be applied to a semiconductor device that requires high-speed operation.

As a method of reducing the parasitic capacitance of the protection device 7, a P-type first diffused resistor 4 and an N-type semiconductor substrate 6 are used.
It is most effective to reduce the area of the PN junction between 0 and 0, that is, the area of the protection diode, but this is not preferable because the electrostatic discharge withstand capability may be extremely reduced.

Therefore, a method of reducing the parasitic capacitance of the pad 8 can be considered. FIG. 11 shows another example of the conventional protection device. This will be described with reference to FIG. FIG. 11 shows FIG.
In the structure of the cross section shown in FIG. 5, a P-type second low-concentration diffusion layer 40 for forming a region of a conductive impurity different from that of the N-type semiconductor substrate 60 on the surface of the N-type semiconductor substrate 60 below the pad 8.
Is provided.

The P type second low concentration diffusion layer 40 is electrically floating.

FIG. 12 is an equivalent circuit diagram showing the parasitic capacitance in the conventional protection device. Parasitic capacitances C1, C2, and C3 shown in FIG. 12 are parasitically connected to the circuit configuration shown in FIG.

The parasitic capacitors C1 and C2 have the same structure as the equivalent circuit of the conventional example shown in FIG. The parasitic capacitance C3 is the parasitic capacitance of the pad 8 generated by providing the P-type second low-concentration diffusion layer 40. That is, the P-type second low-concentration diffusion layer 40 and the N-type semiconductor substrate having the insulating layer of the field oxide film 58 and the insulating film 59 as one electrode and the N-type semiconductor substrate 60 as the other electrode. PN junction capacitance with 60.

Since the parasitic capacitances C1 and C3 are connected in series as shown in FIG. 12, the combined capacitance Cp of the parasitic capacitances C1 and C3 is expressed by the following equation. Cp = (C1 × C3) / (C1 + C3) As represented by this formula, the parasitic capacitance of the pad 8 becomes small. From this, it can be seen that the circuit operation speed of the semiconductor device is improved in the configuration shown in FIG. 11 than in the configuration shown in FIG.

However, since the capacitance of the input circuit of the semiconductor device is the combined capacitance of the capacitance of the pad 8 and the capacitance of the protection device 7, the problem that the electrostatic breakdown withstand capability will be reduced regardless of which capacitance is smaller. There is.

As is clear from the above description, the circuit operation speed of the semiconductor device is improved by reducing the capacitance of the input circuit of the semiconductor device, and the electrostatic breakdown withstand capability is improved by increasing the capacitance of the input circuit of the semiconductor device. There is a problem that it cannot be compatible with improvement.

In order to solve these problems, the object of the present invention is that when the semiconductor device is operating at a normal circuit operating voltage, the capacitance of the input circuit of the semiconductor device is small and a high voltage due to static electricity or the like is applied to the pad. Only when applied, the capacitance of the input circuit of the semiconductor device is increased.

Thus, a semiconductor device protection device is provided which has an improved electrostatic breakdown resistance without lowering the circuit operation speed of the semiconductor device.

[0037]

To achieve the above object, a semiconductor device protection device according to the present invention comprises a semiconductor substrate,
A second low-concentration diffusion layer that forms a region of a conductive impurity different from that of the semiconductor substrate and a region of a conductive impurity different from the semiconductor substrate that is provided apart from the second low-concentration diffusion layer are formed in the semiconductor substrate. A first low-concentration diffusion layer, a second diffusion layer that forms a region of an impurity having the same conductivity as the first low-concentration diffusion layer provided in the first low-concentration diffusion layer, and a first diffusion layer on the semiconductor substrate.
And a first diffusion resistance that forms a region of a conductive impurity different from that of the semiconductor substrate, which is provided separately from the low-concentration diffusion layer, and is formed separately from the first diffusion resistance with the same conductive impurity as that of the semiconductor substrate. A first diffusion layer, the second low-concentration diffusion layer is provided under the pad, and the first diffusion layer is connected to the first metal wiring through the first contact hole, One terminal of the diffusion resistor is connected to the second metal wiring connected to the pad through the second contact hole, and the second diffusion layer is connected to the fourth metal wiring through the fourth contact hole. The second metal wiring is provided so as to cover a part of the second low concentration diffusion layer and the first low concentration diffusion layer.

[0038]

On the surface of the semiconductor substrate below the pad, a second low-concentration diffusion layer which is different in conductivity from the semiconductor substrate and electrically floating is provided. A second diffusion layer provided in the first low concentration diffusion layer is provided separately from the second low concentration diffusion layer. The fourth metal wiring connected to the second power supply is connected to the second diffusion layer via the fourth contact hole. Second
The second metal wiring connected to the pad is provided between the low-concentration diffusion layer and the first low-concentration diffusion layer.

When a negative polarity static electricity is applied to the pad,
An inversion layer is formed on the semiconductor substrate below the field oxide film covered with the second metal wiring, the second low concentration diffusion layer and the first low concentration diffusion layer are electrically connected, and the parasitic capacitance of the pad is reduced. growing. This makes it possible to prevent the protection device itself and the internal circuit from being destroyed.

[0040]

1 is a plan view showing a pattern layout of a protective device comprising a protective terminal and a protective diode showing a first embodiment of the present invention, and FIG. 2 is a cutting line A shown in FIG. It is a sectional view showing a situation of a section of an A section. FIG.
FIG. 3 is a circuit diagram showing an example of an input circuit including a pad, a protection device, and an internal circuit. The configuration of the protection device of the present invention will be described with reference to FIGS. 1, 2, and 7.

First, the structure of the protection diode will be described.
The protection diode constituting the protection device shown in FIGS. 1 and 7 is a P-type first diode which forms a region of a conductive impurity different from that of the N-type semiconductor substrate 60 in the N-type semiconductor substrate 60 shown in FIG. Diffusion resistor 4 and an N-type first diffusion resistor 4 formed apart from the P-type first diffusion resistor 4 by the same conductive impurities as the N-type semiconductor substrate 60 and formed around the P-type first diffusion resistor 4. And one diffusion layer 6.

With the above configuration, the P-type first diffusion resistor 4
And the N-type semiconductor substrate 60 form PN junction protection diodes 5a ... 5n.

Next, the structure of the protective terminal will be described. A P-type second low-concentration diffusion layer 40 that forms a region of a conductive impurity different from the N-type semiconductor substrate 60 in the N-type semiconductor substrate 60 below the pad 8, and a P-type second low-concentration diffusion layer 40. Diffusion layer 4
The P-type first low-concentration diffusion layer 30 forming the same conductive impurity region as 0 is provided in parallel with the P-type second low-concentration diffusion layer 40 so as to be separated therefrom.

In the P-type first low-concentration diffusion layer 30, a P-type second diffusion layer 16 forming the same conductive impurity region as that of the P-type first low-concentration diffusion layer 30 is provided. .

The protective terminal is formed by the above structure. The protective terminal and the protective diode constitute the protective device of the present invention. Next, the connection state of each component shown in FIGS. 1 and 2 will be described.

The pad 8 is connected to the second metal wiring 18,
The second metal wiring 18 is formed of the P-type first through the second contact hole 22 for etching the insulating film 59 shown in FIG.
It is connected to one terminal of the diffused resistor 4. In addition, the second metal wiring 18 is provided between the P-type second low-concentration diffusion layer 40 and the P-type first low-concentration diffusion layer 30 and is formed between the P-type second low-concentration diffusion layer 40 and the second low-concentration diffusion layer 40. And a part of the P-type first low-concentration diffusion layer 30 are provided.

The other terminal of the P type first diffused resistor 4 is connected to the third metal wiring 28 through the third contact hole 32 for etching the insulating film 59 shown in FIG. The metal wiring 28 of No. 3 is connected to the internal circuit 3 shown in FIG.

The first metal wiring 19 connected to the first power supply 9 shown in FIG. 7 has the N-type first diffusion layer through the first contact hole 12 for etching the insulating film 59 shown in FIG. Connect to 6.

Fourth connection to second power supply 10 shown in FIG.
The metal wiring 20 is connected to the P type second diffusion layer 16 through the fourth contact hole 42 for etching the insulating film 59 shown in FIG.

FIG. 12 is an equivalent circuit diagram showing the parasitic capacitance in the protection device. With the above configuration, parasitic capacitances C1, C2 and C3 are connected to the protection device of the present invention as shown in FIG.

Here, the parasitic capacitance C1 is an insulating layer capacitance composed of the field oxide film 58 and the insulating film 59 shown in FIG.
The parasitic capacitance C2 corresponds to the P-type first diffusion resistor 4 and N shown in FIG.
Type semiconductor substrate 60 and PN junction capacitance, parasitic capacitance C3
Is a PN junction capacitance between the P-type second low-concentration diffusion layer 40 and the N-type semiconductor substrate 60 shown in FIG.

The parasitic capacitances C1 and C3 are connected in series, and the parasitic capacitances C1 and C3 and the parasitic capacitance C2 are connected in parallel.

Next, the operation of the protection device of the present invention will be described with reference to FIGS. 1, 2 and 3. FIG. 3 is an enlarged view of a dotted area 89 surrounded by a square in FIG.

First, when static electricity of positive polarity is applied to the pad 8 shown in FIG. 1, positive static electricity passes from the pad 8 shown in FIG. 1 to the P type first diffusion resistor 4 through the second metal wiring 18. To reach.

As described above, the P-type first diffusion resistor 4
Since the protection diode is formed by the N-type semiconductor substrate 60 and the N-type semiconductor substrate 60, the protection diode operates in the forward direction and a current flows through the N-type semiconductor substrate 60, and the current passes through the N-type first diffusion layer 6. It flows to the first metal wiring 19.

Therefore, in order to clamp the threshold voltage value in the forward direction, the third circuit connected to the internal circuit 3 shown in FIG.
No more than the forward threshold voltage is applied to the metal wiring 28. The above operation is no different from that of the conventional protection device.

On the other hand, when a negative polarity static electricity is applied to the pad 8 shown in FIG. 1, a negative electric field is generated under the second metal wiring 18 by the negative static electricity, so that P shown in FIG.
Of the inversion layer 1 on the surface of the N-type semiconductor substrate 60 between the P-type first low-concentration diffusion layer 40 and the P-type first low-concentration diffusion layer 40.
00 is formed, and the inversion layer 100 electrically connects the P-type second low-concentration diffusion layer 40 and the P-type first low-concentration diffusion layer 30.

The second power source 1 shown in FIG. 7 is provided on the P-type second low-concentration diffusion layer 40 through the P-type first low-concentration diffusion layer 30.
A potential of 0 is supplied. That is, the potential between the parasitic capacitance C1 and the parasitic capacitance C3 shown in FIG. 12 becomes the potential of the second power supply 10, and both ends of the parasitic capacitance C3 are electrically fixed,
Substantially the parasitic capacitance of the pad 8 is only the parasitic capacitance C1.

As a result, the capacitance parasitic on the pad 8 increases. Part of the negative electrostatic energy is absorbed by the large parasitic capacitance appearing on the pad 8.

Negative static electricity is generated from the pad 8 shown in FIG.
Of the P-type first diffusion resistor 4 through the metal wiring 18 of FIG.

As described above, the P-type first diffusion resistor 4 is used.
Since the protection diode is formed by the N-type semiconductor substrate 60 and the N-type semiconductor substrate 60, the protection diode causes a current to flow where it exceeds the breakdown voltage of the PN junction.

A large parasitic capacitance appearing on the pad 8 absorbs static electricity energy and a voltage clamp by the breakdown operation of the protection diode protects the internal circuit from a high static voltage applied from the outside.

On the other hand, when a signal in the normal voltage range for driving the semiconductor device is applied to the pad 8, the electric field applied to the second metal wiring 18 is weak, so that the P-type second low-concentration diffusion layer 40 is formed. The inversion layer 100 is not formed below the second metal wiring 18 between the P-type first low-concentration diffusion layer 30 and the parasitic capacitance in the circuit using this protection device is the parasitic capacitance shown in FIG. Since it is the combined capacitance of C1 and C3, it is small and does not affect the circuit operation speed.

The configuration and internal operation of this embodiment have been described above, but the present invention is not limited to these configurations.

FIG. 5 is a plan view showing a pattern layout of a protection device representing a second embodiment of the present invention, and FIG. 6 shows a cross section of a cutting line BB shown in FIG. FIG. The configuration of the protection device of the present invention will be described with reference to FIGS. 5 and 6.

The structure of the protection device representing the second embodiment is such that the second metal wiring 18 between the P type second low concentration diffusion layer 40 and the P type first low concentration diffusion layer 30 is formed. At the bottom of the
Of the polysilicon electrode 50 so as to cover the entire area between the second low concentration diffusion layer 40 of the P type and the first low concentration diffusion layer 30 of the P type.
Is provided.

As for the connection state of the constituent elements representing the second embodiment, the second metal wiring 18 and the polysilicon electrode 50 are provided through the fifth contact hole 52 for etching the insulating film 59 shown in FIG. . This polysilicon electrode 50
The connection state is the same as that of the first embodiment except that the above is provided.

Next, the operation will be described with reference to FIGS. 5 and 6.

When static electricity having a positive polarity is applied to the pad 8 shown in FIG. 5, the operation is the same as that of the first embodiment, and the description thereof is omitted.

When static electricity of negative polarity is applied to pad 8 shown in FIG. 5, a negative electric field is generated under second metal interconnection 18 and polysilicon electrode 50 by the negative static electricity.

The polysilicon electrode 50 is provided on the field oxide film 58, as shown in FIG. This allows
The distance between the pad 8 and the N-type semiconductor substrate 60 is substantially reduced by the amount of the insulating film 59.

Therefore, the second embodiment of the present invention is the first embodiment.
It can be seen that the electric field applied to the N-type semiconductor substrate 60 is larger in the second embodiment when static electricity of the same voltage is applied to the pad 8 than in the second embodiment.

As described above, since the inversion layer 100 is formed in proportion to the strength of the applied electric field, it is possible to form the inversion layer 100 from a voltage having a lower electrostatic voltage applied to the pad 8.

The inversion layer 100 electrically connects the P-type second low-concentration diffusion layer 40 and the P-type first low-concentration diffusion layer 30.

The second power source 1 shown in FIG. 7 is provided to the P-type second low-concentration diffusion layer 40 through the P-type first low-concentration diffusion layer 30.
A potential of 0 is supplied. That is, the potential between the parasitic capacitance C1 and the parasitic capacitance C3 shown in FIG. 12 becomes the potential of the second power supply 10, and both ends of the parasitic capacitance C3 are electrically fixed,
Substantially the parasitic capacitance of the pad 8 is only the parasitic capacitance C1.

As a result, the capacitance parasitic on the pad 8 increases. Part of the negative electrostatic energy is absorbed by the large parasitic capacitance appearing on the pad 8.

The operation after forming the inversion layer 100 is the same as that of the first embodiment, and therefore its explanation is omitted.

In the second embodiment shown in FIG. 5, the P-type second
The polysilicon electrode 50 is provided so as to cover the entire area between the low-concentration diffusion layer 40 and the P-type first low-concentration diffusion layer 30. The longer the distance that the first low-concentration diffusion layer 30 of the mold faces is, the more the amount of electric charge flowing between these two low-concentration diffusion layers increases, which facilitates electrical connection, which is preferable.

Further, in the first and second embodiments of the present invention, the P-type second low concentration diffusion layer 40 and the P-type first
The low-concentration diffusion layer 30 is separated from the low-concentration diffusion layer 30 in parallel, but different installation structures, for example, the P-type second low-concentration diffusion layer 40 and the P-type first low-concentration diffusion layer 30 Of course, the shape of the facing portions may be uneven.

Furthermore, the shorter the distance between the P-type second low-concentration diffusion layer 40 and the P-type first low-concentration diffusion layer 30, the more electrical connection these two low-concentration diffusion layers have. Therefore, the distance between the P-type second low-concentration diffusion layer 40 and the P-type first low-concentration diffusion layer 30 may be the minimum dimension of the design rule for manufacturing the semiconductor device. .

The P-type second low-concentration diffusion layer 40 may have a different impurity concentration or the same impurity concentration as the P-type first low-concentration diffusion layer 30. When the same impurity concentration is used, the P-type first low-concentration diffusion layer 30 is used.
Since it can be formed in the same step as the step of forming, the number of manufacturing steps is not increased.

Furthermore, the shape and material of the polysilicon electrode 50 shown in the second embodiment are not limited to those shown in FIGS. 5 and 6, but the P-type second low concentration diffusion layer 40 and the P-type second low-concentration diffusion layer 40 may be used. It may be formed so as to cover a part of the first low concentration diffusion layer 30. Needless to say, various changes can be made as long as the material can be connected to the pad 8.

While having the same shape as the pattern layout of the plan view as shown in FIG. 1 of the present embodiment, the N type first diffusion resistor 4 and the P type first substrate 4 are formed on the P type semiconductor substrate 60. The diffusion layer 6 is formed, the N-type first low-concentration diffusion layer 30 is provided, and the N-type second low-concentration diffusion layer 30 is formed in the N-type first low-concentration diffusion layer 30.
The diffusion layer 16 may be formed, and the N-type second low concentration diffusion layer 40 may be provided below the pad 8.

In the embodiment of the present invention, the operation characteristic of the present invention is performed when the negative polarity static electricity is applied to the pad 8.

However, this P-type semiconductor substrate 60
In the case of using, the characteristic operation of the present invention is performed when static electricity of positive polarity is applied to the pad 8. This will be described with reference to FIGS. 1 and 4.

FIG. 4 is an enlarged view of a dotted line area 89 surrounded by a square in FIG.

When a static electricity of positive polarity is applied to the pad 8 shown in FIG. 1, a positive electric field is generated under the second metal wiring 18 by the positive static electricity, so that the N-type second electrode shown in FIG. Low concentration diffusion layer 40 and N-type first low concentration diffusion layer 30
The inversion layer 100 is formed on the surface of the P-type semiconductor substrate 60 between and, and the inversion layer 100 separates the N-type second low-concentration diffusion layer 40 and the N-type first low-concentration diffusion layer 30. Connect electrically.

The second power source 1 shown in FIG. 7 is provided to the N type second low concentration diffusion layer 40 via the N type first low concentration diffusion layer 30.
A potential of 0 is supplied. That is, the potential between the parasitic capacitance C1 and the parasitic capacitance C3 shown in FIG. 12 becomes the potential of the second power supply 10, and both ends of the parasitic capacitance C3 are electrically fixed,
Substantially the parasitic capacitance of the pad 8 is only the parasitic capacitance C1.

That is, a large parasitic capacitance appears on the pad 8, and a part of the positive electrostatic energy is absorbed by this large parasitic capacitance.

As is clear from the above description, the P-type semiconductor substrate 60 has the same N-type first pattern as the pattern layout of the plan view shown in FIG.
Diffusion resistance 4 and a P-type first diffusion layer 6 are formed, an N-type first low-concentration diffusion layer 30 is provided, and an N-type first low-concentration diffusion layer 30 is formed in the N-type first low-concentration diffusion layer 30. Forming a second diffusion layer 16,
Even if the N-type second low-concentration diffusion layer 40 is provided under the pad 8, it is possible to provide the protection device having the features of the present invention.

In the plan view showing the pattern layout of the protection device of this embodiment shown in FIGS. 1 and 2, the protection terminal and the protection diode are arranged side by side, but the installation relationship between the protection terminal and the protection diode is shown. Of course, the present invention is not limited to this, and it goes without saying that the protective terminal and the protective diode may be largely separated from each other.

In any case, various modifications can be made without departing from the spirit of the present invention.

[0093]

The protective device of the present invention comprises a protective terminal and a protective diode. The protective terminal has a conductive second low-concentration diffusion layer provided under the pad, which is different from the semiconductor substrate,
A first low-concentration diffusion layer is provided separately from the second low-concentration diffusion layer. A second diffusion layer is provided in the first low concentration diffusion layer. The protection diode is provided with a first diffusion resistance spaced apart from the first low-concentration diffusion layer, and a first diffusion layer formed away from the first diffusion resistance.

The second metal wiring 18 connected to the pad is provided between the second low concentration diffusion layer and the first low concentration diffusion layer.

When a signal of a normal voltage for driving the semiconductor device is applied to the pad, the parasitic capacitance of the circuit including this protection device is small and does not affect the circuit operation.

On the other hand, when a negative abnormal voltage due to static electricity is applied to the pad, the second low concentration diffusion layer and the second diffusion layer are electrically connected by the inversion layer due to the negative electric field applied to the formation of the second metal wiring. The parasitic capacitance of the circuit including the protection device changes to a large value and absorbs the electrostatic energy.

As a result, since a large amount of static energy is not applied to the protective terminal, it is possible to prevent the internal circuit from being destroyed without destroying the protective device itself.

Further, since the parasitic capacitance formed in the protective terminal is formed under the pad, it does not press the layout area of the semiconductor device, and it is compact and can provide a high electrostatic breakdown resistance.

Further, the present invention can be applied to a semiconductor device which requires high-speed circuit operation, and its effect is very large.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor device protection device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a protection device for a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a part of a semiconductor device protection device according to an embodiment of the present invention.

FIG. 4 is a sectional view showing a part of a semiconductor device protection device according to an embodiment of the present invention.

FIG. 5 is a plan view showing a semiconductor device protection device according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a semiconductor device protection device according to an embodiment of the present invention.

FIG. 7 is a circuit diagram showing an input circuit of a semiconductor device.

FIG. 8 is a plan view showing a protection device for a semiconductor device.

FIG. 9 is a cross-sectional view showing a protection device for a semiconductor device.

FIG. 10 is a circuit diagram showing a connection of parasitic capacitance.

FIG. 11 is a cross-sectional view showing a protection device for a semiconductor device.

FIG. 12 is a circuit diagram showing a connection of parasitic capacitance.

[Explanation of symbols]

 4 First Diffusion Resistance 5 Protection Diode 6 First Diffusion Layer 8 Pad 12 First Contact Hole 22 Second Contact Hole 32 Third Contact Hole 42 Fourth Contact Hole 18 Second Metal Wiring 19 1st Metal wiring 20 Fourth metal wiring 28 Third metal wiring 30 First low-concentration diffusion layer 40 Second low-concentration diffusion layer

Claims (8)

[Claims] 1. A semiconductor substrate, a second low-concentration diffusion layer for forming a region of a conductive impurity different from that of the semiconductor substrate on the semiconductor substrate, and a semiconductor substrate provided separately from the second low-concentration diffusion layer. A first low-concentration diffusion layer forming a conductive impurity region, and a second low-concentration diffusion layer provided in the first low-concentration diffusion layer and forming the same conductive impurity region as the first low-concentration diffusion layer.
And a second low-concentration diffusion layer provided under the pad, and the second diffusion layer is connected to the fourth metal wiring connected to the second power source through the fourth contact hole. Then, the second metal wiring connected to the pad is provided so as to cover a part of the second low-concentration diffusion layer and the first low-concentration diffusion layer. 2. A semiconductor substrate, a second low-concentration diffusion layer for forming a region of a conductive impurity different from that of the semiconductor substrate on the semiconductor substrate, and a semiconductor substrate provided separately from the second low-concentration diffusion layer. A first low-concentration diffusion layer forming a conductive impurity region, and a second low-concentration diffusion layer provided in the first low-concentration diffusion layer and forming the same conductive impurity region as the first low-concentration diffusion layer.
Second diffusion layer and a polysilicon electrode, the second low-concentration diffusion layer is provided under the pad, and the second diffusion layer is connected to the second power supply through the fourth contact hole. Connected to the second metal wiring through the fifth contact hole, the second metal wiring connected to the pad, and the polysilicon electrode connected to the second low-concentration diffusion layer. And a first low concentration diffusion layer so as to cover a part of the first low concentration diffusion layer. 3. A semiconductor substrate, a second low-concentration diffusion layer that forms a region of conductive impurities different from that of the semiconductor substrate on the semiconductor substrate, and a semiconductor substrate provided separately from the second low-concentration diffusion layer. A first low-concentration diffusion layer forming a conductive impurity region, and a second low-concentration diffusion layer provided in the first low-concentration diffusion layer and forming the same conductive impurity region as the first low-concentration diffusion layer.
And a second low-concentration diffusion layer provided under the pad, and the second diffusion layer is connected to the fourth metal wiring connected to the second power source through the fourth contact hole. The second metal wiring connected to the pad is provided so as to cover a part of the second low-concentration diffusion layer and the first low-concentration diffusion layer, and the second low-concentration diffusion layer and the first low-concentration diffusion layer are provided. A protective device for a semiconductor device, characterized in that the distance from the diffusion layer is separated by the minimum dimension specified in the design rule. 4. A semiconductor substrate, a second low-concentration diffusion layer for forming a region of a conductive impurity different from that of the semiconductor substrate on the semiconductor substrate, and a semiconductor substrate provided separately from the second low-concentration diffusion layer. A first low-concentration diffusion layer forming a conductive impurity region, and a second low-concentration diffusion layer provided in the first low-concentration diffusion layer and forming the same conductive impurity region as the first low-concentration diffusion layer.
And a second low-concentration diffusion layer provided under the pad, and the second diffusion layer is connected to the fourth metal wiring connected to the second power source through the fourth contact hole. The second metal wiring connected to the pad is provided so as to cover a part of the second low-concentration diffusion layer and the first low-concentration diffusion layer, and the second low-concentration diffusion layer and the first low-concentration diffusion layer are provided. A semiconductor device protection device having the same impurity concentration as that of the diffusion layer. 5. A semiconductor substrate, a second low-concentration diffusion layer that forms a region of a conductive impurity different from that of the semiconductor substrate on the semiconductor substrate, and a semiconductor substrate that is provided separately from the second low-concentration diffusion layer. A first low-concentration diffusion layer forming a conductive impurity region, and a second low-concentration diffusion layer provided in the first low-concentration diffusion layer and forming the same conductive impurity region as the first low-concentration diffusion layer.
And a second low-concentration diffusion layer provided under the pad, and the second diffusion layer is connected to the fourth metal wiring connected to the second power source through the fourth contact hole. The second metal wiring connected to the pad is provided so as to cover a part of the second low-concentration diffusion layer and the first low-concentration diffusion layer, and the second low-concentration diffusion layer and the first low-concentration diffusion layer are provided. The distance from the diffusion layer is separated by the minimum dimension specified in the design rule, and the impurity concentration of the second low-concentration diffusion layer is the same as that of the first low-concentration diffusion layer. Protective device. 6. A semiconductor substrate, a second low-concentration diffusion layer for forming a region of a conductive impurity different from that of the semiconductor substrate on the semiconductor substrate, and a semiconductor substrate provided separately from the second low-concentration diffusion layer. A first low-concentration diffusion layer forming a conductive impurity region, and a second low-concentration diffusion layer provided in the first low-concentration diffusion layer and forming the same conductive impurity region as the first low-concentration diffusion layer.
Second diffusion layer and a polysilicon electrode, the second low-concentration diffusion layer is provided under the pad, and the second diffusion layer is connected to the second power supply through the fourth contact hole. Connected to the second metal wiring through the fifth contact hole, the second metal wiring connected to the pad, and the polysilicon electrode connected to the second low-concentration diffusion layer. And the first low-concentration diffusion layer so as to cover a part thereof, and the second low-concentration diffusion layer and the first low-concentration diffusion layer are separated from each other by the minimum dimension defined in the design rule, A semiconductor device protection device, wherein the second low concentration diffusion layer and the first low concentration diffusion layer have the same impurity concentration. 7. A semiconductor substrate, a second low-concentration diffusion layer that forms a region of conductive impurities different from the semiconductor substrate on the semiconductor substrate, and a semiconductor substrate provided separately from the second low-concentration diffusion layer. A first low-concentration diffusion layer forming a conductive impurity region, and a second low-concentration diffusion layer provided in the first low-concentration diffusion layer and forming the same conductive impurity region as the first low-concentration diffusion layer.
Diffusion layer, a first diffusion resistor that forms a region of a conductive impurity different from that of the semiconductor substrate, which is provided on the semiconductor substrate separately from the first low-concentration diffusion layer, and a first diffusion resistance that is the same as the semiconductor substrate. A first diffusion layer formed apart from the first diffusion resistance, the second low-concentration diffusion layer is provided under the pad, and the first diffusion layer is formed through the first contact hole to form the first diffusion layer. Connected to the first metal wiring connected to the power supply of the second diffusion layer, and one terminal of the first diffusion resistor is connected to the second metal wiring connected to the pad through the second contact hole. Is connected to a fourth metal wiring connected to the second power supply through the fourth contact hole, and the second metal wiring is part of the second low-concentration diffusion layer and the first low-concentration diffusion layer. A protection device for a semiconductor device, which is provided so as to cover the semiconductor device. 8. A semiconductor substrate, a second low-concentration diffusion layer for forming a region of a conductive impurity different from that of the semiconductor substrate on the semiconductor substrate, and a semiconductor substrate provided separately from the second low-concentration diffusion layer. A first low-concentration diffusion layer forming a conductive impurity region, and a second low-concentration diffusion layer provided in the first low-concentration diffusion layer and forming the same conductive impurity region as the first low-concentration diffusion layer.
Diffusion layer, a first diffusion resistor that forms a region of a conductive impurity different from that of the semiconductor substrate, which is provided on the semiconductor substrate separately from the first low-concentration diffusion layer, and a first diffusion resistance that is the same as the semiconductor substrate. A first diffusion layer formed apart from the first diffusion resistance and a polysilicon electrode, the second low-concentration diffusion layer is provided under the pad, and the first diffusion layer is the first contact hole. Connected to a first metal wiring connected to a first power supply via, and one terminal of the first diffusion resistor connected to a second metal wiring connected to a pad via a second contact hole, The second diffusion layer is connected to the fourth metal wiring connected to the second power source through the fourth contact hole, and the polysilicon electrode is connected to the second metal wiring through the fifth contact hole. , The polysilicon electrode has a second low concentration diffusion layer and a first low concentration diffusion layer. Protection apparatus for a semiconductor device, characterized in that provided so as to cover a portion of the diffusion layer.