JPH0917868A - Wiring connection structure of semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PURPOSE: To mitigate an area reduction of a via contact accompanied by fining of wirings in a semiconductor integrated circuit. CONSTITUTION: A lower layer wiring 1 and an upper layer wiring 4 are constructed with materials different from each other, and a via contact 3 of an opening area larger than an area where the lower layer wiring 1 and the upper layer wiring 4 are superimposed on each other is formed. Accordingly, an increase in contact resistance between wirings accompanying an area reduction of the via contact 3 disappears, and also a disconnection in the via contact 3 is prevented and further a margin for mask alignment of the via contact 3 increases.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring connection structure of a semiconductor integrated circuit device in which upper and lower wiring layers are connected to each other through an opening formed in an interlayer insulating film therebetween, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit device in which various elements such as transistors are formed on a semiconductor substrate,
Wirings are formed in multiple layers on the substrate in order to electrically connect the elements or the elements and the peripheral circuits. A polycrystalline silicon film, a refractory metal film, a refractory metal silicide film, an aluminum alloy film, or the like is used for these wirings.

FIG. 5 and FIG. 6 show a connection structure between multilayer interconnections in a conventional semiconductor integrated circuit device. 5 is a plan view, and FIG. 6A is a cross-sectional view taken along the line AA of FIG.
FIG. 6B is a sectional view taken along the line BB of FIG.

As shown in FIG. 6, a silicon oxide film 115 is formed on a semiconductor substrate 114, and the first layer wiring 1 made of, for example, aluminum is formed on the silicon oxide film 115.
10 are formed. On the silicon oxide film 115,
An interlayer insulating film 111 is formed so as to cover the first layer wiring 110, and an opening portion for electrically connecting the first layer wiring 110 and a second layer wiring 113 described later to each other in the interlayer insulating film 111. 112 is formed. This opening 112
5 is formed inside a region where the first layer wiring 110 and the second layer wiring 113 overlap each other as shown in FIG. 5, and as shown in FIG. A second layer wiring 113 made of, for example, aluminum is formed so as to contact the layer wiring 110.

Next, a method of manufacturing the above structure will be described with reference to FIGS. In each of FIGS. 7 and 8, the division diagrams (a) and (b) correspond to the division diagrams (a) and (b) of FIG. 6, respectively.

First, as shown in FIG.
After the silicon oxide film 115 is formed on the silicon oxide film 4, the first layer wiring 110 is formed in a predetermined pattern on the silicon oxide film 115. Then, an interlayer insulating film 111 is formed on the silicon oxide film 115 so as to cover the first layer wiring 110. After that, a photoresist film 116 is formed on the interlayer insulating film 111, and the photoresist film 116 is patterned into a predetermined shape. Then, using the patterned photoresist film 116 as a mask, the interlayer insulating film 111 is selectively removed by wet etching using dilute hydrofluoric acid solution and anisotropic etching such as reactive ion etching to form the opening 112. To do.

Next, as shown in FIG. 8, after removing the photoresist film 116, a conductive film 113 is formed on the entire surface of the interlayer insulating film 111 including the opening 112 by the reactive sputtering method. Then, a photoresist film 118 is formed on the conductive film 113, and the photoresist film 118 is formed.
Is patterned into a predetermined shape. Then, the conductive film 113 is selectively removed by reactive ion etching using the patterned photoresist film 118 as a mask, and the second layer wiring 113 having a pattern electrically connected to the first layer wiring 110 in the opening 112. To form.

[0008]

In the above-mentioned conventional wiring connection structure, as shown in FIG. 5, the opening area of the opening 112 is set so as to connect the first layer wiring 110 and the second layer wiring 113. In order to reliably perform the above, it is necessary to make the size smaller than the region where the first layer wiring 110 and the second layer wiring 113 overlap each other.

For this reason, for example, if the wiring width of either the first layer wiring 110 or the second layer wiring 113 becomes narrower due to the recent demand for miniaturization, the opening area of the opening 112 will inevitably become larger. As a result, the first layer wiring 110 is narrowed.
The contact area between the second layer wiring 113 and the second layer wiring 113 is reduced to increase the contact resistance between them, or the opening 11
There was a problem that a wire breakage might occur inside the No. 2. Further, if the wiring width of either the first-layer wiring 110 or the second-layer wiring 113 becomes narrow, there is a problem that the mask alignment accuracy when forming the opening 112 becomes strict.

Therefore, an object of the present invention is to increase the contact resistance between the wirings connected to each other in the opening formed in the interlayer insulating film even when the wiring width of the multilayer wiring of the semiconductor integrated circuit device is narrowed. And a wiring connection structure of a semiconductor integrated circuit device capable of preventing disconnection within an opening and relaxing the strictness of alignment accuracy of a patterning mask when forming an opening in an interlayer insulating film, and manufacturing thereof. Is to provide a method.

[0011]

A wiring connection structure for a semiconductor integrated circuit device according to the present invention, which solves the above-mentioned problems, has a first wiring formed on a base insulating film and a first wiring formed on the first wiring. An interlayer insulating film formed on the interlayer insulating film and a second wiring formed on the interlayer insulating film, and the first wiring and the second wiring are formed through an opening formed in the interlayer insulating film. In a wiring connection structure of a semiconductor integrated circuit device in which wiring is electrically connected to each other, the opening portion includes a mutual overlapping area of the first wiring and the second wiring, Is also greatly opened.

In one aspect of the present invention, the opening is formed so as to expose at least a part of a side surface of the first wiring.

In one aspect of the present invention, the first wiring and the second wiring are made of different materials.

The method of manufacturing a wiring connection structure for a semiconductor integrated circuit device according to the present invention includes a step of forming a first wiring in a predetermined pattern on a base insulating film, and an interlayer on the entire surface including the first wiring. Forming an insulating film; forming an opening in the interlayer insulating film, the opening having an opening larger than the width of the pattern of the first wiring at a predetermined position on the first wiring; Forming a conductive film on the entire surface including the portion,
And selectively removing the conductive film to form a second wiring having a pattern connected to the first wiring through the opening.

[0015]

In the present invention, the opening formed in the interlayer insulating film between the first wiring and the second wiring includes the overlapping area of the first wiring and the second wiring. Therefore, even if the wiring width of the first wiring or the second wiring becomes narrow, the first wiring and the second wiring are always formed in the overlapping area of each other. It is possible to contact the entire surface. Therefore, the contact resistance between the wirings due to the opening area of the opening does not increase. In addition, since the opening area of the opening can be made large without depending on the wiring width of the first wiring and the second wiring, disconnection in the opening can be prevented and the opening can be prevented. The strictness of the mask alignment accuracy for patterning the photoresist film and the like during formation is also relaxed.

Further, when the opening is formed in the interlayer insulating film, at least a part of the side surface of the first wiring is also exposed in the opening, whereby the first wiring and the first wiring are formed. The second wiring can be brought into contact with each other even on at least a part of the side surface of the first wiring, and as a result, the contact area between the wirings can be increased and the contact resistance between them can be reduced. .

Further, by forming the first wiring and the second wiring with different materials, for example, when the second wiring is etched for patterning inside the opening, the first wiring is formed. Can be prevented from being etched.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS.

1 and 2 show a wiring connection structure of a semiconductor integrated circuit device according to an embodiment of the present invention. 1 is a plan view, FIG. 2 (a) is a sectional view taken along the line AA of FIG. 1, and FIG. 2 (b) is a sectional view taken along the line BB of FIG.

As shown in FIG. 2, a silicon oxide film 6 having a film thickness of 5000Å is formed on a semiconductor substrate 5, and a first layer wiring 1 made of an aluminum alloy having a film thickness of 500Å is formed on the silicon oxide film 6. Has been done. This first layer wiring 1
May be composed of an aluminum alloy layer and a barrier metal layer of a refractory metal formed thereunder. In that case, the barrier metal layer can be composed of titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tungsten (W), or the like.

As shown in the figure, on the silicon oxide film 6,
An interlayer insulating film 2 having a film thickness of 9000Å is formed so as to cover the first layer wiring 1, and the first layer wiring 1 and a second layer wiring 4 described later are electrically connected to this interlayer insulating film 2. The open hole portion 3 is formed. As shown in FIG. 1, the opening 3 includes a region where the first layer wiring 1 and the second layer wiring 4 overlap each other, and surrounds the region.
It is formed with a large opening. In addition, as shown in FIG. 2, the depth of the opening 3 is 9000Å or more and 9500Å or less, so that a part of the side surface of the first layer wiring 1 is exposed in the opening 3. Has become.

Further, as shown in the drawing, a second layer wiring 4 made of tungsten and having a film thickness of 4000 Å is formed on the interlayer insulating film 2 so as to come into contact with the first layer wiring 1 through the opening 3. . The second layer wiring 4 may be made of titanium, titanium nitride or titanium tungsten. The second layer wiring 4 may be composed of an aluminum alloy layer and a barrier metal layer of a refractory metal formed thereunder, and the barrier metal layer may be titanium, titanium nitride, titanium tungsten, tungsten. Etc. can be mentioned.

In this embodiment, as shown in FIG. 2A, the first layer wiring 1 and the second layer wiring 4 are in contact with each other even on a part of the side surface of the first layer wiring 1. Therefore, the contact area between them becomes large and the contact resistance becomes small.

Next, a method of manufacturing the structure shown in FIGS. 1 and 2 will be described with reference to FIGS. In each of FIGS. 3 and 4, the division diagrams (a) and (b) correspond to the division diagrams (a) and (b) of FIG. 2, respectively.

First, as shown in FIG. 3, after the silicon oxide film 6 is formed on the semiconductor substrate 5 to a film thickness of 5000 Å,
On the silicon oxide film 6, a first layer wiring 1 made of an aluminum alloy and a barrier metal layer and having a film thickness of 500 Å is formed in a predetermined pattern. Next, an interlayer insulating film 2 having a film thickness of 900 is formed on the silicon oxide film 6 so as to cover the first layer wiring 1.
Form 0Å. After that, a photoresist film 7 is formed on the interlayer insulating film 2, and the photoresist film 7 is patterned into a predetermined shape. Then, using the patterned photoresist film 7 as a mask, the interlayer insulating film 2
Are selectively removed by wet etching with a dilute hydrofluoric acid solution and anisotropic etching such as reactive ion etching to form the opening 3.

Next, as shown in FIG. 4, after the photoresist film 7 is removed, a conductive film 4 made of tungsten is formed on the entire surface of the interlayer insulating film 2 including the openings 3 by reactive sputtering. Form to 4000Å. Then, a photoresist film 9 is formed on the conductive film 4, and the photoresist film 9 is patterned into a predetermined shape. Then, the conductive film 4 is selectively removed by reactive ion etching using the patterned photoresist film 9 as a mask, and the second layer wiring 4 having a pattern electrically connected to the first layer wiring 1 in the opening 3. To form. As the gas species in this etching step, a mixed gas of SF ₆ and Cl ₂ is used.

[0027]

According to the present invention, even if the wiring width of a semiconductor integrated circuit device becomes narrower as the wiring becomes finer, the opening area of the opening for connecting the wirings does not depend on the wiring width. Since it is possible to increase the contact resistance between wirings due to the reduction of the area of the opening, it is possible to prevent disconnection at the opening, and The mask alignment accuracy when forming the portion can be relaxed.

[Brief description of the drawings]

FIG. 1 is a plan view showing a wiring connection structure of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a wiring connection structure of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a wiring connection structure of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a wiring connection structure of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 5 is a plan view showing a wiring connection structure of a conventional semiconductor integrated circuit device.

FIG. 6 is a cross-sectional view showing a wiring connection structure of a conventional semiconductor integrated circuit device.

FIG. 7 is a cross-sectional view showing a manufacturing process of a conventional wiring connection structure of a semiconductor integrated circuit device.

FIG. 8 is a cross-sectional view showing a manufacturing process of a conventional wiring connection structure of a semiconductor integrated circuit device.

[Explanation of symbols]

 1 First Layer Wiring 2 Interlayer Insulation Film 3 Opening 4 Second Layer Wiring 5 Semiconductor Substrate 6 Silicon Oxide Film 7, 9 Photoresist Film

Claims (4)

[Claims] 1. A first wiring formed on a base insulating film, an interlayer insulating film formed on the first wiring, and a second wiring formed on the interlayer insulating film. And a wiring connection structure of a semiconductor integrated circuit device in which the first wiring and the second wiring are electrically connected to each other through an opening formed in the interlayer insulating film. A wiring connection structure for a semiconductor integrated circuit device, wherein the hole includes a region where the first wiring and the second wiring overlap with each other and is larger than the overlapping area. 2. The wiring connection structure for a semiconductor integrated circuit device according to claim 1, wherein the opening is formed so as to expose at least a part of a side surface of the first wiring. 3. The wiring connection structure for a semiconductor integrated circuit device according to claim 1, wherein the first wiring and the second wiring are made of different materials. 4. A step of forming a first wiring in a predetermined pattern on a base insulating film, a step of forming an interlayer insulating film on the entire surface including the first wiring, and a step of forming an interlayer insulating film on the first wiring. Forming an opening in the interlayer insulating film, the opening having an opening larger than the width of the first wiring pattern at a predetermined position; forming a conductive film over the entire surface including the opening; Is selectively removed to form a second wiring having a pattern connected to the first wiring through the opening, and a method for manufacturing a wiring connection structure of a semiconductor integrated circuit device.