JPH09135162A - Or logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a delay time at switching of an input signal small and constant by connecting sources of plural 1st transistors(TRs) in common and connecting drains of plural 2nd TRs in common so as to eliminate the cascade connection. SOLUTION: An input signal at an input terminal 201 is fed to gates of N- channel MOS TRs Qa1 , Qb1 and an input signal at an input terminal 202 is fed to gates of N-channel MOS TRs Qa2 , Qb2 . Drains of the 1st TRs Qa1 , Qa2 are connected respectively to a 1st power supply Vcc and sources are connected in common to an output terminal 21. Sources of the 2nd TRs Qa2 , Qb2 are connected to ground (2nd power supply) and drains are connected to a gate of a 3rd N-channel MOS TR Qc and one terminal of a load 22. The other terminal of the load 22 connects to the power supply Vcc. The source of the TR Qc connects to ground and the drain connects to the output terminal 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OR logic circuit, and more particularly to an OR logic circuit using MOS transistors.

[0002]

2. Description of the Related Art Conventionally, NOR is used when performing an OR logical operation.
It combines a logic circuit and an inverter. FIG. 6 shows a conventional 2-input OR logic circuit. In the figure, terminals 11 and 1
An input signal is supplied to each of the two. Input signals to the terminals 11 and 12 are P-channel MOS transistors Qp1 and Qp, respectively.
Two gates and N channel MOS transistors Qn
1 and Qn2 are supplied to the respective gates. P channel MO
The S transistors Qp1 and Qp2 are vertically connected, the drains of the N-channel MOS transistors Qn1 and Qn2 are commonly connected, and the drain of the transistor Qp2 is connected to the drains of the transistors Qn1 and Qn2.
The OR logic circuit 13 is configured. The output of the NOR logic circuit 13 is inverted by an inverter 14 composed of a P channel MOS transistor Qp3 and an N channel MOS transistor and output from a terminal 15.

FIG. 7 shows a conventional n-input OR logic circuit.
In the figure, n-system input terminals coming into the terminals 10 ₁ to 10 _n are P-channel MOS transistors Qp1 to Qn, respectively.
Each gate of pn and N channel MOS transistor Q
It is supplied to the respective gates of n1 to Qnn. P channel M
The OS transistors Qp1 to Qpn are vertically connected, and the drain of the transistor Qp1 is connected to the commonly connected drains of the N-channel MOS transistors Qn1 to Qnn to form an n-input NOR logic circuit 16. The output signal of the NOR logic circuit 16 is a P channel MOS transistor Qpn + 1 and an N channel MOS transistor Q.
It is inverted by the inverter 14 composed of nn + 1 and output from the terminal 15.

[0004]

In the conventional circuit, when all the input signals change from the high level to the low level,
Vertically connected P-channel MOS transistors in the NOR logic circuit are turned on in order from the power supply Vcc side, and turned on.
Since the conduction resistance of the channel MOS transistor is added to increase the load on the current path, a delay occurs until the signal supplied to the inverter 14 changes to the high level. This delay is not a serious problem when the number of input signals is small as shown in FIG. 6, but when the number of input signals is large as shown in FIG. 7, the number of vertically connected P-channel MOS transistors increases and the delay time There was a problem that became large. There is also a problem that the delay time varies depending on which terminal the input signal changing from the high level to the low level comes in.

[0005] The present invention has been made in view of the above points,
An object of the present invention is to provide an OR logic circuit in which the delay time between input and output is small and constant regardless of the increase in the number of input signals.

[0006]

According to a first aspect of the present invention, in an OR logic circuit that performs an OR logic operation on a plurality of input signals, the OR logic circuit is provided corresponding to each of the plurality of input signals, and each gate has the above-mentioned structure. A plurality of first N-channel MOS transistors to which an input signal is supplied, a drain of which is connected to a first power supply and a source of which is commonly connected to an output terminal;
The input signal is provided to each of the plurality of input signals, the input signal is supplied to each gate, the source is connected to the second power supply, the drain is commonly connected, and the first power supply is connected via the load. A plurality of connected second N-channel MOSs
A third N-channel MOS transistor having a gate connected to a commonly connected drain of the transistor and the second N-channel MOS transistor, a source connected to a second power supply, and a drain connected to the output terminal. And a transistor.

As described above, the sources of the plurality of first transistors are commonly connected and the drains of the plurality of second transistors are commonly connected to be used. Since the vertical connection is eliminated, the number of input signals increases. However, the delay time when switching the input signal is small and constant. Also, by using N-channel MOS transistors for the first, second, and third transistors, high-speed operation is possible and isolation is unnecessary.

According to a second aspect of the present invention, in the OR logic circuit according to the first aspect, the load is composed of an N channel MOS transistor. This allows all transistors to be N-channel MOS transistors,
Eliminates the need for isolation.

According to a third aspect of the present invention, in the OR logic circuit according to the first aspect, the load is composed of a resistor. As a result, the invention of claim 1 can be realized. According to a fourth aspect of the present invention, in the OR logic circuit according to the first aspect, the load is composed of a P-channel MOS transistor. As a result, the invention of claim 1 can be realized.

[0010]

FIG. 1 is a circuit diagram of an embodiment of the present invention. This circuit is a semiconductor integrated circuit. In the figure, an input signal is input to each of the input terminals 20 ₁ and 20 ₂ . The input signal of the input terminal 20 ₁ is supplied to the gates of the N-channel MOS transistors Qa ₁ and Qb _{1 respectively} ,
The input signal of ₂ is an N-channel MOS transistor Qa ₂ ,
Qb ₂ is supplied to each gate.

The drains of the first transistors Qa ₁ and Qa ₂ are connected to the first power supply Vcc, and the sources thereof are commonly connected to the output terminal 21. The sources of the second transistors Qb ₁ and Qb ₂ are grounded (second power supply), and the drains thereof are connected to the gate of the third N-channel MOS transistor Qc and one end of the load 22. The other end of the load 22 is connected to the power supply Vcc. The source of the transistor Qc is grounded, and the drain is connected to the output terminal 21.

When the input terminals 20 ₁ and 20 ₂ are at low level, the transistors Qa ₁ , Qa ₂ , Qb ₁ and Q are
b ₂ is all turned off, the power source Vcc is applied to the gate of the transistor Qc through the load 22, and the transistor Qc
c is turned on. Therefore, the output terminal 21 becomes low level.

Next, when either of the input terminals 20 ₁ and 20 ₂ becomes high level, the transistors Qa ₁ and Qb ₁ or the transistors Qa ₂ and Qb ₂ are turned on, the base of the transistor Qc is grounded, and the transistor Qc is turned off. And the output terminal 21 becomes high level when the transistor Qa ₁ or Qa ₂ is turned on. By this, the OR logical operation is performed.

FIG. 2 shows a circuit diagram of another embodiment of the present invention.
You. This circuit is a semiconductor integrated circuit. Input terminal in the figure
Child 20₁~ 20_nAn input signal comes in to each. Input terminal
20₁Input signal is an N-channel MOS transistor Qa
₁, Qb₁Input terminal 20 supplied to each gate_Two~
20_nInput signal is an N-channel MOS transistor Qa
_Two~ Qa_nEach and Qb_Two~ Qb_nSupply to each gate
Is done.

The drains of the first transistors Qa _{1 to} Qa _n are connected to the first power supply Vcc, and the sources thereof are commonly connected to the output terminal 21. The source of the s second transistor Qb ₁ ~Qb _n each is grounded, the drain of each is connected to one end of the gate and the load 22 of the third N-channel MOS transistor Qc. Load 22
The other end of is connected to the power supply Vcc. Transistor Q
The source of c is grounded, and the drain is connected to the output terminal 21.

Here, the input terminal 20₁~ 20_nIs all
Transistor Qa when the level is high ₁~ Qa_n, Qb₁
~ Qb_nAre all turned off, and the power supply Vcc passes through the load 22.
Applied to the gate of transistor Qc
Qc is turned on. Therefore, the output terminal 21
Be a bell.

Next, when any of the input terminals 20 _{1 to} 20 _n (for example, the terminal 20 ₂ ) becomes high level, the transistors Qa ₂ and Qb ₂ are turned on, the base of the transistor Qc is grounded, and the transistor Qc is turned off. , The output terminal 21 by turning on the transistor Qa ₁ or Qa _2.
Becomes high level. This is the same when the other input terminals become high level. By this, the OR logical operation is performed.

That is, the transistors Qa _{1 to} Qa _n are for making the output terminal 21 high level when the input signal becomes high level. Transistor Qb ₁ ~Q
b _n is for turning off the transistor Qc when the input signal becomes high level, and the transistor Qc is turned on when the input signal is all at low level to set the output terminal 21 to low level.

As described above, the transistors Qa _{1 to} Qa _{n are}
And Qb ₁ ~Qb _n uses all N-channel MOS transistor, the transistor Qa ₁ ~Qa _n is Qb ₁ to Q
Similar to b _n , the drains are commonly connected and there is no vertical connection. The N-channel MOS transistor operates faster than the P-channel MOS transistor because the majority carriers move faster. Also, since there is no vertical connection, the delay time does not increase even if the number of input signals increases,
It is constant.

Further, all transistors are N-channel MOS
Since it is a transistor, N-channel MO
The isolation, which was necessary when the S transistor and the P channel MOS transistor were mixed, was eliminated, and the structure was simplified.

3 to 5 are circuit diagrams showing an example of the configuration of the load 22. 3 to 5, the same parts as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 3, a resistor R is used as the load 22. The resistor R is composed of, for example, a diffusion resistor or a polysilicon resistor. Resistance R
Has one end connected to the gate of the transistor Qc and the other end connected to the power supply Vcc.

In FIG. 4, N-channel MOS transistor Qd is used as load 22. Transistor Q
In d, the drain and gate are connected to the power supply Vcc, the source is connected to the gate of the transistor Qc, and the conduction resistance thereof serves as a load. In this case, the transistor Qd is another transistor _{Qa 1 ~Qa n, Qb 1 ~Qb} n, Q
Since it has the same polarity as c, there is no need for isolation.

In FIG. 5, P-channel MOS transistor Qe is used as load 22. Transistor Q
e has a gate grounded and a source connected to the power supply Vcc,
The drain is connected to the gate of the transistor Qc, and its conduction resistance serves as a load. The transistor Qe is other when the transistor Qa ₁ ~Qa _n, Qb ₁ ~Q
Since the polarity is opposite to that of b _n and Qc, isolation is required.

[0024]

As described above, according to the first aspect of the present invention, in an OR logic circuit that performs an OR logic operation on a plurality of input signals, the OR logic circuit is provided corresponding to each of the plurality of input signals, and each gate has the above-mentioned structure. A plurality of first N-channel MOS transistors to which an input signal is supplied, a drain of which is connected to a first power supply and a source of which is commonly connected to an output terminal;
The input signal is provided to each of the plurality of input signals, the input signal is supplied to each gate, the source is connected to the second power supply, the drain is commonly connected, and the first power supply is connected via the load. A plurality of connected second N-channel MOSs
A third N-channel MOS transistor having a gate connected to a commonly connected drain of the transistor and the second N-channel MOS transistor, a source connected to a second power supply, and a drain connected to the output terminal. And a transistor.

Since the sources of the plurality of first transistors are commonly connected and the drains of the plurality of second transistors are commonly used in this way, and the vertical connection is eliminated, the number of input signals increases. However, the delay time when switching the input signal is small and constant. Also, by using N-channel MOS transistors for the first, second, and third transistors, high-speed operation is possible and isolation is unnecessary.

The invention described in claim 2 is the first invention.
In the OR logic circuit described, the load is an N channel M
It is composed of an OS transistor. As a result, all the transistors can be N-channel MOS transistors, and isolation is unnecessary.

[0027] The invention described in claim 3 is the same as in claim 1.
In the described OR logic circuit, the load is composed of a resistor. As a result, the invention of claim 1 can be realized. Also,
According to a fourth aspect of the present invention, in the OR logic circuit according to the first aspect, the load is composed of a P-channel MOS transistor. As a result, the invention of claim 1 can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of the present invention.

FIG. 2 is a circuit diagram of the present invention.

FIG. 3 is a circuit diagram of the present invention.

FIG. 4 is a circuit diagram of the present invention.

FIG. 5 is a circuit diagram of the present invention.

FIG. 6 is a circuit diagram of a conventional circuit.

FIG. 7 is a circuit diagram of a conventional circuit.

[Explanation of symbols]

20 ₁ to 20 _n input terminals 21 output terminal 22 load _{Qa 1 ~Qa n, Qb 1 ~Qb} n, Qc, Qd N -channel MOS transistor Qe P-channel MOS transistor R resistor

Claims (4)

[Claims] 1. An O that performs an OR logical operation on a plurality of input signals.
In the R logic circuit, a plurality of R logic circuits are provided corresponding to each of the plurality of input signals, each of the gates is supplied with the input signal, the drain is connected to the first power supply, and the sources are commonly connected to the output terminal. Of the first N-channel MOS transistor and the plurality of input signals, the respective gates are supplied with the input signal, the source is connected to the second power supply, and the drains are commonly connected. A plurality of second N-channel MOSs connected to the first power source through the load
A transistor, a gate connected to a commonly connected drain of the second N-channel MOS transistor and a source connected to the second
And a third N-channel MOS transistor having a drain connected to the output terminal of the OR logic circuit. 2. The OR logic circuit according to claim 1, wherein the load is composed of an N-channel MOS transistor. 3. The OR circuit according to claim 1, wherein the load is composed of a resistor. 4. The OR logic circuit according to claim 1, wherein the load is a P-channel MOS transistor.