JPH09116434A - Digital/analog conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily recognize the change of analog conversion voltage by means of a change in the low-order bit of a digital signal input by providing a test control circuit which compulsorily sets voltage larger than voltage between the both ends of the resistance elements at regular time. SOLUTION: This D/A conversion circuit consists of a first resistance string connecting in series equal resistance R1 -R16 , second resistance strings connecting plural resistance R in series and a selection circuit 3. The sixteen second resistance strings are connected in parallel to the respective resistance elements R1 -R16 of the first resistance string 1. The selection circuit 3 selectively takes out the voltage of a node from the connection nodes of the respective resistance elements in accordance with the content of the digital signal input. Furthermore, the test control circuit 10 which can compulsorily set test voltage higher than that at the time of a regular operation on the both ends of the second resistance string becoming a test object is provided. Thus, the test precision of the DA conversion circuit can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog (DA) conversion circuit formed in a semiconductor integrated circuit, and more particularly to a DA conversion circuit equipped with a test control circuit for improving the accuracy of a performance test. And, for example, C
It is used for a one-chip microcomputer / controller (hereinafter referred to as a microcomputer) having a MOS structure.

[0002]

2. Description of the Related Art Generally, in order to convert various digital signals inside a microcomputer and then convert them into analog quantities, D
An A conversion circuit is used. The DA conversion circuit built in the microcomputer mainly includes a string resistance method and an R-2R ladder resistance method.

Since the string resistance DA converter circuit selectively takes out a voltage divided into a plurality of pieces by the resistance string, it has high accuracy and is excellent in monotonic increase. R
The -2R ladder resistance type DA converter circuit has a small pattern area when the bit number n of the digital code input is small, but when the bit number n is large, it is difficult to use from the viewpoint of monotonic increase or the pattern area. Is.

The DA conversion circuit incorporated in the microcomputer is required to have a high conversion accuracy, a small pattern area (low cost), noise intensity, etc., and recently, for a DA conversion of a multi-bit configuration having a large number of conversion bits. Strong demand.

FIG. 8 shows an example of an 8-bit string resistance type DA conversion circuit for DA converting 8-bit digital signal inputs B0 to B7. In FIG. 8, between the first voltage node (VDD node) to which the reference voltage (for example, power supply voltage VDD) is applied and the second voltage node (VSS node) to which the ground voltage VSS is applied, 16 (= 2 ⁴ ) first resistance elements R1 to R1 having the same resistance value
A first resistor string 1 in which 6 are connected in series is formed.

The resistance elements R1 to R16 are connected in parallel and have the same resistance value.
1 = (2 ⁴ ) second resistance elements R connected in series
Six second resistor strings 2 are formed.

In the above structure, the voltage between VSS and VDD is VDD / 16 (= 2) at the series connection points (15 voltage division points) of the resistance elements R1 to R16 of the first resistance string 1.
⁴ ) Division voltage is generated which is gradually increased at fixed intervals divided by 15 units.

Then, in each second resistor string 2,
The corresponding resistance elements R1 to R16 connected in parallel respectively.
The voltage between both ends of the resistance element R is divided into 15 by 16 resistance elements R, and the division voltage that increases sequentially at a constant interval is applied to each resistance element R.
Occurs at the series connection point (15 voltage division points) of.

Further, a selection circuit for selectively taking out the voltage at one end on the VSS node side of each of the resistance elements R of the 16 second resistance strings 2 in accordance with the contents of 8-bit digital signal inputs B0 to B7. 3 is provided.

In this case, the decoded output corresponding to the upper 4 bits of the digital signal inputs B0 to B7 is a specific one first resistance of the resistance elements R1 to R16 in the first resistance string 1. Used to selectively specify the voltage across the device.

The decode output corresponding to the lower 4 bits of the digital signal inputs B0 to B7 is connected across both ends of a specific one first resistance element selected and designated by the upper 4 bits. It is used for selectively designating the VSS node side voltage of a specific one second resistance element of the resistance elements R in the specific one second resistance string 2.

As a result, the digital signal inputs B0 to B7 are input.
Depending on the minimum value (0) to the maximum value (255) of
Digital signal input B0 ~ within the range of DD × 255/256
A voltage that sequentially increases in units of a step width (VDD / 256) corresponding to 1 LSB (minimum weight bit) of B7 is selectively selected and output.

However, the conventional DA conversion circuit described above is
When testing performance such as resolution, absolute accuracy, and monotonicity, the step width of 1LSB is quite small (for example, VDD =
In the case of 4.0 V, the step width = 15.625 mV), so that the change in the analog signal output due to the change in the lower bit of the digital signal input is small.

As a result, the analog signal output is affected by the power supply noise, making accurate measurement difficult or exceeding the accuracy limit of the measuring instrument, which lowers the accuracy of the performance test and makes the test impossible. (In fact, the production test may omit the performance test for the lower bits of the digital signal input). Furthermore, in recent years, DA
The number of bits of the conversion circuit tends to increase, and it is more difficult to guarantee the accuracy of the performance test accordingly.

[0015]

As described above, the conventional DA converter circuit has a problem that the test accuracy is lowered when the lower bit of the digital signal input is changed in the performance test. The present invention has been made to solve the above problems, and it becomes possible to confirm accurately and easily the change in the analog conversion voltage corresponding to the change in the lower bit of the digital signal input during the performance test. It is an object of the present invention to provide a digital-analog conversion circuit that can improve accuracy.

[0016]

In the digital-analog conversion circuit of the present invention, a plurality of first resistance elements having the same resistance value are connected in series between a reference voltage node and a ground voltage node. A first resistor string and the first resistor string
A plurality of second resistance strings connected in parallel corresponding to the respective resistance elements of the resistance string and having a plurality of second resistance elements having the same resistance value connected in series, and the reference voltage. A digital signal input from the voltage of the node, the voltage of the series connection node of the resistance elements of the first resistance string, the voltage of the series connection node of the resistance elements of the second resistance string, and the voltage of the ground voltage node. And a selection circuit which selectively takes out according to the contents of the above, and a voltage between both ends of an arbitrary number of first resistance elements to be tested in the first resistance string in the test mode, And a test control circuit for forcibly setting a voltage higher than the voltage across the first resistance element.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an example of an 8-bit string resistance type DA conversion circuit according to a first embodiment of the DA conversion circuit of the present invention.

In the DA conversion circuit shown in FIG. 1, a first voltage node (VDD node) to which a reference voltage (for example, power supply voltage VDD) is applied and a second voltage node (VSS node) to which the ground voltage VSS is applied. 16 (= 2 ⁴ ) first resistance elements R1 to R16 having the same resistance value between
Forming a first resistor string 1 in which are connected in series.

The resistance elements R1 to R16 are connected in parallel and have the same resistance value.
1 = (2 ⁴ ) second resistance elements R connected in series
Six second resistor strings 2 are formed.

In the above structure, the voltage between VSS and VDD is VDD / 16 (= 2) at the series connection points (15 voltage division points) of the resistance elements R1 to R16 of the first resistance string 1.
⁴ ) Division voltage is generated which is gradually increased at fixed intervals divided by 15 units.

Then, in each second resistor string 2,
The corresponding resistance elements R1 to R16 connected in parallel respectively.
The voltage between both ends of the resistance element R is divided into 15 by 16 resistance elements R, and the division voltage that increases sequentially at a constant interval is applied to each resistance element R.
Occurs at the series connection point (15 voltage division points) of.

Further, an 8-bit digital signal input B0
To B7, the voltage of the VDD node, the voltage of the series connection node of the resistance elements R1 to R16 of the first resistance string 1, and the 16 second resistance strings 2
Of the series connection node of the resistance elements R of the
A selection circuit 3 is provided which selectively takes out the voltage of the node.

In this example, the selection circuit 3 is configured to selectively take out from the voltages at the one ends on the VSS node side of the respective resistance elements R of the 16 second resistance strings 2. . That is, the 16 second resistor strings 2
Selectively take out the voltage (VSS or the voltage at 255 voltage division points) at one end of each resistance element R on the VSS node side 2
A switch circuit 4 composed of 56 (= 2 ⁸ ) switch elements, and a decoder circuit for decoding the digital signal inputs B0 to B7 and selectively turning on the 256 switch elements in accordance with the decoded output. 5 and.

In this case, the decoded output corresponding to the upper 4 bits of the digital signal inputs B0 to B7 is the specific one first resistance of the resistance elements R1 to R16 in the first resistance string 1. Used to selectively specify the voltage across the device.

The decode output corresponding to the lower 4 bits of the digital signal inputs B0 to B7 is connected between both ends of a specific one first resistance element selected and designated by the upper 4 bits. It is used for selectively designating the VSS node side voltage of a specific one second resistance element of the resistance elements R in the specific one second resistance string 2.

As a result, during normal operation, the digital signal inputs B0 to B7 within the range of VSS to VDD × 255/256 according to the minimum value (0) to the maximum value (255) of the digital signal inputs B0 to B7. A voltage that sequentially increases in units of a step width (VDD / 256) corresponding to 1 LSB is selectively selected and output.

Further, a test control circuit 10 is provided to perform a performance test of the DA conversion circuit. When the test control circuit 10 is in the test mode,
The voltage across the arbitrary number of first resistance elements to be tested in the resistance string 1 is forcibly set to a voltage higher than the voltage across the arbitrary number of first resistance elements during normal operation. Is configured to.

In this example, the test control circuit 10 includes 16 first resistance elements R1 to R1 of the first resistance string 1.
16 test voltage applying circuits 20 each having a pair of output terminals connected to both ends of R16;
A control signal Ci for controlling the output operation of the six test voltage applying circuits 20 according to the test mode / normal operation.
Test voltage application control circuit 30 for supplying (i = 1 to 16)
And

The 16 test voltage application circuits 20 are
In the normal operation, the output terminal pair is controlled to be open, and in the test mode, the first resistor string 1
A specific pair of output terminals 21 connected across both ends of a specific one first resistance element to be tested,
22 outputs a voltage (VDD in this example) larger than the voltage (VDD / 16) generated during the normal operation between both ends of the first resistance element.

FIG. 2 shows a test voltage applying circuit 20 shown in FIG.
One example of each of the above is shown. In the test voltage applying circuit 20 shown in FIG. 2, the VDD node and the first output terminal 21
Is connected between the source and drain of the PMOS transistor TP, and the drain and source of the NMOS transistor TN is connected between the second output terminal 22 and the VSS node. The control input node 23
The control signal Ci (i = 1 to 16) input to
The signal is directly input to the gate of the PMOS transistor TP, inverted by the inverter circuit 24, and input to the gate of the NMOS transistor TN.

Now, the operation of the test voltage applying circuit 20 will be described. When the control signal input Ci is at "H" level, the PMOS transistor TP and the NMOS transistor TN are turned off, and the pair of output terminals 2
1, 22 are open.

On the other hand, the control signal input Ci is "L".
In case of level, PMOS transistors TP, NMO
The S transistor TN is turned on, and the VDD voltage is output between the pair of output terminals 21 and 22.

FIG. 3 shows an example of the test voltage application control circuit 30 in FIG. 1, and its truth table is shown in FIG. The test voltage application control circuit 30 shown in FIG. 3 has a 5-bit control code signal A input from the outside through, for example, five control input terminals (pads) 31 on the IC chip.
A decoder circuit is used which decodes B, C, D and G and obtains decode outputs C1 to C16 as shown in the truth table of FIG.

The decoder circuit includes an appropriate number of inverter circuits 32 for generating inverted signals of control code signal inputs A, B, C, D and G and in-phase signals, and 16 four-input NOR gates 33. 16 dual-input NAND gates 34
It is composed of

Here, the test voltage application control circuit 30
Will be described. During normal operation, control code signal G
Is at "L" level, and the decode outputs C1 to C16 all become "H". As a result, each output terminal pair of the 16 test voltage applying circuits 20 is opened.

In the test mode, the control code signal G is at "H" level, and the decode outputs C1 to C16 are output according to the contents of the remaining 4-bit control code signals A, B, C and D.
Becomes "L" as an alternative. As a result, the VDD voltage is output from the pair of output terminals of one specific test voltage applying circuit of the 16 test voltage applying circuits 20, and the output terminals of the remaining 15 test voltage applying circuits are respectively output. It becomes open.

That is, D according to the first embodiment described above.
In the A conversion circuit, in the normal operation, the voltage between the VDD node and the VSS node is applied across the first resistor string 1 in accordance with the contents of the digital signal inputs B0 to B7. It is possible to selectively take out the voltage at one end on the VSS node side of the 256 second resistance elements R in the second resistance strings 2.

Further, in the test mode, a specific one first resistor to be tested in the first resistor string 1 is used.
Of the resistance element (for example, R1) of the first resistance element R1 during the normal operation.
In a state in which the voltage is forcibly set to a voltage higher than DD / 16) (eg, VDD), the specific one first resistance element (eg, the first resistance element (eg, VDD) is selected according to the contents of the lower 4 bits of the digital signal inputs B0 to B7. It is possible to selectively take out the voltage at one end on the VSS node side of the 16 second resistance elements R in the one second resistance string 2 connected between both ends of R1).

Therefore, in the test mode, the apparent step width of 1 LSB is changed from the 1 LSB step width in the normal operation (when VDD = 4.0 V, VDD / 256 = 15.6).
It can be expanded to 16 times (VDD / 16 = 250 mV) than 25 mV.

As described above, since it is possible to temporarily expand the change in the analog conversion voltage corresponding to the change in the lower bits of the digital signal inputs B0 to B7, the measuring instrument or the LSI can be used.
It is possible to accurately and easily confirm the change in the analog conversion voltage corresponding to the change in the lower bits without being affected by power supply noise, etc., within the range of the accuracy of the tester, and to test the performance of the DA conversion circuit. The accuracy of is improved.

The selection circuit 3 is not limited to the first embodiment, and various modifications can be made. In addition, the test control circuit 10 includes the first
However, the present invention is not limited to the above embodiment, and various modifications can be made. For example, by supplying the boosted output of the existing power supply booster circuit on the same chip as the operating power supply of the test voltage application circuit 20, the boosted output can be applied across the specific first resistance element in the test mode. It will be possible.

FIG. 5 shows a modification of the test control circuit 10 shown in FIG. Test control circuit 10a shown in FIG.
1 is different from the test control circuit 10 in FIG. 1 in the connection position of the test voltage application circuit 20 and the test voltage application control circuit 30a, and the other parts are the same, and are therefore denoted by the same reference numerals as in FIG.

The test voltage application circuit 20 includes, for example, four first resistance elements (R) connected in series among the sixteen first resistance elements R1 to R16 of the first resistance string 1.
1 to R4), (R5 to R8), (R9 to R12), (R13
To R16), a pair of output terminals corresponding to both ends of the resistance element group are connected, and the output terminal pair is controlled to an open state during normal operation. For example, four pieces are output from a specific pair of output terminals connected between both ends of the resistance element group to be tested, between the both ends of the resistance element group so as to output a voltage larger than the voltage generated in the normal operation. It is provided.

Further, the test voltage application control circuit 30a
Is configured as shown in FIGS. 6A and 6B so as to supply a control signal for controlling the output operation of the four test voltage applying circuits 20 according to the test mode / normal operation. Has been done.

FIG. 6A shows an example of the test voltage application control circuit 30a in FIG. 5, and the truth table thereof is shown in FIG.
This is shown in FIG. The test voltage application control circuit 30a shown in FIG. 6A decodes, for example, 3-bit control code signals A, B, G input from the outside via three control input terminals (pads) 31 on the IC chip. Then, Fig. 6
Decode outputs C1 to C4 as shown in the truth table of (b)
A decoder circuit for obtaining

The decoder circuit is an inverter circuit 32 for generating an inverted signal of the control code signal inputs A and B.
And four three-input NAND gates 35. The test voltage application control circuit 30 shown in FIG. 3 and the test voltage application control circuit 30a shown in FIG.
For example, when the test mode is specified by the test mode control bit signal G input from one control input terminal (pad), the decode output (as shown in the truth table of FIG. 4 or FIG. 6B) C1 to C16) or (C1
It is possible to omit the input of the control code signals (A, B, C, D) or (A, B) by changing the circuit configuration so as to automatically generate .about.C4) by scanning.
This reduces the number of control input terminals (pads),
It is possible to effectively use the control input terminal in a method other than the test mode, which is suitable for the original purpose of the LSI.

The present invention is not limited to the string resistance DA converter circuit according to the first embodiment, but can be applied to the string resistance DA converter circuit as shown in FIG. .

FIG. 7 shows an example of a string resistance type DA converter circuit according to a second embodiment of the DA converter circuit of the present invention. In FIG. 7, the resistor string 61 has the same resistance value between the VDD node and the VSS node.
Fifty-six resistance elements r are connected in series.

The series connection points (255 voltage division points) of the resistance elements r of the resistance string 61 are connected to VSS to VDD.
The divided voltage is generated at a constant interval in which the inter-voltage is divided into 255 by VDD / 256 unit.

The selection circuit 62 uses the digital signal inputs B0 ...
According to the content of B7, the voltage is selectively taken out from the voltage of the VDD node, the voltage of the series connection node of the resistance elements r and the voltage of the VSS node. In this example, the voltage at each one end of the resistance element r of the resistor string 61 on the VSS node side is selectively taken out, and one end is connected to each one end of the resistance element r. A switch circuit composed of 256 switch elements each having the other end commonly connected to a voltage output end, and digital signal inputs B0 to B
7 and a decoder circuit for selectively controlling the 256 switch elements to be in the ON state according to the decoded output.

Further, among the resistance elements r, an arbitrary number (16 in this example) of first resistance elements connected in series is used as a unit, and a voltage between both ends of each resistance element r is defined as a voltage between both ends generated during normal operation. A test control circuit 63 for forcibly setting a voltage higher than that in the test mode is provided.

Also in the string resistance DA converter circuit according to the second embodiment, the same effect can be obtained by the same operation as that of the string resistance DA converter circuit according to the first embodiment.

[0053]

As described above, according to the DA conversion circuit of the present invention, it is possible to temporarily expand the change in the analog conversion voltage corresponding to the change in the lower bit of the digital signal input during the performance test. It becomes possible to confirm the change of the analog conversion voltage corresponding to the change of the lower bit accurately and easily without being affected by the power supply noise, etc. within the range of the accuracy of the measuring instrument or the LSI tester. The accuracy of the performance test of the DA conversion circuit can be improved. Considering that the number of bits of the DA conversion circuit tends to increase more and more in the future, such an effect is sure to be extremely effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of an 8-bit string resistance DA conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a test voltage application circuit in the test control circuit in FIG.

3 is a circuit diagram showing an example of a test voltage application control circuit in the test control circuit in FIG.

FIG. 4 is a diagram showing an example of a truth table of a test voltage application control circuit in the test control circuit in FIG.

5 is a circuit diagram showing a modified example of the test control circuit in FIG.

6 is a circuit diagram showing an example of a test voltage application control circuit in FIG. 5 and a diagram showing an example of a truth table.

FIG. 7 is a circuit diagram showing an example of a string resistance DA conversion circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example of a conventional string resistance DA conversion circuit for 8 bits.

[Explanation of symbols]

 R1 to R16, R ... Resistance element, 1 ... First resistance string, 2 ... Second resistance string, 3 ... Selection circuit, 4 ... Switch circuit, 5 ... Decoder circuit, 10, 10a ... Test control circuit, 20 ... Test voltage application circuit, 21 ... First output terminal, 22 ... Second output terminal, 23 ... Control input node, 24 ... Inverter circuit, 30, 30a ... Test voltage application control circuit.

Claims (4)

[Claims] 1. A first resistance string in which a plurality of first resistance elements having the same resistance value are connected in series between a reference voltage node and a ground voltage node, and a first resistance string of the first resistance string. A plurality of second resistance strings, each of which is connected in parallel to each resistance element and has a plurality of second resistance elements having the same resistance value, connected in series, and a second resistance string depending on the content of the digital signal input. Of the voltage of the reference voltage node, the voltage of the series connection node of the resistance elements of the first resistance string, the voltage of the series connection node of the resistance elements of the second resistance string, and the voltage of the ground voltage node. A selection circuit that selectively takes out of the above, and a voltage between both ends of an arbitrary number of first resistance elements to be tested in the first resistance string in the test mode, A digital-analog conversion circuit, comprising: a test control circuit for forcibly setting a voltage higher than a voltage between both ends generated in an arbitrary number of first resistance elements. 2. The digital-analog conversion circuit according to claim 1, wherein the test control circuit includes a pair of first resistance elements corresponding to a pair of first resistance elements of the first resistance string. An output terminal is connected, the output terminal is controlled to an open state during normal operation, and is connected between both ends of a specific one first resistance element to be tested of the first resistance string in the test mode. A plurality of test voltage applying circuits for outputting a voltage larger than a voltage generated during normal operation between the both ends of the first resistance element from a specified pair of output terminals, and the plurality of test voltage applying circuits. And a test voltage application control circuit for supplying a control signal for controlling the output operation of the circuit according to the test mode / normal operation. 3. The digital-analog conversion circuit according to claim 1, wherein the test control circuit includes an arbitrary number of first resistance elements connected in series among a plurality of first resistance elements of the first resistance string. A pair of output terminals corresponding to both ends of the resistance element group with the resistance element as a unit are connected, the output terminals are controlled to be in an open state during normal operation, and in the test mode, among the resistance element groups. Application of a plurality of test voltages from a specific pair of output terminals connected between both ends of the resistance element group to be tested, between the both ends of the resistance element group, a voltage larger than the voltage generated during normal operation is output. And a test voltage application control circuit that supplies a control signal for controlling the output operation of the plurality of test voltage application circuits according to the test mode / normal operation. Digital-analog converter circuit. 4. A resistance string in which a plurality of resistance elements having the same resistance value are connected in series between a reference voltage node and a ground voltage node, and the reference voltage node according to the content of a digital signal input. , A selection circuit that selectively takes out of the voltage of the series connection node of each resistance element and the voltage of the ground voltage node, and at least one of the resistance elements connected in series for converting lower bits. Digital-analog conversion, comprising: a test control circuit for forcibly setting the voltage across the first resistance elements of the number of the first resistance elements to a voltage higher than the voltage across the terminals generated during normal operation in the test mode. circuit.