JPH0898395A - Circuit breaker with open-phase protecting function - Google Patents

Abstract

PURPOSE: To provide a circuit breaker with open-phase protecting function against which plurality of delay time can be set in a detecting stage and operating time of which can be easily set. CONSTITUTION: An open-phase detecting circuit section A is provided with first and second detection circuits I and II and, when a load voltage exceeds reference voltages Vs1 and Vs2 which are respectively set to the circuit I and II, the charging of the capacitors C3 and C4 of delay circuits 4a and 4b is started. Therefore, two detecting stages are provided and the delay circuit 4b which corresponds to the second detection circuit II set to the higher reference voltage is made to reach the corresponding threshold level Vth4 in a shorter time than the other delay circuit 4a by making the magnitudes of the charging currents to or capacitances of the capacitors C3 and C4 of the circuits 4a and 4b different from each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit breaker with an open phase protection function, which shuts off an electric circuit when an open phase of a single-phase 3-wire power supply phase is detected.

[0002]

2. Description of the Related Art Conventionally, in this type of circuit breaker with an open phase protection function, the load voltage between the neutral line on the load side and each phase,
When the load voltage exceeds the reference voltage by comparing with the reference voltage, the main contact inserted in the circuit is opened to shut off the power to protect the load. However, for example, the rated voltage of 15
When 0% voltage and 200% voltage are applied, they are cut off at the same time, and the load is the one that the microcomputer is equipped with and the overvoltage withstand voltage is lowered like the recent home appliances. However, there was a problem that the load could not be sufficiently protected.

Therefore, the present applicant has filed Japanese Patent Application Laid-Open No. 5-2906.
No. 85 is proposed. This one compares the load voltage between the load side neutral line and each phase with the reference voltage, and when the load voltage exceeds the reference voltage, the capacitor is charged with a constant current and the voltage of the capacitor reaches a certain level or more. The output of the open phase detection signal is delayed until then.

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the conventional example shown in No. 0685, the delay time corresponding to the value of the voltage applied to the load at the time of phase loss is secured to improve the protection performance, but it is difficult to set the operation time. The present invention has been made in view of the above problems, and an object of the present invention is to provide a circuit breaker with an open phase protection function, which has a plurality of detection stages and can set a delay time at each detection stage. To provide.

An object of the invention of claim 2 is to provide a circuit breaker with an open-phase protection function, which is more reliable than the object of the invention of claim 1 and has more reliable load protection. The object of the invention of claim 3 is to provide a circuit breaker with an open phase protection function in which the number of parts is reduced in addition to the object of the invention of claim 1 or claim 2. The object of the invention of claim 4 is, in addition to the object of the invention of claim 3, is that a missing phase can be detected immediately after the open phase is shut off and the load can be protected when the power is turned on again. It is to provide a circuit breaker with a phase protection function.

[0006]

In order to achieve the above object, the invention of claim 1 compares the load voltage between the neutral wire on the load side and each phase with the reference voltage, and the load voltage is the reference. When the voltage exceeds the voltage, the detection circuit detects the open phase, and when this detection circuit detects the open phase, the capacitor is charged with a constant current from the detection circuit and the output of the open phase detection signal is delayed until the voltage of the capacitor reaches a certain level or higher. And a switch circuit that is turned on by a phase loss detection signal output from the phase loss detection means, and a trip coil of a main contact excited by the switch means. , In the circuit breaker with open-phase protection function that opens the main contact inserted in the circuit by the excitation of the trip coil, the open-phase detection means have different reference voltages, and are broken when the load voltage exceeds the reference voltage. Detect phase That those having at least two detection circuits.

According to a second aspect of the present invention, in the first aspect of the present invention, when a load voltage higher than a reference voltage is detected in at least one of the detection circuits, a load is applied to the capacitor together with a constant current from the detection circuit. It is provided with a charge control means for supplying a current according to the voltage. According to the invention of claim 3, the delay circuit is common to each detection circuit, and when each detection circuit detects a phase loss, a common capacitor is charged with a constant current corresponding to each.

According to the present invention, the reference voltage of the detection circuit having the higher reference voltage rises at a constant rate from when the power is turned on until it reaches the steady value, and the reference voltage of the other detection circuit becomes steady. It is slower than the time to reach the value.

[0009]

According to the invention of claim 1, the open-phase detecting means has at least two detection circuits each having a different reference voltage and detecting the open-phase when the load voltage exceeds the reference voltage. It is possible to have a plurality of detection stages, and it becomes possible to set a delay time at each detection stage.

According to the invention of claim 2, in the invention of claim 1 or 2, when a load voltage of a predetermined voltage or more is detected in at least one of the detection circuits, a constant voltage from the delay circuit is detected. Since the device is provided with a charging control means for supplying a current according to the load voltage to the capacitor together with the current, the charging of the capacitor can be accelerated when the load voltage becomes equal to or higher than a predetermined voltage, and the load protection can be made more reliable. can do.

According to the third aspect of the present invention, the delay circuit charges the common capacitor with a constant current from each detection circuit when each detection circuit becomes higher than the respective reference voltage. The number of parts can be reduced. Claim 4
According to the invention of claim 3, in the invention of claim 3, the time until the reference voltage of the detection circuit having the higher reference voltage is increased from the power-on at a constant rate to reach a steady value is the reference of the other detection circuit. Since the voltage is slower than the time it takes to reach the steady value, the detection circuit with the higher reference voltage detects the open phase earlier than the timing when the other detection open circuit detects the open phase when the power is turned on in the steady state. Therefore, even if the power is turned on in the open phase state, the open phase can be detected immediately and the load can be protected immediately.
In particular, even after the interruption of the open phase, the load can be surely protected even if the cause of the open phase is not turned off and then the power is turned on again.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.
To do. (Embodiment 1) FIG. 2 shows a basic circuit configuration of the present invention.
And each single-phase three-wire electric circuit L₁, L ₂And on the neutral line N
Is the main contact S₁Are inserted respectively. Surrounded by a dashed-dotted frame
The part indicated by the broken line shows the neutral phase loss protection circuit.
Electric line L in the road₁, L₂Is full-wave rectified by diode DB
Input to the terminal of the open-phase detection circuit section A,
The detection line Ln from the neutral line N is₁, L₂Between
Connected resistance R₁, R ₂(= R₁) Connected to the dividing point
This voltage division point is the resistance R₃Through open phase detection circuit
1 is connected to the detection terminal.

As for the voltage of the detection terminal, a pulsating current voltage having a uniform amplitude appears when the power source and the load are normally connected. However, when the neutral line N is disconnected and a phase loss occurs,
The pulsating voltage becomes large and small alternately due to the voltage division ratio due to the load of the L ₁ phase and the L ₂ phase, and when the potential of this terminal exceeds a predetermined level, the open phase detection circuit section A detects the open phase and the open phase occurs. A detection signal is output from the output terminal, and the thyristor SCR that is switching means is turned on by this open-phase detection signal, and an exciting current is passed through the trip coil CL to open the main contact S ₁ to protect the load. Of. ZNR
₁ is a surge absorbing element.

Here, the open phase detection circuit portion A in this embodiment is constructed as shown in FIG. In other words, the terminal is connected to the input terminal of the constant voltage circuit 1, the terminal is connected to the ground,
The pulsating current voltage from the diode bridge DB is converted into a direct current of a constant voltage to obtain an operating power source for each circuit of the open phase detection circuit section A.

The detection terminals are connected to the non-inverting terminals of the comparators 2a and 2b, respectively, and the voltage at the detection terminals is equal to that of the comparators 2a and 2b.
Reference voltages Vs ₁ and Vs ₂ applied to the inverting terminal of 2b
Is being compared with. The comparators 2a and 2b and the waveform shaping circuits 3a and 3b constitute first and second detection circuits I and II, respectively.
When the pulsating current voltage as shown in (a) appears and becomes equal to or higher than the reference voltage Vs ₁ or Vs ₂ of the comparator 2a or 2b, the comparator 2a or 2b produces a detection output during that period.

The waveform shaping circuit 3a (or 3b) is constructed as shown in FIG. 5, and the comparator 2a (or 2b).
When the output of the capacitor becomes "H", the electric charge of the capacitor C ₁ (or C ₂ ) is discharged through the knot gate, the load voltage becomes the reference voltage Vs ₁ or Vs ₂ or less, and the comparator 2a.
When the output of (or 2b) becomes "L", the constant current source 20 charges the capacitor C ₁ (or C ₂ ) as shown in FIG. 3 (b) or (c). When this voltage exceeds the threshold level Vth ₁ (or Vth ₂ ) of the comparator 21 in the waveform shaping circuit 3a (or 3b), the comparator 21 outputs "L", and in the following case, "H".
Output is generated. Where capacitor C ₁ (or C ₂ )
Is charged at the threshold level Vth ₁ (or Vth
_{In order} to exceed ₂ ), the load voltage must be kept below the reference voltage Vs ₁ or Vs ₂ for at least 3 cycles of the frequency of the AC power supply.

The outputs of the waveform shaping circuits 3a and 3b are connected to the delay circuits 4a and 4b, respectively.
The delay circuit 4 receives the "H" output of the comparators 21a and 32b.
As shown in FIGS. 3 (d) and 3 (e), a and 4b are configured to charge the capacitors C ₃ and C ₄ respectively provided with a constant current. That delay circuit 4a (or 4b) as shown in FIG. 5 comes to output "H" of the comparator 21, is charged with a constant current by the capacitor C ₃ (or C ₄₎ a constant current source 22. The voltages of the capacitors C ₃ and C ₄ are supplied to the comparators 5a and 5b, and the threshold levels Vth ₃ and Vth
₄ is adapted to be compared, and outputs a signal "H" from the comparator 5a, 5b when the threshold level Vth _3, Vth ₄ is the voltage of the capacitor C _3, C ₄ and withstand exceeded.

The outputs of the comparators 5a and 5b are supplied to the OR gate 6.
Is input to the output circuit 7 via any of the output circuits 7.
When the outputs of the comparators 5a and 5b of “H” become “H”, open phase detection
Output the signal from the output terminal as shown in Fig. 3 (f).
It As described above, in this embodiment, the first and second detection circuits I,
II, and the reference voltage Vs set in each₁，
Vs₂Delay voltage 4a, 4b when the load voltage exceeds
Capacitor C in₃, C_FourTo start charging
And has a plurality of detection stages (2 in the embodiment), and
C of the delay circuits 4a and 4b corresponding to ₃, C_Four
The charging current or the capacity of the capacitor
Normalize, the second detection time on the side where the high reference voltage is set
The delay circuit 4b corresponding to the road has a shorter time from the start of charging.
At threshold level Vth₃To reach
It Therefore, if the load voltage is high, the open phase detection signal
Occurs, load protection can be achieved quickly, and conversely the load voltage
If it is low, it takes a long time to generate the open-phase detection signal.
In order to improve reliability by preventing transient operations, etc.
It

FIG. 4 shows the protected area in this embodiment.
Cage, X₁Is the first detection circuit I, X ₂Is the second detection circuit
The protected area of II is shown. (Embodiment 2) In the open phase detection circuit section A of Embodiment 1,
Delay circuits 4a and 4b are provided corresponding to the first and second detection circuits.
However, in this embodiment, as shown in FIG. 6, the delay circuit 4a,
4b is shared and one delay circuit 4 and comparator 5 are omitted.
The phase detection signal is delayed to reduce the number of circuit components.
It

That is, in this embodiment, the waveform shaping circuits 3a, 3
The delay circuit 4 receives the output of b to charge the capacitor C ₅ , and receives the output of the waveform shaping circuit 3a on the side of the first detection circuit I to delay the delay circuit as shown in FIG. 7 (d). 4 starts charging the capacitor C ₅ , and thereafter, when the detection level on the second detection circuit II side is exceeded, receives the output of the waveform shaping circuit 3b to increase the charging current and charges the capacitor C ₅ . In this case, the delay circuit 4 is provided with a constant current source 22 corresponding to each of the waveform shaping circuits 3a and 3b, and the currents thereof are added.

When the output of the waveform shaping circuit 3b on the second detection circuit II side is received, the charging voltage of the capacitor C ₅ rises faster, and the time until it exceeds the threshold level Vth ₅ of the comparator 5 is correspondingly increased. The time is shortened and the time until the output of the open phase detection signal from the output circuit 7 shown in FIG. The operation of the first and second detection circuits I and II is similar to that of the first embodiment. FIG. 7A shows the voltage of the detection terminal and the reference voltage Vs ₁ of the comparators 2a and 2b.
FIG. 7B and FIG. 7C show the relationship with Vs ₂ .
Similar to (b) and (c), the waveforms of the operating states of the waveform shaping circuits 3a and 3b are shown.

FIG. 8 shows the protected area in this embodiment.
Cage, X₁Is the first detection circuit I, X ₂Is the second detection circuit
The protected area of II is shown. (Third Embodiment) The open-phase detection circuit section A of this embodiment is the same as that of the first embodiment.
Based on the circuit configuration, as shown in Fig. 9, load
Voltage is reference voltage Vs₁Figure 1 performed when the above
Constant current I shown in 0 (d)₁Delay circuit 4a
Sensor C₃In addition to charging the
Flow I₂As shown in FIG.₃Flow
The voltage-current conversion circuit 8 that is charged by charging the first detection circuit I
It was attached to.

That is, in this embodiment, when a zener diode DZ having a zener voltage equal to the reference voltage Vs ₁ of the comparator 2a is connected to the input side of the voltage-current conversion circuit 8 and the load voltage exceeds the zener voltage, The current I ₂ according to the magnitude of the voltage input via the Zener diode DZ is supplied to the capacitor C ₃ of the delay circuit 4a for charging as shown in FIG. 10 (e).

Therefore, when the level of the load voltage shown in FIG. 10A becomes higher, the charging current for charging the capacitor C ₃ correspondingly increases, and the voltage of the capacitor C ₃ shown in FIG. The rising speed is shortened, and the time required to reach the threshold level Vth ₃ of the comparator 2a is shortened. That is, the delay operation time can be changed according to the load voltage.

The operation on the second detection circuit II side is in accordance with the first embodiment, and the charging voltage of the capacitor C ₄ of the delay circuit 4b shown in FIG. 10 (g) is compared with the threshold level Vth ₄ by the comparator 5b. To be done. The outputs of the comparators 5a and 5b enter the output circuit 7 through the OR gate 6, and the output circuit 7 detects the phase loss shown in FIG. 10 (h) when either of the outputs of the comparators 5a and 5b becomes "H". Output a signal.

10 (b) and 10 (c) are shown in FIG. 3 (b).
Similar to (c), the waveforms of the operating states of the waveform shaping circuits 3a and 3b are shown. FIG. 11 shows a protection region in this embodiment, where X ₁ is the first detection circuit I and X ₂ is the second detection circuit.
2 shows a protection area of the detection circuit II of FIG. (Fourth Embodiment) The open-phase detection circuit portion A of the present embodiment is obtained by adding the circuit configuration of the third embodiment to the circuit configuration of the second embodiment.
When the load voltage becomes equal to or higher than the reference voltage Vs ₁ as shown in FIG. 13, the voltage I ₂ corresponding to the magnitude of the load voltage and flowing in the capacitor C ₅ of the delay circuit 4 to charge the current I ₂ − A current conversion circuit 8 is additionally provided.

That is, in this embodiment, when a zener diode DZ having a zener voltage equal to the reference voltage Vs ₁ of the comparator 2a is connected to the input side of the voltage-current conversion circuit 8 and the load voltage exceeds the zener voltage, A current I ₂ according to the magnitude of the voltage input through the Zener diode DZ is passed through the capacitor C ₅ of the delay circuit 4 to charge it as shown in FIG. 13 (e).

Therefore, in addition to receiving the outputs of the waveform shaping circuits 3a and 3b, the capacitor C ₅ of the delay circuit 4 is charged by the constant current I ₁ shown in FIG.
Since the current I ₂ corresponding to the level of the load voltage illustrated in (a) charges the capacitor C _5, increase in the voltage of the capacitor C ₅ is faster shown in the-figures 13 (f), the threshold level of the comparator 5 The time to reach Vth ₅ is shortened. That is, the delay operation time can be changed according to the load voltage.

Since the operations of the first and second detection circuits I and II are similar to those of the first and second embodiments, the description of the configuration and operation will be omitted. 13B and 13C show the waveforms of the operation states of the waveform shaping circuits 3a and 3b, respectively, as in FIGS. 3B and 3C, and FIG. Indicates a signal.

FIG. 14 shows the protection region in this embodiment, where X ₁ is the second detection circuit I and X ₂ is the protection region of the second detection circuit II. The present embodiment configured as described above has the characteristics of the second embodiment and the characteristics of the third embodiment. (Fifth Embodiment) The voltage-current conversion circuit 8 in the third embodiment is attached to the first detection circuit I, but this embodiment is attached to the second detection circuit II as shown in FIG. Is. That is, in this embodiment, the constant current I shown in FIG. 16D, which is performed when the load voltage becomes equal to or higher than the reference voltage Vs ₂ .
_In addition to charging the capacitor C ₄ of the delay circuit 4b by ₁ ,
The current I ₂ corresponding to the magnitude of the load voltage equal to or higher than the reference voltage Vs _{2 is} supplied to the capacitor C ₄ for charging as shown in FIG. 16 (e).

That is, in the present embodiment, a zener diode DZ 'having a zener voltage equal to the reference voltage Vs ₂ of the comparator 2b is connected to the input side of the voltage-current conversion circuit 8 and the load voltage exceeds the zener voltage. The current I ₂ according to the magnitude of the voltage input through the Zener diode DZ ′ is supplied to the capacitor C ₄ of the delay circuit 4b for charging as shown in FIG. 16 (e).

Therefore, the reference voltage Vs shown in FIG.
₂ or more and the load voltage is generated increases the charging current for charging the capacitor C ₄ in accordance with the load voltage, increase in the voltage of the capacitor C ₄ shown in FIG. 16 (g) is fast, the comparator 5
The time required to reach the threshold level Vth _{4 of} b is shortened. That is, the delay operation time can be changed according to the load voltage.

The operation on the second detection circuit I side is in accordance with the first embodiment, and the charging voltage of the capacitor C ₃ of the delay circuit 4a shown in FIG. 16 (f) is compared with the threshold level Vth ₃ by the comparator 2a. To be done. The outputs of the comparators 5a and 5b enter the output circuit 7 through the OR gate 6, and the output circuit 7 detects the open phase shown in FIG. 16 (h) when either of the outputs of the comparators 5a and 5b becomes "H". Output a signal.

16 (b) and 16 (c) are shown in FIG. 3 (b).
Similar to (c), the waveforms of the operating states of the waveform shaping circuits 3a and 3b are shown. FIG. 17 shows a protection area in this embodiment, where X ₁ is the first detection circuit I and X ₂ is the second detection circuit I.
2 shows a protection area of the detection circuit II of FIG. (Embodiment 6) The open-phase detection circuit portion A of this embodiment is obtained by adding the circuit configuration of the fifth embodiment to the circuit configuration of the second embodiment.
As shown in FIG. 19, when the load voltage becomes equal to or higher than the reference voltage Vs _2, the current I ₂ corresponding to the magnitude of the load voltage is shown in FIG.
As shown in (e), a voltage-current conversion circuit 8 for charging the capacitor C ₅ of the delay circuit 4 by charging it is additionally provided.

That is, in this embodiment, when a zener diode DZ 'having a zener voltage equal to the reference voltage Vs ₂ of the comparator 2b is connected to the input side of the voltage-current conversion circuit 8 and the load voltage exceeds the zener voltage. The current I ₂ corresponding to the magnitude of the voltage input through the Zener diode DZ is supplied to the capacitor C ₅ of the delay circuit 4 to charge it as shown in FIG. 19 (e).

Accordingly, the constant current I ₁ or I ₃ shown in FIG. 19 (d) or (f) flows through the capacitor C ₅ of the delay circuit 4 in response to the outputs of the waveform shaping circuits 3a and 3b to charge it. In addition, since the current I ₂ corresponding to the load voltage equal to or higher than the reference voltage Vs ₂ shown in FIG. 19A charges the capacitor C ₅ ,
As a result, the voltage of the capacitor C ₅ shown in FIG. 19 (g) rises faster, and the threshold level Vth _{5 of the} comparator 5 is increased.
It takes less time to reach. That is, the delay operation time can be changed according to the load voltage.

Since the operations of the first and second detection circuits I and II are the same as those of the first and second embodiments, the description of the structure and operation will be omitted. 19B and 19C show the waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively, similarly to FIGS. 3B and 3C, and FIG. 19G shows the phase loss detection of the output circuit 7. Indicates a signal.

FIG. 20 shows the protection area in this embodiment, where X ₁ is the first detection circuit I and X ₂ is the second detection circuit II. The present embodiment configured as described above has the characteristics of the second embodiment and the characteristics of the fifth embodiment. (Embodiment 7) The phase loss detection circuit section A of this embodiment has the same structure as that of the embodiment 5 as shown in FIG.
A third detection circuit III composed of c, a delay circuit 4c and a comparator 5c corresponding thereto are added, and an OR gate 6 having three inputs is used.

That is, the comparator 2c of the third detection circuit III generates a detection output when a load voltage equal to or higher than the reference voltage Vs ₃ is input to the detection terminal as shown in FIG. 22 (a). The corresponding waveform shaping circuit 3c charges and discharges the capacitor C ₆ according to the detection output of the comparator 5c as shown in FIG. 22 (d), and sets the threshold level Vth ₆ to the capacitor C _6.
When the voltage of ₆ does not exceed, the output is given to the delay circuit 4c. The delay circuit 4c receives this output and charges the capacitor C ₇ with a constant current as shown in FIG. 22 (i). Comparator 5c is an OR gate the "H" signal when the voltage of the capacitor C ₇ exceeds the threshold level Vth ₇ 6
Output to.

That is, the operations of the third detection circuit III, the delay circuit 4c, and the comparator 5c are as follows.
It performs the same operation as II. When the "H" signal is output from any of the comparators 2a to 5c, the output circuit 7
Outputs an open phase detection signal as shown in FIG.
22 (b) and 22 (c) show the waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively, as in FIGS. 3 (b) and 3 (c).
22 (e) shows the constant current I ₁ flowing through the capacitor C ₄ of the delay circuit 4b corresponding to the output of the waveform shaping circuit 3b, and FIG.
22 (f) shows the current I ₂ flowing through the capacitor C ₄ by the voltage-current conversion circuit 8, and FIGS. 22 (g) and 22 (h) show the voltages of the capacitors C ₃ and C ₄ of the delay circuits 4a and 4b, respectively.

According to this embodiment, in addition to the features of the fifth embodiment, the number of detection stages is increased to three, which makes it easier to set the operating time. FIG. 23 shows a protection area in this embodiment, where X ₁ is the first detection circuit I and X ₂ is the second detection circuit I.
The detection circuits II and X ₃ of 3 indicate protection regions of the third detection circuit III. (Ninth Embodiment) The open phase detection circuit section A of this embodiment has the same structure as that of the sixth embodiment as shown in FIG.
A third detection circuit III composed of c, a delay circuit 4c and a comparator 5c corresponding thereto are added.

The operation of the third detection circuit III is the eighth embodiment.
The delay circuit 4 receives the output of the waveform shaping circuit 3c of the third detection circuit III and corresponds to the outputs of the waveform shaping circuits 3a and 3b of the first and second detection circuits I and II. In addition to the charging by the constant currents I ₁ and I ₂ shown in FIGS. 25 (e) and (f) and the charging by the current I ₃ by the voltage-current conversion circuit 8 shown in FIG. 25 (g), FIG. It was charged by constant current I ₄ shown in FIG. 25 accelerate the rise of the charging voltage of the capacitor C ₅ shown in (i), accelerating the time to exceed the threshold level Vth ₅ of comparator 5, FIG. 2
The delay time until the open phase detection signal output from the output circuit 7 shown in FIG. 5 (j) is generated is variable.

Note that FIG. 25A shows the load voltage input to the detection terminal, and FIGS. 25B and 25C show FIGS. 3B and 3C.
Similarly, the waveforms of the operating states of the waveform shaping circuits 3a and 3b are shown, and FIG. 25D shows the operating state of the waveform shaping circuit 3c. This embodiment has the characteristics of the sixth embodiment and the characteristics of the eighth embodiment. (Embodiment 10) The open phase detection circuit unit A of this embodiment is the same as that of Embodiment 1.
As shown in FIG. 26, a third detection circuit III including a comparator 2c and a waveform shaping circuit 3c, a delay circuit 4c and a comparator 5c corresponding thereto are added to the configuration of FIG. 26, and an OR gate 6 having three inputs is used. It is a thing. Since the operation of the third detection circuit III is the same as that of the eighth embodiment, its explanation is omitted.

FIG. 27 (a) shows the load voltage input to the detection terminal, and FIGS. 27 (b) and 27 (c) show the operating states of the waveform shaping circuits 3a and 3b, respectively, as in FIGS. 3 (b) and 3 (c). 29 (d) shows the waveform of the operation state of the waveform shaping circuit 3c, and FIGS. 27 (e) (f) (g) shows the delay circuit 5 respectively.
a, 5b and 5c capacitors C ₃ , C ₄ and C ₇ ,
FIG. 27H shows the open phase detection signal of the output circuit 7.

Thus, in this embodiment, the number of detection stages is three, and the protection area is as shown in FIG. X ₁ is the first
Detection circuits I and X ₂ of the second detection circuit II and X ₃ of the third detection circuit III are protection regions. (Embodiment 11) The open phase detection circuit section A of this embodiment is the same as the embodiment 2.
As shown in FIG. 29, a third detection circuit III including a comparator 2c and a waveform shaping circuit 3c, a delay circuit 4c and a comparator 5c corresponding to the third detection circuit III are added, and an OR gate 6 having three inputs is used. It is a thing. In other words, Example 10
There is one delay circuit and one comparator behind it, eliminating the need for an OR gate.

Since the operation of the third detection circuit III is the same as that of the eighth embodiment, its explanation is omitted. Therefore, in this embodiment, the number of circuit components can be reduced as compared with the tenth embodiment. FIG. 30A shows the load voltage input to the detection terminal as
30B and 30C show the waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively, similarly to FIGS. 3B and 3C, and FIG. 30D shows the operating state of the waveform shaping circuit 3c. FIG. 30 (e) shows the waveform of the capacitor C of the delay circuit 5,
FIG. 30 (f) shows the open phase detection signal of the output circuit 7.

(Embodiment 12) As shown in FIG. 31, the structure of the open-phase detection circuit section A of this embodiment is the same as that of Embodiment 2 except that the reference voltage in the steady state is the reference voltage of the comparator 2a of the detection circuit I in the steady state. Comparator 2b of the detection circuit II higher than the reference voltage Vs _{1 of}
Then, the time from when the power is turned on until the reference voltage value is raised at a constant rate to reach the reference voltage Vs ₂ in the steady state is detected by the detection circuit I.
Of the reference voltage Vs ₁ of the comparator 2a of FIG. Specifically, the voltage of the terminal, that is, the voltage of the capacitor C ₀ externally connected between both terminals as shown in FIG. 2, is divided by the resistors R ₁ and R ₂ , and the reference voltage Vs is obtained by the divided voltage. It is the one to get ₂ .

Therefore, when the main contact S ₁ is turned on and power is supplied, the reference voltage Vs ₁ of the comparator 2a of the detection circuit I immediately rises as shown in FIG.
The reference voltage Vs ₂ of the II comparator 2a rises at a constant rate as the charging voltage of the external capacitor C ₀ rises, and it takes time to reach a predetermined voltage. Therefore, when the main contact S ₁ is turned on while the phase loss occurs, the voltage at the detection terminal immediately exceeds the reference voltage Vs ₂ of the comparator 2b, and the detection output is generated from the comparator 2b. Upon receiving this detection output, the delay circuit 4 starts charging the capacitor C ₅ as shown in FIG. 32D, and then receives the output of the waveform shaping circuit 3a on the detection circuit I side to increase the charging current and than is to charge the C _5.

That is, the charging voltage of the capacitor C ₅ is the threshold level V of the comparator ₅ early after the power is turned on.
th ₅ the past becomes the this output phase loss detection signal from the output circuit 7 shown in FIG. 32 (e), the open phase immediately when the main contact point S ₁ is being turned in the open phase state The circuit is cut off upon detection, and the load can be promptly protected. Since the operation when the open phase occurs after the reference voltage Vs ₂ rises is the same as that of the second embodiment, the description thereof will be omitted.

32 (b) and (c) are shown in FIG. 7 (b).
Similar to (c), the waveforms of the operating states of the waveform shaping circuits 3a and 3b are shown. Further, FIG. 33 shows a protection region in this embodiment, where X ₁ is the protection region of the first detection circuit I, X ₂ is the protection region of the second detection circuit II, and X ₃ is the second protection region when the power is turned on. The protection area of the detection circuit II is shown.

[0051]

According to the invention of claim 1, the open-phase detecting means has at least two detection circuits each having a different reference voltage and detecting the open-phase when the load voltage exceeds the reference voltage. It is possible to have a plurality of detection stages, and it is possible to set a delay time at each detection stage.

The invention of claim 2 is claim 1 or claim 2.
In the invention described above, in at least one of the detection circuits, when a load voltage equal to or higher than a predetermined voltage is detected, a charging control means for flowing a current according to the load voltage to the capacitor together with a constant current from the delay circuit is provided. Therefore, when the load voltage becomes equal to or higher than the predetermined voltage, the capacitor can be charged faster, and the load protection can be made more reliable.

According to a third aspect of the invention, the delay circuit is common to each detection circuit, and when each detection circuit detects a phase loss, a common capacitor is charged with a constant current corresponding to each of the detection circuits. This has the effect of making it possible to reduce the number of circuit components. According to a fourth aspect of the invention, in the third aspect of the invention, the time from when the reference voltage of the detection circuit having the higher reference voltage is raised to a steady value after the power is turned on is increased at a constant rate. Since the time required for the reference voltage to reach the steady value was delayed, the open circuit detects the open phase earlier than the timing when the detection circuit with the higher reference voltage detects the open phase when the power is turned on in the steady state. Therefore, even if the power is turned on in the open phase state, the open phase can be detected immediately and the load can be protected promptly.Especially after the open phase cutoff, the cause of the open phase is removed. The effect is that load protection can be surely achieved even if the power is re-applied without being turned on.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a phase loss detection circuit unit according to a first embodiment of the present invention.

FIG. 2 is an overall circuit configuration diagram of the same as above.

FIG. 3 is a waveform diagram for explaining the operation of the above.

FIG. 4 is an explanatory diagram of a protection area of the above.

FIG. 5 is a specific circuit diagram of a main part of the above.

FIG. 6 is a circuit configuration diagram of an open phase detection circuit unit according to a second embodiment of the present invention.

FIG. 7 is a waveform diagram for explaining the same operation as above.

FIG. 8 is an explanatory diagram of a protection area of the above.

FIG. 9 is a circuit configuration diagram of an open phase detection circuit unit according to a third embodiment of the present invention.

FIG. 10 is a waveform diagram for explaining the operation of the above.

FIG. 11 is an explanatory diagram of the above protected area.

FIG. 12 is a circuit configuration diagram of an open phase detection circuit unit according to a fourth embodiment of the present invention.

FIG. 13 is a waveform diagram for explaining the operation of the above.

FIG. 14 is an explanatory diagram of a protection area of the above.

FIG. 15 is a circuit configuration diagram of an open phase detection circuit unit according to a fifth embodiment of the present invention.

FIG. 16 is a waveform diagram for explaining the operation of the above.

FIG. 17 is an explanatory diagram of the above protected area.

FIG. 18 is a circuit configuration diagram of an open phase detection circuit unit according to a sixth embodiment of the present invention.

FIG. 19 is a waveform diagram for explaining the same operation as above.

FIG. 20 is an explanatory diagram of the above protection area.

FIG. 21 is a circuit configuration diagram of an open phase detection circuit unit according to a seventh embodiment of the present invention.

FIG. 22 is a waveform diagram for explaining the operation of the above.

FIG. 23 is an explanatory diagram of the above protection area.

FIG. 24 is a circuit configuration diagram of an open phase detection circuit unit according to an eighth embodiment of the present invention.

FIG. 25 is a waveform diagram for explaining the same operation as above.

FIG. 26 is an explanatory diagram of the above protected area.

FIG. 27 is a circuit configuration diagram of an open-phase detection circuit unit according to a ninth embodiment of the present invention.

FIG. 28 is an explanatory diagram of a protection area of the above.

FIG. 29 is a circuit configuration diagram of an open phase detection circuit unit according to the tenth embodiment of the present invention.

FIG. 30 is a waveform diagram for explaining the same operation as above.

FIG. 31 is a circuit configuration diagram of an open phase detection circuit unit according to an eleventh embodiment of the present invention.

FIG. 32 is a waveform diagram for explaining the same operation as above.

FIG. 33 is an explanatory diagram of a protection area of the above.

[Explanation of symbols]

1 constant voltage circuit 2a, 2b comparator 3a, 3b waveform shaping circuit 4a, 4b delay circuit 5a, 5b comparator 6 OR gate 7 output circuit I, II detection circuit A open-phase detection circuit section C _{1 to} C ₄ capacitor Vs ₁ , Vs ₂ reference voltage Vth ₃ threshold level

Claims (4)

[Claims] 1. A detection circuit for detecting a phase loss when the load voltage between a load-side neutral wire and each phase is compared with a reference voltage and the load voltage becomes equal to or higher than the reference voltage. When the phase is detected, the capacitor is charged with a constant current and the phase loss detecting means having a delay circuit for delaying the output of the phase loss detecting signal until the voltage of the capacitor reaches a certain level or more, and the phase loss detecting means outputs the signal. Equipped with a switch means that turns on when there is an open phase detection signal, and a trip coil for the main contact that is excited by this switch means. With the open phase protection function that opens the main contact that is inserted in the electrical circuit by exciting the trip coil. In the circuit breaker, the open-phase detection means includes at least two detection circuits that have different reference voltages and detect the open-phase when the load voltage exceeds the reference voltage. Shield with function Vessel. 2. When at least one of the detection circuits detects a load voltage equal to or higher than a predetermined voltage, a charging control means for flowing a constant current from the detection circuit and a current according to the load voltage to the capacitor is provided. Circuit breaker with open-phase protection feature. 3. The delay circuit is commonly used for each detection circuit, and when each detection circuit detects a phase loss, a common capacitor is charged with a constant current corresponding to each of the detection circuits. Circuit breaker with the open-phase protection function described in 2. 4. The time required for the reference voltage of the detection circuit having the higher reference voltage to rise to a steady value after the power is turned on at a constant rate until the reference voltage of the other detection circuit reaches the steady value. The circuit breaker with the open-phase protection function according to claim 3, wherein the circuit breaker is delayed from the time.