JPH0897644A - J-fet amplifier circuit - Google Patents

Abstract

PURPOSE: To provide a low distortion J-FET common source amplifier circuit without applying NFB. CONSTITUTION: An amplification use 1st J-FET 2 connects to ground via a 1st source resistor RS1. Furthermore, a 2nd J-FET 2 as a load is connected to the J-FET 1 via a 2nd source resistor RS2 and a 2nd (1st) resistor R2 (R1) is connected between a gate G2 and a voltage source (between the gate G2 and one terminal of the RS2) respectively. Since the 2nd J-FET 2 acts like a distortion cancelling element as a load of the J-FET, a low distortion amplifier circuit is realized without NFB.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a J-FET grounded-source amplifier circuit suitable for audio amplifiers and the like, and in particular, by using a load having a distortion canceling element, a low distortion without applying NFB (negative feedback). J
-Improvement for realizing a FET amplifier circuit.

[0002]

2. Description of the Related Art Conventionally, as an amplifier circuit using a J-FET (J-type field effect transistor), as shown in FIG.
A FET source grounded amplifier circuit is commonly used. In the circuit of FIG. 3, the AC voltage gain A is
Approximately, the ratio A of the drain resistance RD and the source resistance RS
It is well known that = RD / RS.

[0003]

However, it is well known that the transfer characteristic of the J-FET has nonlinearity, and therefore the output waveform is distorted with the configuration of FIG. Conventionally, this distortion has been inevitable. In order to reduce this distortion, it has been considered preferable to apply a large amount of NFB after increasing the overall amplification factor by using the amplifier circuit of FIG. 3 in multiple stages.

However, some problems have been pointed out by applying a large amount of NFB. Instability due to oscillation and dissatisfaction in sound quality when used in an audio circuit are particularly serious problems.

In view of the above points, an object of the present invention is to realize a low-distortion J-FET source grounded amplifier circuit without applying NFB.

[0006]

To achieve the above object, a first invention is a J-FET having a first J-FET for amplification whose source is grounded via a first source resistor.
In the amplifier circuit, as a load of the first J-FET, a second J-FET having the same characteristics as the first J-FET for amplification and a second source resistance having the same value as the first source resistance.
A FET is used, and the first resistance is connected to one end of the gate and the second source resistance, and the second resistance is connected between the gate and the voltage source.

A second invention is the circuit according to the first invention, further comprising a third source resistance having the same characteristics as the first J-FET and having the same value as the first source resistance. J
-FET, the same current as the first J-FET is caused to flow through the third J-FET, and the third J-FET has a first resistor having the same value as the first resistor between the gate and the second source resistor. The third resistor is connected, and the connection point between the gate and the third resistor is connected to the output terminal.

[0008]

In the circuit of the first invention, the second J-FET is provided.
Operates as a load having a distortion canceling element of the first J-FET for amplification, so that a low distortion amplifier circuit is realized without applying NFB.

In the circuit of the second invention, the third J-
By using the FET, when the current flowing through the first resistor cannot be ignored in the circuit of the first invention, this current is canceled.

[0010]

Embodiments of the present invention shown in the drawings will be described below.
FIG. 1 shows an embodiment of a J-FET grounded source amplifier circuit according to the present invention. In the figure, the first J-FET for amplification is used.
1 is grounded via the first source resistor RS1, and the second J-FET 2 having the same characteristics is used as its load as a distortion canceling element. The second source resistance RS2 is R
The same value as S1, the gate G2 and the second source resistor RS2
A first resistor R1 is connected to one end of the first resistor R2, and a second resistor R2 is connected between its gate G and a voltage source.

In the circuit of FIG. 1, the first and second resistors R1 and R2 have a large value so that the current flowing through them can be ignored. At this time, the voltage VOUT of the output terminal
Is the voltage value VS of the voltage source minus the voltage VR1 across the first resistor R1 and the voltage VR2 across the second resistor R2.

## EQU1 ## VOUT = VS-VR2-VR1 When the second resistor R2 has a value N times that of the first resistor R1, the currents flowing through R1 and R2 can be regarded as almost the same (J- The gate current of the FET is extremely small and can be ignored),

## EQU00002 ## VOUT = VS- (N + 1) VR1.

Also, the gates of the first and second J-FETs,
The source-to-source voltages are VGS1, VGS2, first and second, respectively.
Let I be the current flowing through the source resistances RS1 and RS2 of

[Formula 3] VR1 = VGS2 + IRS2 = VGS1 + IR
Since S1 = VIN,

## EQU4 ## VOUT = VS- (N + 1) VIN, and the output voltage VOUT that is (N + 1) times the input voltage VIN is obtained at the output terminal in terms of AC. That is, the embodiment circuit of FIG. 1 can be said to be a distortion-free voltage amplifier with an amplification factor (N + 1).

FIG. 2 shows another embodiment of the present invention, in which a circuit is added to cancel the current flowing through the first resistor R1 when it cannot be ignored in the illustrated embodiment. This additional circuit consists of a third J-FET3, a third resistor R3, a third source resistor RS3 and a fourth J-FET4 and a fourth source resistor RS4.

In the circuit of FIG. 2, all J-FETs 1
~ Characteristics of J-FET4 and its source resistances RS1 to RS4
If the values of the first resistor R1 and the third resistor R3 are equal, the currents flowing through R1 and R3 are substantially equal, and the current flowing through R1 is the drain of the first J-FET1 for amplification. It does not flow into D1, so in the circuit of FIG.
The same effect can be obtained that the value of 1 is large and the current flowing through R1 can be ignored.

[0015]

As described above, according to the present invention, N
A low-distortion J-FET source grounded amplifier circuit can be obtained without applying FB.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional J-FET common-source amplifier circuit.

[Explanation of symbols]

J-FET1 to J-FET4 J-type field effect transistor RS1 to RS4 source resistance R1 to R3 first to third resistances D1 to D4 drain S1 to S4 source G1 to G4 gate

Claims (2)

[Claims] 1. A J-FET amplifier circuit comprising a first J-FET for amplification, the source of which is grounded via a first source resistor, wherein a first J-FET for amplification is used as a load of the first J-FET. A second J-F having the same characteristics as the first J-FET and a second source resistance having the same value as the first source resistance.
A J-FET amplifier circuit using ET, wherein the first resistance is connected to one end of the gate and the second source resistance, and the second resistance is connected between the gate and the voltage source. 2. A third J-FET having a second source resistance having the same characteristics as the first J-FET and having the same value as the first source resistance, the third J-FET being provided. The same current as that of the first J-FET is caused to flow in the FET, and a third resistor having the same value as that of the first resistor is provided between the gate and the second source resistor.
Of the resistor, and the connection point between the gate and the third resistor,
A J-FET amplifier circuit characterized by being connected to an output terminal.