JPH0888189A - Thin film polycrystalline semiconductor and its manufacture, and photovoltaic device and its manufacture - Google Patents

Abstract

PURPOSE: To simply obtain a thin film polycrystalline semiconductor excellent in device characteristics like carrier mobility, and a photovoltaic device excellent in conversion efficiency. CONSTITUTION: In the title thin film polycrystalline semiconductor, crystal phase 21 diffused in an amorphous semiconductor thin film 22 is subjected to solid growth and crystallized at a temperature wherein new crystal nuclei are not formed. In the title photovoltaic device, a polycrystalline semiconductor layer of one conductivity type is formed on a substrate in which layer crystal phase diffused in an amorphous semiconductor layer of one conductivity type is subjected to solid growth and polycrystallized at a temperature wherein new crystal nuclei are not formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film polycrystalline semiconductor in which a semiconductor thin film is polycrystallized, a manufacturing method thereof, a photovoltaic device using such a thin film polycrystalline semiconductor, and a manufacturing method thereof. is there.

[0002]

2. Description of the Related Art Conventionally, a thin film polycrystalline semiconductor obtained by polycrystallizing a thin film semiconductor has been widely used in a photovoltaic device and the like, and thus, in using the thin film polycrystalline semiconductor in a photovoltaic device and the like. Are required to improve the device characteristics such as carrier mobility in a thin film polycrystalline semiconductor by increasing the grain size of the crystal.

Here, in manufacturing a thin film polycrystalline semiconductor, conventionally, a solid phase growth method is generally used in which an amorphous semiconductor thin film is formed on a substrate and the amorphous semiconductor thin film is heated to crystallize. In order to manufacture a thin film polycrystalline semiconductor having a large crystal grain size by the solid phase growth method, a laser annealing method or the like in which this amorphous semiconductor thin film is irradiated with a laser to crystallize is used. By doping a part of the amorphous semiconductor thin film with impurities such as phosphorus (P) or boron (B), the charge state in the amorphous semiconductor thin film is changed, and the amorphous semiconductor thin film is selectively doped from the impurity-doped part. A method has been developed to initiate crystallization in.

However, even when a part of the amorphous semiconductor thin film is doped with impurities as described above, when the amorphous semiconductor thin film is heated and crystallized, various types of amorphous semiconductor thin films can be obtained. Crystal nuclei are generated in the portion and solid-phase grown, and as shown in FIG. 1, many crystals 2a are formed in the thin film polycrystalline semiconductor 2 on the substrate 1, and the grain size of each formed crystal 2 is It is still not sufficient, and there is a problem that the crystal grain boundaries 2b are formed in the thickness direction of the thin film polycrystalline semiconductor 2 and the device characteristics such as carrier mobility and conversion efficiency cannot be sufficiently improved. there were.

Further, since device characteristics such as carrier mobility and conversion efficiency cannot be sufficiently improved as described above, when a photovoltaic device is manufactured by using such a thin film polycrystalline semiconductor, this photovoltaic device is produced. The characteristics of the power device are not sufficiently improved, and there is a problem that a photovoltaic device with high conversion efficiency cannot be obtained.

[0006]

SUMMARY OF THE INVENTION Therefore, the applicant of the present invention, in Japanese Patent Application No. 5-153692, which is a prior application, heat-treats an amorphous silicon thin film doped with impurities and having a crystal phase dispersed therein, It has been disclosed that when solid phase growth of this amorphous silicon thin film is performed, thin film polycrystalline silicon in which large crystals without crystal grain boundaries are formed in the thickness direction is obtained.

However, even in this case,
When heat-treating an amorphous silicon thin film for solid phase growth,
New crystal nuclei are formed in the amorphous silicon thin film, and these are solid-phase grown to form crystals with a small grain size in the thin film polycrystalline silicon, or the amorphous silicon thin film is doped with impurities. In this case, the doped impurities may move during solid phase growth, and the characteristics of the formed thin film polycrystalline silicon may deteriorate.

An object of the present invention is to solve various problems as described above in a thin film polycrystalline semiconductor obtained by crystallizing an amorphous semiconductor thin film and a photovoltaic device using this thin film polycrystalline semiconductor. It is a thing.

That is, according to the present invention, in a thin film polycrystalline semiconductor obtained by crystallizing a semiconductor thin film, a crystal having a small grain size is not formed, and a large crystal having no grain boundary in the thickness direction is formed. Therefore, it is possible to easily obtain a thin film polycrystalline semiconductor excellent in device characteristics such as carrier mobility and conversion efficiency, and to easily obtain a photovoltaic device using a thin film polycrystalline semiconductor with high conversion efficiency. The task is to

[0010]

According to the present invention, in order to solve the above problems, solid phase growth is performed at a low temperature at which a crystal phase in an amorphous semiconductor thin film does not form new crystal nuclei. The thin-film polycrystalline semiconductor in which the above amorphous semiconductor thin film is polycrystallized has been developed.

In the above thin film polycrystalline semiconductor, silicon, germanium, silicon germanium or the like is used as the semiconductor material.

Further, in the present invention, in manufacturing the above-mentioned thin film polycrystalline semiconductor, a step of forming an amorphous semiconductor thin film in which a crystal phase is dispersed on a substrate, and the amorphous semiconductor thin film A step of performing a heat treatment at a low temperature at which new crystal nuclei are not formed and solid-phase growing the crystal phase is performed.

In the photovoltaic device according to the present invention, in order to solve the above problems, the crystal phase in the one-conductivity-type amorphous semiconductor layer is solidified at a low temperature at which new crystal nuclei do not form. We have developed a photovoltaic device in which a polycrystalline semiconductor of one conductivity type that has been phase-grown and polycrystallized is formed on a substrate.

As such a photovoltaic device,
An amorphous semiconductor layer of one conductivity type in which a crystal phase is dispersed and an amorphous semiconductor layer of another conductivity type are stacked on a substrate, and the above crystalline phase is solid-phased at a low temperature at which new crystal nuclei are not formed. A photovoltaic device in which polycrystalline semiconductor layers of one conductivity type and another conductivity type that have been grown and polycrystallized are stacked on a substrate, and also contained in the polycrystalline semiconductor layer of one conductivity type We have developed a photovoltaic device that changes the amount of impurities in the thickness direction.

Further, in the present invention, in manufacturing the above photovoltaic device, a step of forming an amorphous semiconductor layer of one conductivity type on a substrate so that a crystal phase is dispersed, And a step of polycrystallizing the amorphous semiconductor layer by solid-phase growing the above crystal phase at a low temperature at which no crystal nuclei are formed. In manufacturing a photovoltaic device in which a polycrystalline semiconductor layer of a conductivity type is laminated, a step of forming an amorphous semiconductor layer of a conductivity type on a substrate so that a crystal phase is dispersed, Forming another type of amorphous semiconductor layer on the above-mentioned amorphous semiconductor layer, and performing solid phase growth of the above crystal phase at a low temperature at which new crystal nuclei are not formed That is, the step of polycrystallizing the semiconductor layer is performed.

[0016]

In the thin film polycrystalline semiconductor according to the present invention, as described above, the crystal phase in the amorphous semiconductor thin film is solid-phase grown at a low temperature at which new crystal nuclei are not formed, and the amorphous Since the semiconductor thin film is polycrystallized,
A new crystal is not formed other than the above crystal phase grown by solid phase growth, and the thin film polycrystalline semiconductor has a large crystal having no crystal grain boundary in the thickness direction. The film characteristics such as mobility are improved.

In manufacturing such a thin film polycrystalline semiconductor, the amorphous semiconductor thin film is heat-treated at a low temperature at which new crystal nuclei are not formed, and the crystalline phase dispersed in the amorphous semiconductor thin film is removed. Since solid-phase growth was adopted, new crystal nuclei were formed in the amorphous semiconductor thin film and crystallized, and crystals with a small grain size were not formed in the thin film polycrystalline semiconductor. Only the phase is solid-phase grown, and a thin film polycrystalline semiconductor having large crystals without crystal grain boundaries in the thickness direction can be reliably obtained.

Furthermore, since the amorphous semiconductor thin film is heat-treated at a low temperature at which new crystal nuclei are not formed, when the amorphous semiconductor thin film is doped with impurities, the doped impurities are arbitrarily moved during the heat treatment. Then, the device characteristics of the formed thin film polycrystalline semiconductor are not deteriorated, and the amount of impurities to be doped into the amorphous semiconductor thin film is changed in the thickness direction, so that the doping amount of impurities is reduced. A thin film polycrystalline semiconductor having an internal electric field which changes in the thickness direction can be easily obtained.

Further, in the photovoltaic device according to the present invention, the one-conductive type amorphous semiconductor layer is polycrystallized by solid-phase growth at a low temperature at which a crystal phase does not form new crystal nuclei. Type polycrystalline semiconductor is formed on the substrate, the same as in the case of the above thin film polycrystalline semiconductor,
In the one-conductivity-type polycrystalline semiconductor layer, a new crystal is not formed other than the crystal in which the crystal phase is solid-phase grown, and one-conductivity-type polycrystal having a large crystal without grain boundaries in the thickness direction. A crystalline semiconductor layer is obtained, characteristics such as carrier mobility in this one-conductivity-type polycrystalline semiconductor layer are improved, and conversion efficiency in the photovoltaic device is improved.

In manufacturing such a photovoltaic device, an amorphous semiconductor layer of one conductivity type is heat-treated at a low temperature at which new crystal nuclei are not formed and dispersed in the amorphous semiconductor layer. Since it was designed to grow a solid crystal phase,
No new crystal nuclei are formed in the amorphous semiconductor layer to be crystallized, and only the dispersed crystal phase undergoes solid phase growth to form a large crystal having no grain boundaries in the thickness direction. The conductive type polycrystalline semiconductor layer is surely formed on the substrate, and the photovoltaic device with good conversion efficiency as described above can be easily obtained.

Further, as described above, the crystal phase in the one-conductivity-type amorphous semiconductor layer is solid-phase grown at a low temperature at which new crystal nuclei are not formed. Impurities move freely during heat treatment,
The characteristics of the formed one-conductivity-type polycrystalline semiconductor layer are not deteriorated, and the amount of impurities to be doped into the amorphous semiconductor layer is changed in the thickness direction thereof, so that the doping amount of impurities is reduced. Can be easily obtained by changing in the thickness direction and having an internal electric field.

In addition, an amorphous semiconductor layer of one conductivity type in which a crystal phase is dispersed and an amorphous semiconductor layer of another conductivity type are laminated on a substrate, and the above-mentioned is formed at a low temperature at which a new crystal nucleus is not formed. In a photovoltaic device in which polycrystalline semiconductor layers of one conductivity type and another conductivity type, in which a crystal phase is solid-phase grown and polycrystallized, are laminated on a substrate, each of the polycrystalline semiconductors of one conductivity type and other conductivity type A new crystal is not formed in the layer other than the above crystal phase grown by solid phase growth, and there is no grain boundary in the thickness direction across the polycrystalline semiconductor layer of one conductivity type and the other conductivity type. Large crystals are formed, characteristics such as carrier mobility are improved in each of the one-conductivity-type and other-conductivity-type polycrystalline semiconductor layers, and the conversion efficiency in the photovoltaic device is improved.

In manufacturing a photovoltaic device in which a polycrystalline semiconductor layer of one conductivity type and a polycrystalline semiconductor layer of another conductivity type are stacked on a substrate in this manner, the crystal phase is dispersed. When one-conductivity-type amorphous semiconductor layer and another-conductivity-type amorphous semiconductor layer are stacked and the above crystal phase is solid-phase grown at a low temperature at which new crystal nuclei are not formed, No new crystal nuclei are formed in the crystalline semiconductor layer to crystallize, and only crystals in which the dispersed crystal phase is solid-phase grown are formed. A large crystal having no crystal grain boundary in the thickness direction is surely formed over the layer, and the photovoltaic device with good conversion efficiency as described above can be easily obtained.

Further, in the photovoltaic device in which the amount of impurities contained in the one-conductivity type polycrystalline semiconductor layer polycrystallized as described above is changed in the thickness direction thereof, the one-conductivity type An internal electric field is generated in the polycrystalline semiconductor layer, the carrier mobility is further improved by the internal electric field, and the conversion efficiency in the photovoltaic device is further improved.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

(Embodiment 1) In this embodiment, FIG.
As shown in FIG. 3, the microcrystalline silicon layer 20 in which the crystalline phase 21 is dispersed in the amorphous silicon layer 22 is formed on the substrate 10.

In this embodiment, the substrate 10 is made of a highly heat-resistant material such as quartz, metal such as tungsten, molybdenum, and titanium having a flat surface.

When the microcrystalline silicon layer 20 in which the crystalline phase 21 is dispersed in the amorphous silicon layer 22 is formed on the substrate 10 as described above, the gas flow rate is 100 by the plasma CVD method. % SiH ₄ 3-10
sccm, PH ₃ 0.001-0.01 sccm, H ₂
40 to 300 sccm, RF power: 10 to 30 W, reaction pressure: 10 to 100 Pa, substrate temperature: 400 to 650
The gas flow rate is 100% SiH _{4 3} sccm, PH ₃ 0.00
5 sccm, H ₂ 300 sccm, RF power: 30
W, reaction pressure: 54.5 Pa, substrate temperature: 550 ° C., and phosphorus P under conditions of high dilution with hydrogen.
A microcrystalline silicon layer 20 doped with was formed.

Here, when the crystal phase 21 in the microcrystalline silicon layer 20 thus formed was evaluated by a diffraction pattern of a transmission electron microscope, it was found that the crystal phase 21 was composed of a single crystal. .

Further, in this embodiment, as described above, the single crystal crystal phase 21 is dispersed in the amorphous silicon layer 22, and the phosphorus-doped microcrystalline silicon layer 20 is heat-treated to obtain the above-mentioned material. When solid-phase growth of the crystal phase 21 is performed, 500 ° C. and 450 lower than the formation temperature of the microcrystalline silicon layer 20 described above so that new crystal nuclei are not formed.
The heat treatment was performed at two different temperatures of ° C.

Then, as described above, 500 ° C. and 450 ° C.
And the microcrystalline silicon layer 20.
In the step of performing solid phase growth, it was examined how the dark conductivity of the above-mentioned microcrystalline silicon layer 20 changes depending on the time of solid phase growth, and the dark conductivity of the solid phase growth at 500 ° C. Change with a solid line
The change in dark conductivity in the case of solid-phase growth at 450 ° C. is shown in FIG.

As a result, in the case of solid phase growth at a temperature of 500 ° C., the dark conductivity sharply rises by the treatment for about 15 minutes, and if the treatment for 5 hours is performed, the dark conductivity before solid phase growth is increased. The dark conductivity was 50 times. Further, even when solid phase growth was performed at a temperature of 450 ° C., the dark conductivity was improved 10 times or more by the treatment for 10 hours.

As a result, the crystal phase 21 in the microcrystalline silicon layer 20 is solid phase grown even by the heat treatment at about 450 ° C., and the solid phase growth can be performed at a temperature considerably lower than the temperature at which the microcrystalline silicon layer 20 is formed. I found out that

(Embodiment 2) In this embodiment, FIG.
As shown in FIG. 5, a substrate 10 having an uneven surface is used, and a microcrystal in which a crystalline phase 21 is dispersed in an amorphous silicon layer 22 is formed on the surface of the substrate 10 having such an uneven surface. The silicon layer 20 was formed.

When the microcrystalline silicon layer 20 in which the crystal phase 21 is dispersed in the amorphous silicon layer 22 is formed on the surface of the substrate 10 in this manner, also in this embodiment, the microcrystalline silicon layer 20 of the first embodiment described above is used. Similarly to the case, the gas flow rate: 100% SiH _{4 3} sccm, PH by the plasma CVD method
₃ 0.005 sccm, H ₂ 300 sccm, RF power: 30 W, reaction pressure: 54.5 Pa, substrate temperature: 55
The microcrystalline silicon layer 20 doped with phosphorus P was formed under the condition of 0 ° C.

Here, on the surface of the substrate 10 having such an uneven surface, the crystalline phase 21 has an amorphous silicon layer 22.
When the microcrystalline silicon layer 20 dispersed in the above is formed, the crystal phase 21 is dispersed at a wide interval as shown in FIG. 4, as compared with the case of the above-described first embodiment using the substrate 10 having a flat surface. became.

Then, the microcrystalline silicon layer 20 in which the crystal phase 21 is thus dispersed in the amorphous silicon layer 22 is heat-treated at a temperature at which new crystal nuclei are not formed, as in the case of the first embodiment. Then, when the above-mentioned crystal phase 21 is solid-phase grown, a crystal having a larger crystal grain size is formed than in the case of Example 1, and a thin film polycrystal having more excellent film characteristics such as carrier mobility. Silicon was obtained.

(Embodiment 3) In this embodiment, a microcrystalline silicon layer 20 in which a crystal phase 21 is dispersed in an amorphous silicon layer 22 is formed on a substrate 10 in the same manner as in Embodiment 1 above. After the formation, the amorphous silicon layer 30 was formed on the microcrystalline silicon layer 20 as shown in FIG.

Here, in this embodiment, the amorphous silicon layer 30 is formed on the microcrystalline silicon layer 20 as described above.
The amorphous silicon layer 30 is formed by plasma CVD or thermal CVD so as not to dope impurities.
It was formed by the method.

When the amorphous silicon layer 30 is formed by the plasma CVD method, the gas flow rate is 1
00% SiH _{4 40 to} 100 sccm, RF power: 0
˜100 W, reaction pressure: 50 to 1500 Pa, substrate temperature: 400 to 650 ° C.
In this example, gas flow rate: SiH ₄ 40 sccm, R
The amorphous silicon layer 30 was formed under the conditions of F power: 80 W, reaction pressure: 66.5 Pa, and substrate temperature: 550 ° C.

Thus, on the substrate 10, the microcrystalline silicon layer 20 in which the crystal phase 21 is dispersed in the amorphous silicon layer 22 and the amorphous silicon layer 30 not doped with impurities are laminated. In order to prevent new crystal nuclei from being formed, they were heat-treated at a temperature of 500 ° C., which is lower than the formation temperature of the silicon layers 20 and 30, and solid-phase grown.

When solid phase growth is performed in this manner, new crystal nuclei are not generated, and solid phase growth occurs in the crystal phase 21 dispersed in the microcrystalline silicon layer 20 as described above. Happens, as shown in FIG.
This crystal phase 21 gradually becomes larger, and this crystal phase 21 extends in the film thickness direction and grows in the amorphous silicon layer 30 not doped with impurities. Finally, as shown in FIG. A thin film polycrystalline silicon having a crystal 21a continuously extending from the microcrystalline silicon layer 20 to an amorphous silicon layer 30 not doped with impurities and having a large crystal 21a having no crystal grain boundary in the film thickness direction. 40 was obtained.

In the thin-film polycrystalline silicon 40 thus obtained, since there are no crystal grain boundaries in the film thickness direction as described above, the film characteristics such as carrier mobility were good.

(Embodiment 4) Also in this embodiment, as in the case of the above-mentioned Embodiment 3, the substrate 10 is provided with the microcrystalline silicon layer 20 in which the crystal phase 21 is dispersed in the amorphous silicon layer 22.
After the formation, the amorphous silicon layer 30 is formed on the microcrystalline silicon layer 20, as shown in FIG.

Here, in this embodiment, the amorphous silicon layer 30 is formed on the microcrystalline silicon layer 20 as described above.
In forming the film, the amorphous silicon layer 30 doped with phosphorus P as an impurity is formed by plasma CVD or thermal CVD.
It was formed by the method.

When the amorphous silicon layer 30 doped with phosphorus P is formed by the plasma CVD method, the gas flow rate is 100% SiH ₄ 40 to 10.
0 sccm, PH ₃ 0.01 to 0.08 sccm, RF
Power: 0-100W, Reaction pressure: 50-1500P
a, Substrate temperature: set to be in the range of 400 to 650 ° C. so that the atomic concentration of phosphorus P in the amorphous silicon layer 30 is 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . . In this embodiment, gas flow rate: SiH ₄ 40s
ccm, PH ₃ 0.08 sccm, RF power: 30
An amorphous silicon layer 30 doped with phosphorus P was formed under the conditions of W, reaction pressure: 40 Pa, and substrate temperature: 550 ° C.

On the other hand, in order to make a comparison with that of Example 4, in the comparative example, as shown in FIG. 7, the crystalline phase was not dispersed and the amorphous phase was simply doped with phosphorus P. The silicon layer 2 is formed on the substrate 1. In forming the amorphous silicon layer 2 containing no crystal phase in this manner, the amorphous silicon layer 2 is formed on the substrate 1 under the same conditions as in the case of forming the amorphous silicon layer 30 doped with phosphorus P. The amorphous silicon layer 2 was formed directly.

Then, heat treatment was carried out at a temperature of 500 ° C. for the above-mentioned Example 4 and this comparative example, and solid phase growth was performed.

As a result, the microcrystalline silicon layer 2 in which the crystal phase 21 is dispersed in the amorphous silicon layer 22 as in the fourth embodiment.
In the case where 0 was formed, as in the case of Example 3 above, new crystal nuclei were not generated,
Solid phase growth occurs in the portion of the crystal phase 21, the crystal 21a also grows in the amorphous silicon layer 30 doped with phosphorus P, and from the microcrystalline silicon layer 20 to the amorphous silicon layer 20. Crystal 21a continuously extended to 30
And a large crystal 21 with no grain boundaries in the film thickness direction.
A thin film polycrystalline silicon 40 having a was obtained. And
This thin-film polycrystalline silicon 40 also had good film characteristics such as carrier mobility as in the case of Example 3 above.

On the other hand, in the comparative example in which the amorphous silicon layer 2 only doped with phosphorus P was formed on the substrate 1, the atomic concentration of phosphorus P in the amorphous silicon layer 2 was 5 ×. Despite the increase of 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ , solid phase growth did not occur in this amorphous silicon layer 2 and it was not crystallized.

(Embodiment 5) In this embodiment, the substrate 10 is made of an inexpensive material such as glass or stainless steel.

Also in this embodiment, as shown in FIG. 2, the crystal phase 21 is dispersed in the amorphous silicon layer 22 and the phosphorus P is doped on the substrate 10 by the plasma CVD method. The microcrystalline silicon layer 20 was formed.

Here, such a microcrystalline silicon layer 20 is formed.
When plasma is formed by plasma CVD method, gas flow rate: 100% SiH _{4 3 to 10} sccm, PH ₃
0.001~0.01sccm, H ₂ 40~300sc
cm, RF power: 10 to 30 W, reaction pressure: 10 to 1
The substrate temperature was set to be lower than that of the above-described first to third embodiments.

In this embodiment, gas flow rate: 100% SiH _{4 3} sccm, PH ₃ 0.005 s
ccm, H ₂ 300 sccm, RF power: 30 W, reaction pressure: 54.5 Pa, substrate temperature: 500 ° C.,
The crystalline phase 21 has an amorphous silicon layer 22 on the substrate 10.
To form a microcrystalline silicon layer 20 which is dispersed in and doped with phosphorus P.

After the microcrystalline silicon layer 20 is formed on the substrate 10 in this manner, in this embodiment, the microcrystalline silicon layer 20 is doped with impurities as shown in the above-mentioned Embodiment 3. Amorphous silicon layer 30 not formed
Of the amorphous silicon layer 30 doped with phosphorus P as shown in the above-mentioned Example 4 by plasma CVD method or thermal CVD method. I tried to make different kinds.

Here, when the amorphous silicon layer 30 not doped with impurities is formed by the plasma CVD method, the substrate temperature is made lower than in the case of the above-mentioned third embodiment, and the gas flow rate: 100% SiH ₄ 40-100 scc
m, RF power: 0 to 100 W, reaction pressure: 50 to 15
00 Pa, substrate temperature: 400 to 500 ° C., in this embodiment, gas flow rate: SiH _{4 40} sc
cm, RF power: 80 W, reaction pressure: 66.5 Pa,
The amorphous silicon layer 30 not doped with impurities was formed under the condition of the substrate temperature: 500 ° C.

Also, when the phosphorus P-doped amorphous silicon layer 30 is formed by the plasma CVD method, the substrate temperature is set lower than in the case of the above-described fourth embodiment, and the gas flow rate is 100% SiH ₄ 40. ~ 100sccm, PH ₃
0.001 to 4 sccm, RF power: 0 to 100 W,
Reaction pressure: 50 to 1500 Pa, substrate temperature: 400 to 5
The gas flow rate: SiH ₄ 40 sccm, PH ₃ 0.08 sccm,
RF power: 30 W, reaction pressure: 40 Pa, substrate temperature:
The amorphous silicon layer 30 doped with phosphorus P was formed under the condition of 500 ° C.

Then, an amorphous silicon layer 30 not doped with impurities is formed on the microcrystalline silicon layer 20 formed on the substrate 10 made of glass or stainless steel as described above. The amorphous silicon layer 30 doped with phosphorus P was heat-treated at a temperature of 450 ° C. for solid phase growth so that new crystal nuclei were not formed.

As a result, in any of the embodiments, as in the case of the embodiments 3 and 4, (A) and (B) of FIG.
As shown in FIG. 5, solid crystal growth occurs in the portion of the crystal phase 21 in the microcrystalline silicon layer 20 without generation of new crystal nuclei, and the crystal 21a is amorphous in which the above impurities are not doped. Of the crystalline silicon layer 30 and the phosphorus-P-doped amorphous silicon layer 30 to form crystals 21a continuously extending from the microcrystalline silicon layer 20 to the amorphous silicon layer 30. Thin-film polycrystalline silicon 4 having large crystal 21a with no grain boundary
0 was obtained.

The thin-film polycrystalline silicon 40 obtained in this manner also has good film characteristics such as carrier mobility as in Examples 3 and 4, and was made of glass, stainless steel, or the like. The thin film polycrystalline silicon 40 having excellent characteristics was obtained even when the inexpensive substrate 10 was used.

(Embodiment 6) In this embodiment, germanium is used as the semiconductor material instead of the silicon used in the above Embodiments 1 to 5.

Also in this embodiment, as shown in FIG. 2, the crystal phase 21 is the amorphous germanium layer 2
The microcrystalline germanium layer 20 dispersedly present in No. 2 was formed on the substrate 10.

Here, the crystal phase 2 is formed on the substrate 10 as described above.
In forming the microcrystalline germanium layer 20 in which 1 is dispersed in the amorphous germanium layer 22, plasma CV is used.
Gas flow rate: 100% GiH ₄ 1 to 10 s by D method
ccm, PH ₃ 0.001 to 0.01 sccm, H ₂ 4
The temperature was 0 to 300 sccm, the RF power was 5 to 10 W, the reaction pressure was 10 to 100 Pa, and the substrate temperature was 200 to 400 ° C.

Then, after the microcrystalline germanium layer 20 in which the crystal phase 21 is dispersed in the amorphous germanium layer 22 is formed on the substrate 10 in this manner, in this embodiment, as shown in FIG. An amorphous germanium layer 30 not doped with impurities is formed on the microcrystalline germanium layer 20 by the plasma CVD method, and an amorphous germanium layer 30 doped with phosphorus P is formed by the plasma CVD method. And the one formed by.

Here, when the amorphous germanium layer 30 not doped with impurities is formed on the microcrystalline germanium layer 20 by the plasma CVD method, the gas flow rate is 100% GeH ₄ 40 to 100 scc.
m, RF power: 0 to 50 W, reaction pressure: 50 to 150
0 Pa, substrate temperature: 200 to 400 ° C., and when forming the amorphous germanium layer 30 doped with phosphorus P by the plasma CVD method, gas flow rate: 100% GeH ₄ 20 to 50 sccm,
PH ₃ 0.01 to 0.08 sccm, RF power: 0
50 W, reaction pressure: 50 to 1500 Pa, substrate temperature: 2
It was carried out within the range of 00 to 500 ° C.

In this manner, the amorphous germanium layer 30 not doped with impurities and the amorphous germanium layer 30 doped with phosphorus P are formed on the microcrystalline germanium layer 20. About what you did,
In order to prevent the formation of new crystal nuclei, heat treatment was performed at a temperature of 300 ° C. for solid phase growth.

As a result, in any of the embodiments, as in the case of the embodiments 3 to 5, (A) of FIG.
As shown in (B), new crystal nuclei are not generated, and solid phase growth occurs in the part of the crystal phase 21 in the microcrystalline germanium layer 20.
Extend to the amorphous germanium layer 30 not doped with the impurities or the amorphous germanium layer 30 doped with phosphorus P, and continuously extend from the microcrystalline germanium layer 20 to the amorphous germanium layer 30. Thus, a thin film polycrystalline germanium 40 having a large crystal 21a having no crystal grain boundary in the film thickness direction was obtained.

The thin-film polycrystalline germanium 40 thus obtained was also good in film characteristics such as carrier mobility.

Example 7 In this example, silicon germanium (hereinafter, SiGe) was used as a semiconductor material.
Abbreviated. ) Was used.

Also in this embodiment, as shown in FIG. 2, the microcrystalline SiGe layer 20 in which the crystal phase 21 is dispersed in the amorphous SiGe layer 22 is formed on the substrate 10.

Here, the crystal phase 2 is formed on the substrate 10 as described above.
1 is microcrystalline SiGe dispersed in the amorphous SiGe layer 22.
When forming the layer 20, a gas flow rate: 100% GiH ₄ 1 to ₅ sccm, Si is formed by a plasma CVD method.
H ₄ 1~5sccm, PH ₃ 0.001~0.01sc
cm, H ₂ 40 to 300 sccm, RF power: 10
20 W, reaction pressure: 10 to 100 Pa, substrate temperature: 20
It was carried out in the range of 0 to 500 ° C.

Then, the crystal phase 2 is formed on the substrate 10 in this manner.
1 is microcrystalline SiGe dispersed in the amorphous SiGe layer 22.
After forming the layer 20, in this embodiment, as shown in FIG. 5, an amorphous SiGe layer 30 not doped with impurities is formed on the microcrystalline SiGe layer 20 by plasma CVD. And the amorphous SiGe layer 30 doped with phosphorus P formed by the plasma CVD method.

Here, in forming the amorphous SiGe layer 30 which is not doped with impurities by the plasma CVD method on the microcrystalline SiGe layer 20, the gas flow rate is 100% GeH ₄ 20 to 50 sccm, SiH ₄ Two
0 to 50 sccm, RF power: 0 to 50 W, reaction pressure: 50 to 1500 Pa, substrate temperature: 200 to 500 ° C
And in forming the amorphous SiGe layer 30 doped with phosphorus P, the gas flow rate:
100% GeH ₄ 20 to 50 sccm, SiH ₄ 20 to
50 sccm, PH ₃ 0.01 to 0.08 sccm, R
F power: 0 to 100 W, reaction pressure: 50 to 1500 P
a, Substrate temperature: Performed in the range of 200 to 500 ° C.

Thus, the above-mentioned microcrystalline SiGe layer 2 is formed.
0, amorphous SiGe not doped with impurities
For the layer 30 formed and the phosphorus P-doped amorphous SiGe layer 30 formed, solid-phase growth is performed by heat treatment at a temperature of 400 ° C. so that new crystal nuclei are not formed. did.

As a result, in any of the embodiments, as in the cases of the above-mentioned Embodiments 3 to 5, (A) of FIG.
As shown in (B), the crystal phase 21 in the microcrystalline SiGe layer 20 does not generate new crystal nuclei.
Solid phase growth occurs only in the part of
Is an amorphous SiGe layer 30 not doped with impurities
Alternatively, a crystal 21a extending to the amorphous SiGe layer 30 doped with phosphorus P and continuously extending from the microcrystalline SiGe layer 20 to the amorphous SiGe layer 30 is formed. Thin-film polycrystal S with large crystal 21a without
iGe40 was obtained.

Then, the thin film polycrystal S thus obtained
iGe40 also had good film characteristics such as carrier mobility.

In each of Examples 1 to 7 described above, phosphorus P which is an n-type dopant is used as an impurity to be doped, but arsenic As which is another n-type dopant is used. Alternatively, p-type dopant such as boron B or aluminum Al may be used.

(Embodiment 8) In the photovoltaic device according to this embodiment, first, as shown in FIG. 8, the crystal phase 61 is not formed on the substrate 50 made of metal such as tungsten, molybdenum, titanium, and stainless. An n ⁺ -type microcrystalline silicon layer 60 dispersed in the crystalline silicon layer 62 and heavily doped with phosphorus P is formed, and phosphorus n-doped n is formed on the n ⁺ -type microcrystalline silicon layer 60. Type amorphous silicon layer 70 is formed, and ap ⁺ type amorphous silicon layer 80 heavily doped with boron B is further formed on this n type amorphous silicon layer.

[0079] Here, in forming by plasma CVD the n ⁺ -type microcrystalline silicon layer 60 on the substrate 50 as described above, the gas flow rate: 100% SiH ₄ 1~
10 sccm, PH ₃ 0.001-0.01 sccm,
H ₂ 40 to 300 sccm, RF power: 10 to 30
W, reaction pressure: 10 to 100 Pa, substrate temperature: 400 to
The gas flow rate is 100% SiH _{4 3} sccm, PH _{3 in} this embodiment.
0.005 sccm, H ₂ 300 sccm, RF power: 30 W, reaction pressure: 54.5 Pa, substrate temperature: 55
An n ⁺ type microcrystalline silicon layer 60 having a thickness of 0.2 μm was formed under the condition of 0 ° C.

The n ⁺ -type microcrystalline silicon layer 60 is also used.
N-type amorphous silicon layer 7 doped with phosphorus P on
In forming 0 by the plasma CVD method,
Gas flow rate: 100% SiH ₄ 40-100 sccm, P
H ₃ 0 to 0.0008 sccm, RF power: 0 to 10
0 W, reaction pressure: 50 to 1500 Pa, substrate temperature: 40
The gas flow rate is 100% SiH ₄ 40 sccm, P in this embodiment.
An n-type amorphous silicon layer 70 having a film thickness of 10 μm was formed under the conditions of H ₃ 8 × 10 ⁻⁶ sccm, RF power: 80 W, reaction pressure: 65.5 Pa, and substrate temperature: 550 ° C.

Further, this n-type amorphous silicon layer 70 is formed.
When the p ⁺ -type amorphous silicon layer 80 heavily doped with boron B is formed on the upper surface by the plasma CVD method, the gas flow rate is 100% SiH ₄ 40 to 100 sc
cm, B ₂ H ₆ 0.02 to 0.1 sccm, RF power: 10 to 30 W, reaction pressure: 10 to 100 Pa, substrate temperature: 400 to 650 ° C. In this example, gas is used. Flow rate: 100% SiH ₄ 20s
ccm, B ₂ H ₆ 0.1 sccm, RF power: 20
Under the conditions of W, reaction pressure: 33 Pa, and substrate temperature: 550 ° C., a p ⁺ -type amorphous silicon layer 80 having a film thickness of 0.2 μm was formed.

In this way, the n ⁺ type microcrystalline silicon layer 60, the n type amorphous silicon layer 70, and the
With the p ⁺ -type amorphous silicon layer 80 formed, each silicon layer 60, so that new crystal nuclei are not formed,
Heat treatment was performed at a temperature of 500 ° C., which is lower than the formation temperatures of 70 and 80, to perform solid phase growth.

When solid phase growth is performed in this manner, new crystal nuclei are not generated, and in the crystal phase 61 dispersed in the n ⁺ -type microcrystalline silicon layer 60 as described above. Solid phase growth occurs, and as shown in FIG. 9A, the crystal phase 61 gradually increases, and the crystal phase 61 extends in the film thickness direction to form the n-type amorphous silicon layer 70.
Finally, as shown in FIG. 7B, the n ⁺ type microcrystalline silicon layer 60 to the n type amorphous silicon layer 70 and the p ⁺ type amorphous silicon layer 80 are finally grown. N ⁺ -type polycrystalline silicon layer 60a having a large crystal 61a having no crystal grain boundary in the film thickness direction, an n-type polycrystalline silicon layer 70a, and ap ⁺ -type Obtained by laminating the polycrystalline silicon layer 80a and the polycrystalline silicon layer 80a on the substrate 50. The p ⁺ -type polycrystalline silicon layer 8
The sheet resistance at 0a was about 80 Ω / □.

Then, solid phase growth was performed in this manner to form an n ⁺ type polycrystalline silicon layer 60a, an n type polycrystalline silicon layer 70a, and ap ⁺ type polycrystalline silicon layer 80a on the substrate. After that, as shown in FIG. 10, a width of 0.1 mm and a height of 0.1 mm are formed on the p ⁺ -type polycrystalline silicon layer 80a.
2 to 3 m of the surface electrode 91 made of 2 mm of aluminum
The antireflection film 92 made of silicon nitride (SiN) is formed to a thickness of about 0.1 μm on the portion where the surface electrode 91 is not formed, and the photovoltaic device is obtained. It was

Here, the current-voltage characteristics of the photovoltaic device of this embodiment are as shown in FIG.
In the photovoltaic device of this embodiment, the short-circuit photocurrent Isc is 30.5 mÅ / cm ² and the open circuit voltage Voc is 0.
525V, fill factor F.I. F. Was 0.65, the conversion efficiency was 10.4%, and the short-circuit photocurrent and the fill factor were good, and the conversion efficiency was high.

Next, as in the case of the photovoltaic device according to this embodiment, n ⁺ in which the crystalline phase 61 is dispersed in the amorphous silicon layer 62 and which is heavily doped with phosphorus P is formed on the substrate 50. After forming the n-type microcrystalline silicon layer 60, in forming the n-type amorphous silicon layer 70 doped with phosphorus P on the n + -type microcrystalline silicon layer 60, the plasma CVD method described above is used. SiH ₄ used in
And PH ₃ gas flow rates are appropriately changed so that the phosphorus P atom concentration is 1 × 10 ¹⁶ cm ⁻³ , 1 × 10 ¹⁷ cm ⁻³ , 1 × 1.
Three kinds of n-type amorphous silicon layers 7 having a size of 0 ¹⁸ cm ^-3
0 is formed, and thereafter, on each of these n-type amorphous silicon layers 70, p ⁺ -type non-doped non-doped p-type heavily doped with boron B is formed in the same manner as in the above-described embodiment. A crystalline silicon layer 80 was formed.

Then, in the case where the three types of the n-type amorphous silicon layers 70 having different phosphorus P atomic concentrations are formed, new crystal nuclei are not formed, as in the case of the above-described embodiments. As described above, a large crystal 6 having no grain boundaries in the film thickness direction is formed by heat treatment at a temperature of 500 ° C. and solid phase growth.
An n ⁺ type polycrystalline silicon layer 60a having 1a, an n type polycrystalline silicon layer 70a, and ap + type polycrystalline silicon layer 80a were laminated on the substrate 50.

Then, before the solid phase growth and after the solid phase growth as described above, the changes in the atomic concentration of phosphorus or boron doped in the respective silicon layers are measured to carry out the solid phase growth. The result before performing is shown in (A) of FIG. 12, and the result after performing solid phase growth is shown in (B) of the same figure.

As a result, when solid phase growth is performed at a low temperature of about 500 ° C. at which new crystal nuclei are not formed as described above, phosphorus P or boron B doped in each of the silicon layers is solid-phase grown. Without moving, p above
^At the junction interface between the ⁺ -type polycrystalline silicon layer 80a and the n-type polycrystalline silicon layer 70a, the atomic concentration of boron B was drastically reduced, and a pn junction having good characteristics was formed.

(Embodiment 9) In this embodiment, the substrate 5 is used in the same manner as the photovoltaic device of the above-mentioned Embodiment 8.
0 After forming the n ⁺ -type microcrystalline silicon layer 60 on, in forming the amorphous silicon layer 70 of n-type with phosphorous P doped on the n ⁺ -type microcrystalline silicon layer 60, SiH ₄ used in the above plasma CVD method
And the amount of PH ₃ are changed with time so that the atomic concentration of phosphorus P doped in the n-type amorphous silicon layer 70 is gradually decreased.

Here, in this embodiment, when forming the n-type amorphous silicon layer 70 as described above, RF power: 80 W, reaction pressure: 70 Pa, substrate temperature: 550 by plasma CVD method. Under the condition of ℃,
2% PH ₃ for 100% SiH ₄ 100 sccm
The atomic concentration of phosphorus P is gradually decreased in the range of × 10 ^{-4 to} 2 × 10 ^-5 sccm and the phosphorus P atomic concentration is 1 × 10 ¹⁷ cm ^-3 to 1 × 10 ^16.
n-type amorphous silicon layer changed in the range of cm ⁻³ , and 1
2% of PH ₃ for 100 sccm of 00% SiH ₄
The atomic concentration of phosphorus P is gradually reduced in the range of 10 ^{−3 to} 2 × 10 ⁻⁴ sccm so that the phosphorus P atomic concentration is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ^17.
An n-type amorphous silicon layer changed in the range of cm ⁻³ is formed on the n ⁺ -type microcrystalline silicon layer 60, and then each n-type amorphous silicon layer is formed. On each of the layers 70, as in Example 8 above,
A p ⁺ type amorphous silicon layer 80 heavily doped with boron B was formed.

After forming the p ⁺ -type amorphous silicon layer 80 in this way, as in the case of Example 8 above, 500 times are formed so that new crystal nuclei are not formed.
N ⁺ -type polycrystalline silicon layer 60a having a large crystal 21a without crystal grain boundaries in the film thickness direction, n-type polycrystalline silicon layer 70a, and p
A + -type polycrystalline silicon layer 80 a and a + -type polycrystalline silicon layer 80 a were laminated on the substrate 50.

Here, after the solid phase growth as described above, the atomic concentration of phosphorus or boron doped in each of the polycrystalline silicon layers 60a, 70a and 80a was measured, and the result is shown in FIG. .

As a result, when solid phase growth is carried out at a low temperature of about 500 ° C. at which new crystal nuclei are not formed as described above, phosphorus P or boron B doped in each silicon layer moves during solid phase growth. Even if the n-type amorphous silicon layer 70 in which the atomic concentration of phosphorus P is gradually changed in the thickness direction is crystallized as described above, the doped phosphorus P moves. No, phosphorus P
An n-type polycrystalline silicon layer 70a having an atomic concentration of gradually changing in the thickness direction was obtained, and an internal electric field was generated in the n-type polycrystalline silicon layer 70a.

Then, in the same manner as in Example 8 described above, the surface electrode 91 and the antireflection film 92 were formed on the p ⁺ -type polycrystalline silicon layer 80a to obtain a photovoltaic device. In this case, in this photovoltaic device, the internal electric field in the n-type polycrystalline silicon layer 70a allows the carriers to be collected more efficiently, which further improves the conversion efficiency.

(Embodiment 10) In the photovoltaic device according to this embodiment, the order of the silicon layers to be laminated on the substrate is changed from that of the above-mentioned embodiment 8, and the crystalline layer on the substrate is amorphous silicon. A p ⁺ type microcrystalline silicon layer dispersed in the layer and heavily doped with boron B is formed, and p type amorphous silicon doped with boron B is formed on the p ⁺ type microcrystalline silicon layer. Layer, and on the p-type amorphous silicon layer, n ⁺ heavily doped with phosphorus P
To form a mold type amorphous silicon layer.

Here, in forming the p ⁺ -type microcrystalline silicon layer on the substrate by the plasma CVD method as described above, the gas flow rate: 100% SiH ₄ 1-10 sc
cm, B ₂ H ₆ 0.001-0.01 sccm, H ₂ 4
0 to 300 sccm, RF power: 10 to 30 W, reaction pressure: 10 to 100 Pa, substrate temperature: 400 to 650 ° C
The gas flow rate: 100% SiH _{4 3} sccm, B ₂ H ₆ 0.00
5 sccm, H ₂ 300 sccm, RF power: 30
Under the conditions of W, reaction pressure: 54.5 Pa, and substrate temperature: 550 ° C., a p ⁺ -type microcrystalline silicon layer having a film thickness of 0.2 μm was formed.

When a p-type amorphous silicon layer doped with boron B is formed on the p ⁺ -type microcrystalline silicon layer by the plasma CVD method, gas flow rate: 100% SiH ₄ 40- 100 sccm, B ₂ H ₆
0 to 0.0008 sccm, RF power: 0 to 100
W, reaction pressure: 50 to 1500 Pa, substrate temperature: 400
The gas flow rate is 100% SiH ₄ 40 sccm, B _{2 in} this embodiment.
Under conditions of H ₆ 8 × 10 ⁻⁶ sccm, RF power: 80 W, reaction pressure: 66.5 Pa, and substrate temperature: 550 ° C., a p-type amorphous silicon layer having a film thickness of 10 μm was formed.

Further, in forming the n ⁺ type amorphous silicon layer heavily doped with phosphorus P on the p type amorphous silicon layer by the plasma CVD method,
Gas flow rate: 100% SiH ₄ 40-100 sccm, P
H ₃ 0.02~0.1sccm, RF power: 10-3
0 W, reaction pressure: 10 to 100 Pa, substrate temperature: 400
650 ° C., and in this embodiment, gas flow rate: 100% SiH ₄ 20 sccm, PH
₃ 0.1sccm, RF power: 20W, Reaction pressure: 3
The film thickness is 0.2μ under the conditions of 3 Pa and substrate temperature: 550 ° C.
An n ⁺ -type amorphous silicon layer having a thickness of m was formed.

Then, a new crystal is formed with the p ⁺ -type microcrystalline silicon layer, the p-type amorphous silicon layer, and the n ⁺ -type amorphous silicon layer thus formed on the substrate. In order to prevent the formation of nuclei, heat treatment was performed at a temperature of 500 ° C., which is lower than the formation temperature of each silicon layer, and solid phase growth was performed.

When solid-phase growth is performed in this manner, no new crystal nuclei are generated as in the case of Example 8, and p ⁺ -type microcrystalline silicon is used as described above. Solid phase growth occurs in the crystal phase 21 dispersed in the layer 20, the crystal phase 21 gradually increases, and finally, from the p ⁺ type microcrystalline silicon layer to the p type amorphous silicon layer and n ^+. formed crystals 21a extending continuously in the amorphous silicon layer type, and the p ⁺ -type polycrystalline silicon layer having a large crystal 21a with no grain boundaries in the film thickness direction, p-type polycrystalline silicon layer And an n ⁺ -type polycrystalline silicon layer were laminated on the substrate.

Then, on the n ⁺ -type polycrystalline silicon layer thus solid-phase-grown, aluminum having a width of 0.1 mm and a height of 0.2 mm is formed in the same manner as in the case of the eighth embodiment. The surface electrodes are formed at intervals of 2 to 3 mm, and an antireflection film made of silicon nitride (SiN) is formed on the portion where the surface electrodes are not formed by about 0.1 mm.
A photovoltaic device was obtained by forming with a film thickness of μm.

Here, the current-voltage characteristics of the photovoltaic device of this embodiment are as shown in FIG.
In the photovoltaic device of this embodiment, the short-circuit photocurrent Isc is 30.5 mÅ / cm ² and the open circuit voltage Voc is 0.
53 V, fill factor F.I. F. Is 0.7 and conversion efficiency is 1
It was 1.3%, and the short-circuit photocurrent and fill factor were good, and the conversion efficiency was high.

Further, in the photovoltaic device according to this embodiment, when the p-type amorphous silicon layer doped with boron B is formed on the p ⁺ -type microcrystalline silicon layer, the plasma described above is used. Si used in the CVD method
By appropriately changing the amounts of H ₄ and B ₂ H ₆ , the atomic concentration of boron B is 1 × 10 ¹⁶ cm ⁻³ , 1 × 10 ¹⁷ cm ⁻³ , 1 ×.
Three types of p-type amorphous silicon layers each having a thickness of 10 ¹⁸ cm ⁻³ were formed, and then, on each of these p-type amorphous silicon layers, the same as in the above case. Then, an n ⁺ type amorphous silicon layer heavily doped with phosphorus P was formed.

When these were heat-treated at a temperature of 500 ° C. for solid phase growth as described above, the above-mentioned Example 8 was used.
In the same manner as in the case of forming three types of n-type amorphous silicon layers in which the atomic concentration of phosphorus P is changed in, the phosphorus P and boron B doped in each of the above silicon layers move during solid phase growth. Characteristics are not deteriorated, and the atomic concentration of phosphorus P is drastically reduced at the interface where the n ⁺ -type polycrystalline silicon layer is joined to the p-type polycrystalline silicon layer. A good pn junction was formed.

In forming the p-type amorphous silicon layer doped with boron B, the plasma CV described above is used.
By sequentially changing the amounts of SiH ₄ and B ₂ H ₆ used in the D method, the atomic concentration of boron B doped in the p-type amorphous silicon layer is gradually decreased in the film thickness direction to obtain the p-type Even when the atomic concentration of boron B contained in the amorphous silicon layer is gradually changed in the thickness direction, it is heat treated at a temperature of 500 ° C. to perform solid phase growth, as in the case of Example 9 described above. Then, boron B does not move during solid-phase growth, and a p-type polycrystalline silicon layer in which the atomic concentration of doped boron B is gradually changed in the thickness direction is formed, and this p-type polycrystalline silicon is formed. When an internal electric field is generated in the layer and is used in a photovoltaic device, the internal electric field in the p-type polycrystalline silicon layer allows the carriers to be collected more efficiently and the conversion efficiency to be further improved.

(Embodiment 11) In the photovoltaic device of this embodiment, in the same manner as in the case of Embodiment 8 above,
The substrate 50, after the crystal phase 61 to form a phosphorus P number doped n ⁺ -type microcrystalline silicon layer 60 while being dispersed in the amorphous silicon layer 62, the microcrystalline silicon layer of the n ⁺ -type An n-type amorphous silicon layer 70 doped with phosphorus P was formed on 60.

Then, with the n ⁺ -type microcrystalline silicon layer 60 and the n-type amorphous silicon layer 70 formed on the substrate 50 as described above, each silicon is prevented so that new crystal nuclei are not formed. 500 below the formation temperature of layers 60, 70
It heat-processed at the temperature of (degree C) and solid-phase-grown.

When solid phase growth is performed in this manner, new crystal nuclei are not generated and solid phase growth occurs in the crystal phase 61 dispersed in the n ⁺ -type microcrystalline silicon layer 60. , A crystal 21a extending continuously from the n ⁺ type microcrystalline silicon layer 60 to the n type amorphous silicon layer 70 is formed, and as shown in FIG. 15, there is no crystal grain boundary in the film thickness direction. An n ⁺ type polycrystalline silicon layer 60a having a large crystal 21a and an n type polycrystalline silicon layer 70
and a are formed on the substrate 50.

Then, in the present embodiment, as shown in the figure, a gas flow rate of 100% SiH ₄ is formed on the n-type polycrystalline silicon layer 70a formed as described above by the plasma CVD method. 40 sccm, RF power:
An i-type amorphous silicon layer 93 is formed under the conditions of 3 W, reaction pressure: 10 Pa, and substrate temperature: 130 ° C.
On the amorphous silicon layer 93 of the type by a plasma CVD method, gas flow rate: 100% SiH ₄ 5 sccm, B ₂ H ₆
0.1 sccm, RF power: 3 W, reaction pressure: 13 P
a, Substrate temperature: The p-type amorphous silicon layer 94 was formed under the condition of 130 ° C.

Then, on the p-type amorphous silicon layer 94 thus formed, the surface electrode 91 and the antireflection film 92 are provided in the same manner as in the case of the above-described eighth embodiment to provide the photovoltaic power. I got the device.

Also in the photovoltaic device obtained as described above, carriers are efficiently generated in the n ⁺ type polycrystalline silicon layer 60a and the n type polycrystalline silicon layer 70a formed on the substrate 60. It was collected and the conversion efficiency was high.

(Embodiment 12) Also in the photovoltaic device according to this embodiment, as in the case of the above-mentioned embodiment 8,
The substrate 50, after the crystal phase 61 to form a phosphorus P number doped n ⁺ -type microcrystalline silicon layer 60 while being dispersed in the amorphous silicon layer 62, the microcrystalline silicon layer of the n ⁺ -type An n-type amorphous silicon layer 70 doped with phosphorus P was formed on 60.

Then, with the n ⁺ -type microcrystalline silicon layer 60 and the n-type amorphous silicon layer 70 formed on the substrate 50 as described above, each silicon is prevented so that new crystal nuclei are not formed. 500 below the formation temperature of layers 60, 70
It heat-processed at the temperature of (degree C) and solid-phase-grown.

When solid phase growth is performed in this way, new crystal nuclei are not generated, and solid phase growth occurs in the crystal phase 61 dispersed in the n ⁺ -type microcrystalline silicon layer 60. , A crystal 21a continuously extending from the n ⁺ type microcrystalline silicon layer 60 to the n type amorphous silicon layer 70 is formed, and as shown in FIG.
N having a large crystal 21a with no grain boundary in the film thickness direction
^{A +} -type polycrystalline silicon layer 60a and an n-type polycrystalline silicon layer 70a were formed on the substrate 50.

In the present embodiment, as shown in the same figure, a gas flow rate of 100% SiH ₄ is formed on the n-type polycrystalline silicon layer 70a formed as described above by the plasma CVD method. 5 sccm, B ₂ H ₆ 0.1
sccm, RF power: 3 W, reaction pressure: 13 Pa, substrate temperature: 130 ° C., p-type amorphous silicon layer 95
And then heat-treating the p-type amorphous silicon layer 95 thus formed at 600 ° C. for solid phase growth,
As shown in FIG. 7B, a p-type polycrystalline silicon layer 95a was formed on the n-type polycrystalline silicon layer 70a.

Then, on the p-type polycrystalline silicon layer 95a thus formed, the surface electrode 91 and the antireflection film 92 are provided in the same manner as in the case of the above-mentioned eighth embodiment to provide the photovoltaic device. To get.

Also in the photovoltaic device thus obtained, carriers are efficiently generated in the n ⁺ type polycrystalline silicon layer 60a and the n type polycrystalline silicon layer 70a formed on the substrate 60. It was collected and the conversion efficiency was high.

In the photovoltaic devices in Examples 8 to 11 described above, an example in which silicon was used as the semiconductor material was shown. However, instead of silicon, the thin film thin film of Examples 6 and 7 was used. The photovoltaic device as described above can be manufactured by using germanium or silicon germanium used in the crystalline semiconductor, and the photovoltaic devices manufactured in this way are also the photovoltaic devices of Examples 8 to 11 above. As with the power device, the conversion efficiency is higher.

[0120]

As described above in detail, in the thin film polycrystalline semiconductor according to the present invention, a new crystal is not formed in addition to the solid phase grown crystal phase of the amorphous semiconductor thin film. Since it has a large crystal without grain boundaries in the thickness direction, the device characteristics such as carrier mobility and conversion efficiency were good.

When a thin film polycrystalline semiconductor is manufactured by the method for manufacturing a thin film polycrystalline semiconductor according to the present invention,
As described above, a thin film polycrystalline semiconductor having good film characteristics such as carrier mobility is easily manufactured, and the amorphous semiconductor thin film is heat-treated at a low temperature at which new crystal nuclei are not formed. Impurities doped in the thin film do not move arbitrarily during heat treatment, and the doping amount of impurities can be changed in the thickness direction to have an internal electric field. Semiconductors have become easy to obtain.

Further, in the photovoltaic device according to the present invention, as in the case of the above-mentioned thin film polycrystalline semiconductor, a new crystal other than the crystal in which the crystal phase is solid-phase grown in the one-conductivity type polycrystalline semiconductor layer. Is not formed,
A one-conductivity-type polycrystalline semiconductor layer having large crystals with no crystal grain boundaries in the thickness direction was formed, characteristics such as carrier mobility were improved, and conversion efficiency was improved.

When the photovoltaic device is manufactured by the method for manufacturing a photovoltaic device according to the present invention, the above-mentioned photovoltaic device having good conversion efficiency can be easily manufactured, and
It is also possible to form a one-conductivity-type polycrystalline semiconductor layer having an internal electric field by changing the doping amount of impurities in the thickness direction, and it has become possible to easily manufacture a photovoltaic device having higher conversion efficiency.

[Brief description of drawings]

FIG. 1 is a schematic view showing a crystal structure of a conventional thin film polycrystalline semiconductor.

FIG. 2 is a schematic view showing a state in which an amorphous semiconductor thin film in which a crystal phase is dispersed is formed on a substrate having a flat surface in a thin film polycrystalline semiconductor according to an example of the present invention.

FIG. 3 is a solid phase diagram of a thin film polycrystalline semiconductor according to an embodiment of the present invention, in which an amorphous semiconductor thin film in which a crystal phase is dispersed on a substrate having a flat surface is solid phase grown at 450 ° C. and 500 ° C. It is a graph which showed change of dark conductivity according to growth time.

FIG. 4 is a schematic view showing a state in which an amorphous semiconductor thin film in which a crystal phase is dispersed is formed on a surface of a substrate having an uneven surface in a thin film polycrystalline semiconductor according to an example of the present invention. .

FIG. 5 shows a state in which a thin film polycrystalline semiconductor according to an embodiment of the present invention has a substrate on which a microcrystalline semiconductor layer having a crystalline phase dispersed in an amorphous semiconductor layer and an amorphous semiconductor layer are stacked. FIG.

FIG. 6 shows a state in which a dispersed crystal phase in a microcrystalline semiconductor layer formed on a substrate grows in the thin film polycrystalline semiconductor according to the embodiment of the present invention to form a thin film polycrystalline semiconductor on the substrate. It is the schematic shown.

FIG. 7 is a schematic view showing a state in which an amorphous semiconductor layer in which a crystal phase is not dispersed is formed on a substrate in a comparative example.

FIG. 8 shows a photovoltaic device according to an embodiment of the present invention, in which a crystalline phase is dispersed in an amorphous semiconductor layer and one conductivity type microcrystalline semiconductor layer highly doped with impurities is formed on a substrate; FIG. 3 is a schematic view showing a state where a conductive type amorphous semiconductor layer and another conductive type amorphous semiconductor layer are stacked.

FIG. 9 shows a photovoltaic device according to an embodiment of the present invention, in which a crystalline phase in a one-conductivity-type microcrystalline semiconductor layer formed on a substrate grows and one impurity-doped one-conductivity is highly doped on the substrate. FIG. 6 is a schematic diagram showing a state in which a type polycrystalline semiconductor layer, one conductivity type polycrystalline semiconductor layer, and another conductivity type polycrystalline semiconductor layer are formed.

FIG. 10 is a schematic view of a photovoltaic device according to an embodiment of the present invention.

FIG. 11 is a diagram showing current-voltage characteristics of the photovoltaic device according to the example of the present invention.

FIG. 12 shows how the amount of impurities doped in each semiconductor layer formed on a substrate changes before and after solid phase growth in the photovoltaic device according to the example of the present invention. It is the graph which investigated.

FIG. 13 is a diagram showing a photovoltaic device according to an embodiment of the present invention, in which solid phase growth is performed by changing the amount of impurities contained in one conductivity type amorphous semiconductor layer in the thickness direction, and after solid phase growth, impurities are deposited. It is the graph which investigated how the amount of changes.

FIG. 14 is a diagram showing current-voltage characteristics of a photovoltaic device according to another embodiment of the present invention.

FIG. 15 shows a photovoltaic device according to an embodiment of the present invention in which an n ⁺ type polycrystalline semiconductor layer, an n type polycrystalline semiconductor layer, an i type amorphous semiconductor layer, and a p type amorphous are formed on a substrate. It is the schematic which showed the state which laminated | stacked with the quality semiconductor layer.

FIG. 16 shows a photovoltaic device according to an embodiment of the present invention after an n ⁺ -type polycrystalline semiconductor layer, an n-type polycrystalline semiconductor layer and a p-type amorphous semiconductor layer are laminated on a substrate. , P
FIG. 3 is a schematic view showing a state in which a p-type polycrystalline semiconductor layer is formed by solid phase growth of a p-type amorphous semiconductor layer.

[Explanation of symbols]

10 Substrate 20 Microcrystalline Semiconductor Layer 21 Crystal Phase 22 Amorphous Semiconductor Layer 40 Thin Film Polycrystalline Semiconductor 50 Substrate 60 n ⁺ Type Microcrystalline Silicon Layer 60a n ⁺ Type Polycrystalline Silicon Layer 70 n Type Amorphous Silicon Layer 70a n-type polycrystalline silicon layer 80 p ⁺ -type microcrystalline silicon layer 80a p ⁺ -type polycrystalline silicon layer

Claims (8)

[Claims] 1. The amorphous semiconductor thin film is polycrystallized by solid phase growth at a low temperature at which a crystal phase in the amorphous semiconductor thin film does not form new crystal nuclei. Thin film polycrystalline semiconductor. 2. The thin film polycrystalline semiconductor according to claim 1, wherein the semiconductor material is any one of silicon, germanium, and silicon germanium. 3. A step of forming an amorphous semiconductor thin film in which a crystal phase is dispersed on a substrate, and a heat treatment of the amorphous semiconductor thin film at a low temperature at which new crystal nuclei are not formed, thereby removing the above crystal phase. A method of manufacturing a thin film polycrystalline semiconductor, which comprises a step of solid phase growth. 4. A polycrystalline semiconductor of one conductivity type which is polycrystallized by solid phase growth at a low temperature at which a crystal phase in the amorphous semiconductor layer of one conductivity type does not form new crystal nuclei, is formed on a substrate. A photovoltaic device characterized by being formed. 5. A one-conductivity-type amorphous semiconductor layer in which a crystal phase is dispersed and a second-conductivity-type amorphous semiconductor layer are laminated on a substrate, and the above-mentioned is formed at a low temperature at which a new crystal nucleus is not formed. 1. A photovoltaic device, comprising: one-conductivity-type and other-conductivity-type polycrystalline semiconductor layers, which are polycrystallized by solid-phase growth of a crystal phase, on a substrate. 6. The photovoltaic device according to claim 4 or 5, wherein the amount of impurities contained in the polycrystallized one-conductivity-type polycrystalline semiconductor layer varies in the thickness direction. A characteristic photovoltaic device. 7. A step of forming an amorphous semiconductor layer of one conductivity type on a substrate so as to disperse the crystal phase, and solid-phase growing the crystal phase at a low temperature at which new crystal nuclei are not formed. And a step of polycrystallizing the amorphous semiconductor layer. 8. A step of forming an amorphous semiconductor layer of one conductivity type on a substrate such that a crystal phase is dispersed, and an amorphous semiconductor layer of another conductivity type on the amorphous semiconductor layer of one conductivity type. A method comprising: a step of forming a semiconductor layer; and a step of polycrystallizing each of the above-mentioned amorphous semiconductor layers by solid-phase growing the above crystal phase at a low temperature at which new crystal nuclei are not formed. Manufacturing method of electromotive force device.