JPH0879064A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE: To reduce the cost of an integrated circuit by providing a reference voltage source so as to apply its generated voltage to a voltage controlled oscillator circuit thereby eliminating the need for the provision of a resistor and reducing a chip area. CONSTITUTION: A loop filter 200 is provided with reference voltage sources 10,11. Upon the receipt of a signal UP from a phase comparator, a switch 6 is closed and a current Ip is supplied to a capacitor 3 from a constant current source 4. Furthermore, a switch S is thrown to the position of a terminal 80, a voltage of the reference voltage source 10 is added to a terminal voltage of the capacitor 3 by an adder circuit 12 and the resulting sum voltage is given to a voltage controlled oscillator circuit 100. Upon the receipt of a signal DOWN from the phase comparator, a switch 7 is closed and a current Ip from a constant current source 5 flows out of the capacitor 3. Furthermore, the switch S is thrown to the position of a terminal 90, a voltage of the reference voltage source 11 is added to the terminal voltage of the capacitor 3 by the adder circuit 12 and the resulting sum voltage is given to a voltage controlled oscillator circuit 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly to a charge pump type phase locked loop circuit.

[0002]

2. Description of the Related Art A general phase locked loop circuit will be described with reference to FIG. FIG. 5 is a block diagram showing the configuration of a general phase locked loop circuit. In the figure, the phase locked loop circuit is configured to include a phase comparator 300 for comparing the phases of the input IN and the output OUT, and a voltage controlled oscillator circuit 100 whose oscillation frequency is controlled by the result of the phase comparison. , The output O of the voltage controlled oscillator circuit 100
The UT is negatively fed back to the phase comparator 300. A loop filter 200 is provided between the phase comparator 300 and the voltage controlled oscillator circuit 100.

In such a configuration, the input IN and the output OU
The phase with T is compared in the phase comparator 300. As a result of the comparison, the UP signal is output when the phase of the input IN is ahead of the phase of the output OUT, and the DOWN signal is output when the phase is delayed. The time when the UP signal or the DOWN signal is output is the time corresponding to the phase difference between the input IN and the output OUT. Since the UP signal or the DOWN signal is smoothed by the loop filter 200 and then input to the voltage controlled oscillator circuit 100, the phase of the output signal OUT approaches the phase of the input signal IN due to the action of negative feedback, and eventually matches.

By the way, MOS (Metal Oxid)
As a configuration of a phase locked loop suitable for an eSemiconductor (Integrated Circuit) integrated circuit, there is a charge pump type phase locked loop. An example of the configuration of the charge pump type phase locked loop is described in, for example, the document “Change-Pump Ph”.
ase-Lock Loops, IEEE TRAN
SACTIONS ON COMMUNICATION
S, VOL. COM-28, NO. 11, NOVEM
As is well known for "BER 1980". The configuration of the loop filter portion is shown in FIG. 6, and the same portions as those in FIG. 5 are designated by the same reference numerals.

In FIG. 6, the loop filter 200 is
A resistor 2 having a resistance value R, a capacitance 3 having a capacitance value C, and a current value Ip
The constant current sources 4 and 5, the switch 6 controlled to open / close by the signal UP, and the switch 7 controlled to open / close by the signal DOWN. The gain of the voltage controlled oscillator circuit 100 is K0.

In the loop filter 200 having such a configuration, when the signal UP is input from the phase comparator, the switch 6
Is closed, and the current Ip flows from the constant current source 4 into the resistor 2 and the capacitor 3. While the current Ip is flowing in, a rectangular voltage having a voltage value Ip * R is generated across the resistor 2, and an integrated voltage having a slope Ip / C is generated at the terminal of the capacitor 3.

When the signal DOWN is input from the phase comparator, the switch 7 is closed, and the constant current source 5 causes the current Ip to flow out from the resistor 2 and the capacitor 3. While the current Ip is flowing, a rectangular voltage having a voltage value −Ip * R is generated across the resistor 2 and an integrated voltage having a slope −Ip / C is generated at the terminal of the capacitor 3.

This charge pump type loop filter 20
0 plays a role as a loop filter by the integral action of the above current source and capacitance. By inserting the resistor 2 in series with the capacitor 3, the order of the loop becomes quadratic. Natural frequency (na), which is a factor that determines the characteristics of the phase-locked loop using this filter
total frequency) ω n, attenuation rate (da
The mpping factor) ξ is expressed as follows.

Ωn = {(K0 * Ip) / (2 * π * C)} ^1/2 (1) ξ = (R * C / 2) * ωn (2) In the equation (1), K0 is It is the gain of the voltage controlled oscillator circuit.

[0010]

The conventional charge pump type phase locked loop described above has the following drawbacks.

First, in the secondary phase-locked loop,
If the damping rate ξ is set to ξ <1, there is a drawback that insufficient braking occurs and ringing occurs in the output. Therefore, a value of about ξ = 1.4 is usually used.

On the other hand, since it is the natural number wn that determines the band of the loop, the product of R * C required to obtain the desired ξ and ωn is determined from the above equation (2). However, if you want to narrow the band of the loop, in other words, w
If we want to reduce n, we have to increase the product of R * C. The use of large-capacity C and high-resistance R in an integrated circuit is a big drawback because it occupies a very large area.

In particular, recent CMOS (Complement)
In the nary MOS) process, the layer resistance made of polysilicon is lowered to about 10Ω / □ (the resistance value between the opposing sides of the square resistor is about 10Ω) in order to increase the speed. For example, it is desired to use a resistor of 10KΩ. In this case, the aspect ratio is 1000. As you can see from this example,
Resistors are becoming a large area on chips.

On the other hand, a method using a resistor having a relatively small value has been considered. For example, the technique shown in FIG. 7, parts equivalent to those in FIGS. 5 and 6 are indicated by the same reference numerals, and a configuration in which a pair of constant current sources is provided for the resistance and the capacitance is shown.

That is, the constant current sources 4 and 5 having the current value Ipr are provided corresponding to the resistance 2 having the resistance value R, and the constant current sources 6 and 7 having the current value Ipc are provided corresponding to the capacitance 3 of the capacitive ground C. It is provided. Then, the terminal voltages of the resistor 2 and the capacitor 3 are added by the adding circuit 15 and input to the voltage controlled oscillator circuit 100. Further, switches 4 to 7 are provided, the switches 8 and 10 are controlled to open and close by a signal UP, and the switch 9
And 11 are controlled to be opened / closed by a signal DOWN. In addition,
The gain of the voltage controlled oscillator circuit 100 is assumed to be K0.

The operation of the phase locked loop circuit including the loop filter having such a configuration is similar to the operation of the circuit of FIG. 6 described above. The difference in configuration is that the resistance and the capacitance are not connected in series, and the constant current sources 4 and 5 and the switch 8 are
And a point connected to the first charge pump consisting of 9 and 9 and the second charge pump consisting of constant current sources 6 and 7 and switches 10 and 11, respectively, and addition for adding the voltages at the resistance end and the capacitance end. This is the point where the circuit 15 exists.

Therefore, the operational differences are as follows. When the signal UP or DOWN is input, the resistance 2
A rectangular voltage having a voltage value Ipr * R is generated at both ends of, and an integrated voltage having a slope Ipc / C is generated at the terminals of the capacitor 3. These two voltages are added by the adder circuit 15 and added to the voltage controlled oscillator circuit 100. In this case, the natural frequency ωn and the damping rate ξ
And are respectively expressed as follows.

Ωn = {(K0 * Ipc) / (2 * π * C)} ^1/2 (1) ξ = (R * C / 2) * (Ipr / Ipc) * ωn (2) Now, In the phase locked loop shown in FIG. 7, as can be seen by comparing equations (1) to (4), the current value Ip
Is separated into the current values Ipr and Ipc, which increases the degree of freedom of the parameter by one. Therefore, by appropriately selecting the value of Ipr / Ipc in the equation (2), desired values of ωn and ξ can be obtained even for a relatively small value of the product of R * C.

However, even though the value is relatively small, there is no difference in that the resistor must be used. Further, even if a small resistance is used, the current value Ipr must be increased as a cost, which results in an increase in power consumption.

That is, in the conventional phase-locked loop circuit described above, since a resistor is used, a large area in the chip is occupied at the time of integration, and as a result, the cost of the integrated circuit is increased. is there. Further, even if the resistance value is reduced by devising the circuit, there is a drawback that the power consumption increases.

Other phase locked loop circuits are disclosed in Japanese Patent Laid-Open Nos. 63-90213 and 63-9021.
4, JP-A-63-90215 and JP-A-2
However, all of them use resistors, and there is a drawback that the area of the chip becomes large.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a phase locked loop circuit capable of reducing the area of a chip as much as possible and reducing the cost of an integrated circuit. It is to be.

[0023]

A phase-locked loop circuit according to the present invention is a phase-locked loop circuit including voltage-controlled oscillation means for changing and controlling an oscillation frequency of an output according to an applied voltage. Phase comparison means for comparing the phase with the reference input, a reference voltage source for generating at least two kinds of voltages for controlling the change of the phase, and these generated voltages are supplied to the voltage controlled oscillation means according to the phase comparison result. It has a voltage application control means for applying.

[0024]

Function: The phase of the output of the phase locked loop circuit and the phase of the reference input are compared. 2 from the reference voltage source according to the comparison result.
Applying different types of voltage to the voltage controlled oscillator.

[0025]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the operation principle of the phase locked loop circuit according to the present invention, and the same parts as those in FIGS. 4 to 7 are designated by the same reference numerals. In the figure, this circuit includes reference voltage sources 10 and 11, and the voltages generated by the reference voltage sources 10 and 11 are selectively applied to the adder circuit 12 by a switch S. Note that the switch S normally selects the ground level.

In this structure, when the signal UP is input from the phase comparator, the switch 6 is closed and the constant current source 4 causes the current Ip to flow into the capacitor 3. While the current Ip is flowing in, an integrated voltage having a slope Ip / C is generated at the terminal of the capacitor 3. On the other hand, the switch S is closed to the terminal 80 side by the input of the signal UP, and the voltage of the reference voltage source 10 is added to the terminal voltage of the capacitor 3 and output to the output of the adding circuit 12.

When the signal DOWN is input from the phase comparator, the switch 7 is closed and the constant current source 5 supplies the current Ip.
Flows out of the capacity 3. During the period when the current Ip is flowing, an integrated voltage having a slope Ip / C is generated at the terminal of the capacitor 3. On the other hand, the switch S is closed to the terminal 90 side by the input of the signal DOWN, and the voltage of the reference voltage source 11 is added to the terminal voltage of the capacitor 3 and output to the output of the adding circuit 12.

That is, while the signal UP is being input, the positive voltage of the reference voltage source 10 is added by the adder circuit 12 and input to the voltage controlled oscillator 100, and while the signal DOWN is being input, the reference voltage source 11 is input. Negative voltage of addition circuit 12
Are added and input to the voltage controlled oscillator 100. While neither of the signals UP and DOWN is input, the switch S selects the ground level, so that the phase state at that time is maintained.

Here, the voltage values of the reference voltage sources 10 and 11 are the same as the voltage value Ip * R generated across the resistor 2 of the circuit shown in FIG. By doing so, the operation of the circuit of FIG. 1 becomes exactly the same as that of the circuit of FIG.
It becomes a second-order phase locked loop having the characteristics shown by the equations (1) and (2).

A more specific embodiment will be described below.

First, FIG. 2 is a block diagram showing the configuration of the first embodiment of the phase locked loop circuit according to the present invention, and the same portions as those in FIG. 1 are designated by the same reference numerals.

In the figure, the circuit of this embodiment is configured so that the circuit of this embodiment includes an operational amplifier 14. Since the capacitor 3 is connected to the inverting input terminal of the operational amplifier 14, the operational amplifier 14 and the capacitor 3 function as an integrating circuit of the currents of the constant current sources 4 and 5.

Further, the non-inverting input terminal of the operational amplifier 14 has a switch 8 controlled to open / close by a signal UP, a switch 9 controlled to open / close by a signal DOWN, and a signal UP.
, And DOWN are connected to the switch 13 that is closed when neither of them is input. Therefore, the operational amplifier 14 also functions as an adding circuit that adds the generated voltage of the reference voltage sources 10 and 11 to the integrated voltage according to the open / close state of the switches 8, 9 and 13.

That is, when the signal UP is input, the generated voltage of the reference voltage source 10 is added to the integrated voltage, and when the signal DOWN is input, the generated voltage of the reference voltage source 11 is added to the integrated voltage. Add up.

According to this structure, the signal UP or DOWN is input according to the comparison result of the phase comparator, so that the voltage value after the generated voltages of the reference voltage sources 10 and 11 are added is voltage controlled oscillation. It will be input to the circuit 100.

Here, the voltage values of the reference voltage sources 10 and 11 are the same as the voltage value Ip * R generated across the resistor 2 of the circuit shown in FIG. By doing so, the operation of the circuit of this embodiment is exactly the same as that of the circuit of FIG. Therefore, since it is not necessary to provide a resistor, the chip area can be reduced.

Next, FIG. 3 is a block diagram showing the configuration of the second embodiment of the phase locked loop circuit according to the present invention, and the same portions as those in FIG. 1 are designated by the same reference numerals.

In the figure, the circuit of this embodiment is configured to include a capacitor 3 whose one end is grounded. Therefore, the capacitor 3 functions as an integrating circuit for the currents of the constant current sources 4 and 5.

Further, the circuit of this embodiment has the operational amplifier 14
It is configured to include. A switch 8 whose opening and closing is controlled by a signal UP is provided at the inverting input terminal of the operational amplifier 14.
And a switch 9 whose opening and closing is controlled by the signal DOWN,
It is connected to the switch 13 which is in a closed state when neither of the signals UP and DOWN is input. Therefore, the operational amplifier 14 applies the integrated voltage to the reference voltage sources 10, 1 according to the open / closed states of the switches 8, 9 and 13.
It functions as an adder circuit for adding the generated voltage of 1.

That is, when the signal UP is input, the generated voltage of the reference voltage source 10 is added to the integrated voltage, and when the signal DOWN is input, the generated voltage of the reference voltage source 11 is added to the integrated voltage. Add up.

According to this structure, the signal UP or DOWN is input according to the comparison result of the phase comparator, so that the voltage value after the generated voltages of the reference voltage sources 10 and 11 are added is voltage-controlled oscillation. It will be input to the circuit 100.

The voltage values of the reference voltage sources 10 and 11 are the same as the voltage value Ip * R generated across the resistor 2 of the circuit shown in FIG. By doing so, the operation of the circuit of this embodiment is exactly the same as that of the circuit of FIG. Therefore, since it is not necessary to provide a resistor, the chip area can be reduced.

Next, each switch in FIGS. 2 and 3 will be described.

FIG. 4 is a circuit diagram showing an example of the configuration of each switch in FIGS. 2 and 3, and the same parts as those in the drawings are designated by the same reference numerals. In the figure, the switch 6 is a P-type MO
It is an S transistor (hereinafter referred to as PMOSTr), and an inverted signal of the signal UP is input to its gate terminal. Therefore, when the signal UP is output from the phase comparator, the switch 6 is turned on. On the other hand, the switch 7 is an N-type MOS transistor (hereinafter referred to as NMOSTr), and the signal DOWN is input to its gate terminal. Therefore, the signal DOWN from the phase comparator
Is output, the switch 7 is turned on.

The switches 8, 9 and 13 are connected to the PMO.
Each is composed of an STr and an NMOSTr.

Here, focusing on the switch 8, the NMO
The signal UP is input to the STr, and the inverted signal of the signal UP is input to the PMOSTr by the inverter 41. Therefore, when the phase of the input IN is ahead of the phase of the output OUT, the signal UP is output from the phase comparator, the switch 8 is turned on, and the generated voltage of the reference voltage source 10 becomes non-existent in the operational amplifier circuit 14. It will be applied to the inverting terminal.

Focusing on the switch 9, the NMOS
The signal DOWN is input to Tr, and the inverted signal of the signal DOWN is input to the PMOSTr by the inverter 43. Therefore, when the phase of the input IN lags the phase of the output OUT, the phase comparator outputs the signal DOWN.
Is output, the switch 9 is turned on, and the generated voltage of the reference voltage source 11 is applied to the non-inverting terminal of the operational amplifier circuit 14.

Further, the signal UP and the signal DOWN are input to the NOR gate 40, and the output thereof is the NM of the switch 13.
The inverted signal from the inverter 42 is input to the PMOSTr of the switch 13 while being input to the OSTr. Therefore, when the input IN and the output OUT are in phase with each other, the phase comparator outputs the signals UP and DOWN.
None of these are output, and the switch 13 is turned on, and the ground level is applied to the non-inverting terminal of the operational amplifier circuit 14.

According to such a configuration, the voltage value after the generated voltage of the reference voltage sources 10 and 11 is added according to the phase comparison result of the phase comparator, that is, the phase lead or phase lag state, is the voltage controlled oscillator circuit. It is input to 100.

Although the charge pump type phase locked loop circuit has been described above, the present invention is not limited to this and it is obvious that the present invention can be widely applied to the phase locked loop circuit.

[0052]

As described above, according to the present invention, the reference voltage source is provided, and the generated voltage is applied to the voltage controlled oscillator circuit according to the result of the phase comparison between the output of the phase locked loop circuit and the reference input. Therefore, it is not necessary to provide a resistor,
There is an effect that the area of the chip can be reduced and thus the cost of the integrated circuit can be reduced. Further, according to the present invention, since it is not necessary to provide a small resistance, there is an effect that power consumption is not increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing the operating principle of a phase locked loop circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a phase locked loop circuit according to a first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a phase locked loop circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration example of each switch in FIGS. 2 and 3.

FIG. 5 is a block diagram showing a configuration of a general phase locked loop circuit.

FIG. 6 is a block diagram showing a configuration of a conventional phase locked loop circuit.

FIG. 7 is a block diagram showing the configuration of another conventional phase-locked loop circuit.

[Explanation of symbols]

 2 resistance 3 capacitance 4, 5 constant current source 6, 7, 8, 9, 13, S switch 10, 11 reference voltage source 12, 15 adder circuit 14 operational amplifier circuit 100 voltage controlled oscillator circuit 200 loop filter 300 phase comparator

Claims (3)

[Claims] 1. A phase-locked loop circuit including voltage-controlled oscillation means for changing and controlling an oscillation frequency of an output according to an applied voltage, the phase-comparison means comparing a phase between the output and a reference input. A reference voltage source for generating at least two types of voltages for controlling the phase change, and a voltage application control means for applying the generated voltages to the voltage controlled oscillation means according to a phase comparison result. Phase locked loop circuit. 2. The first reference voltage source advances the phase.
And a second voltage for delaying the phase, the voltage application control means applies the first voltage when the phase comparison result indicates a phase delay, and the phase comparison result leads the phase. The phase-locked loop circuit according to claim 1, wherein the second voltage is applied when 3. The first reference voltage source advances the phase.
Voltage and a second voltage for delaying the phase and a third voltage for maintaining the current phase state, and the voltage application control means sets the first voltage to the first voltage when the phase comparison result indicates a phase delay. The second voltage is applied when the phase comparison result indicates a phase advance, and the third voltage is applied when the phase comparison result indicates that there is no phase difference. The phase locked loop circuit according to claim 1, wherein