JPH0878697A - Thin film transistor and method of manufacturing the same - Google Patents

Abstract

PURPOSE: To ensure good characteristic and to prevent failure by shortcircuit or disconnection defect without using an ion implantation process that increases the cost, using a etching method with a good reproducibility and planarising an interlayer insulation film. CONSTITUTION: An activated source region 12 and a drain region 13, a first semiconductor part 11 that has a recessed stepped part between these regions, a second semiconductor part 15 of which the channel region 16 comprises a region where a film is formed on the first semiconductor part 11 and covers the stepped part, a gate insulation film 17 formed on the second semiconductor part 15 and a gate electrode 18 that is flush with the gate insulation film 17 and so arranged as to be self-aligned edge parts of the source region 12 and the drain region 13, are provided. A side of the stepped part of the first semiconductor part 11 is inclined the etching is performed with a good repeatability utilizing the stepped part, the gate electrode 18 is self-aligned adequately and an interlayer insulation film 23 is arranged flat on the surface of the gate insulation film 17 and the gate electrode 18 that are flush in level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, thin film transistors used for switching elements of liquid crystal display devices have been developed.
As a process of manufacturing a stor (hereinafter, simply referred to as a TFT), a self-alignment method, which is advantageous for reducing parasitic capacitance and TFT area, is drawing attention. In the self-alignment method, the self-alignment effect of the gate electrode can minimize the overlap with the source region and the drain region, and can improve the performance and reduce the area. 5 to 8 are
Conventionally known TFT with self-alignment structure
An example of a manufacturing process is shown. As shown in FIG. 5, first, a semiconductor thin film 2 made of intrinsic silicon is formed as a device area on a substrate 1 such as glass. Next, as shown in FIG. 6, after forming the gate insulating film 3 on the entire surface of the semiconductor thin film 2, a metal such as Al is deposited on the gate insulating film 3 and the metal film 4a is patterned by a photolithography technique. Formed to obtain the gate electrode 4. Next, in the step shown in FIG. 7, the gate insulating film 3 is etched using the gate electrode 4 as a mask, and the gate insulating film 3 is etched to a thickness that does not damage the semiconductor thin film 2 by etching. Subsequently, also in FIG.
Ions are implanted into the semiconductor thin film 2 and then activated, and the source region 5 and the drain region 6 are formed by self-aligning the ends 5a and 6a with both ends of the gate electrode 4. Then, in the process of FIG. 8, the interlayer insulating film 7 is formed so as to cover the entire surface including the gate electrode 4, and the source electrode 8 and the drain electrode 9 are formed in the contact holes formed by piercing the interlayer insulating film 7, respectively. By connecting to the source region 5 and the drain region 6, a TFT having a self-conflict structure is manufactured.

[0003]

The following problems are raised in the above TFT manufacturing process by the self-alignment method. One is that since an ion implantation process is required in the manufacturing process, the ion implantation apparatus is expensive and large in size, and annealing by heat treatment after implantation is also indispensable, resulting in a complicated process and a long period of time. In this case, since ion implantation into the semiconductor thin film 2 is performed with the gate insulating film 3 interposed (FIG. 7), it is necessary to secure a high voltage, and as described above, the device is expensive and the process Along with the complication, the manufacturing cost of the TFT is soaring. In addition to this, defects generated at the time of ion implantation still remain after annealing, which deteriorates the TFT performance. Another is that, in the process of FIG. 7, when the gate insulating film 3 is etched, over-etching due to an undercut shape or the like often occurs in the gate insulating film 3 immediately below the gate electrode 4, and etching with good reproducibility is performed. It's difficult. As a result, the leak current of the gate electrode 4 increases in the manufactured TFT, and the characteristics and quality are deteriorated or varied. As a final problem, as shown in FIG. 8, there is a problem that unevenness is generated in the interlayer insulating film 7 due to the step of the underlying surface due to the protrusion of the gate electrode 4, and a short circuit or a disconnection defect easily occurs in the wiring between circuit blocks. There is. Therefore, in view of the above three problems, an object of the present invention is to perform favorable reproducibility etching and planarize an interlayer insulating film without introducing an ion implantation process that causes a cost increase, so that suitable characteristics can be secured. Another object of the present invention is to provide a thin film transistor and a method of manufacturing the thin film transistor, which can take advantage of the self-alignment method by preventing a short circuit and a disconnection defect.

[0004]

In order to achieve the above object, a TFT according to the present invention has a source region and a drain region which are separated from each other, and a concave step portion is provided between these regions. Section, a second semiconductor section provided on the first semiconductor section and covering the step section is a channel region, a gate insulating film provided on the second semiconductor section, and a gate insulating film. And a gate electrode which is provided so as to be flush with the film between the source region and the drain region. In addition, the TF of the present invention
At T, in the stepped portion of the first semiconductor portion, each end portion of the source region and the drain region is inclined so as to be gradually expanded upward, and both ends of the gate electrode are above the inclined end portions. The part may be located. Also, in the method of manufacturing a TFT according to the present invention, a source region and a drain region which are electrically activated in advance and are separated from each other are formed, and a channel region is formed in a concave step portion between both regions, and the channel region is formed thereon. A gate insulating film is formed, and a gate electrode is formed flush with the gate insulating film at a position corresponding to the step portion. Further, according to this manufacturing method, a metal film is deposited on the gate insulating film having a step portion formed by the step portion between the source region and the drain region, and an etching substantially equal to this is deposited on the metal film. A resist film having a speed is applied, the metal film and the resist film are etched, and the metal film is left flat on the step portion of the gate insulating film to form a gate electrode.

[0005]

In the TFT of the present invention, the source region and the drain region of the first semiconductor section are separated from each other, and the second semiconductor section is provided on the first semiconductor section. The gate electrodes corresponding to the first and second semiconductor portions are flush with the gate insulating film and are provided between the source region and the drain region. Therefore, the interlayer insulating film formed thereafter is flattened, which is effective in preventing disconnection and short circuit. In addition, the shape of the stepped portion between the source region and the drain region is formed into an inverted trapezoidal shape in which the side surface of the stepped portion is inclined and gradually expanded upward, so that the channel region adapted to the distance between the source region and the drain region is formed. Gate electrodes obtained and subsequently formed can be provided corresponding to the ends of the source region and the drain region. That is, it is possible to suppress an increase in short circuit and leakage current due to the occurrence of over etching. Further, in the TFT manufacturing method according to the present invention, since the source region and the drain region which are electrically activated and are separated from each other are formed in advance, the ion implantation process is not necessary. A channel region is formed in the concave step portion between the source region and the drain region. By forming the inverted trapezoidal shape by inclining the side surface of the step portion, it is possible to form the channel region and the gate electrode with good reproducibility in a suitable length corresponding to the distance between the source region and the drain region. Further, since the gate electrode is flush with the gate insulating film by the step portion, for example, the interlayer insulating film on the gate electrode can completely cover the gate electrode.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a TFT and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. 1 to 4
Shows an example of a TFT manufacturing process by the self-alignment method of the embodiment. The main part of the structure of the TFT obtained by this process is the first and second semiconductor parts 11,
15, a gate insulating film 17, and a gate electrode 18. The first semiconductor portion 11 is deposited to form a device area. In the first semiconductor portion 11, a source region 12 and a drain region 13 made of electrically activated n-type silicon containing impurities such as phosphorus ions are easily formed, and the source region 12 and the drain region 13 are opposed to each other. The step side surfaces 14a, which are the ends, are inclined and are separated from each other, and a concave step portion 14 is provided therebetween. Further, the second semiconductor section 15 is formed on the first semiconductor section 11, and the channel region 16 is formed in the step section 14. The gate insulating film 17 is formed on the second semiconductor portion 15 and the step portion 14 on the gate insulating film 17 is formed.
The gate electrode 18 is formed at a location corresponding to.

In the manufacturing process, in the step shown in FIG. 1, a first semiconductor portion 1 made of n-type silicon containing, for example, high-concentration impurities is formed on a substrate 10 made of glass or the like.
1 is previously deposited by, for example, a CVD method or a deposition technique, and then a device area is formed by etching.
At this time, the first semiconductor portion 11 is electrically activated such as conductivity, and the source region 12 and the drain region 13 are formed by sloping the step side surfaces 14a, which are the opposite ends, by isotropic etching. They are separated from each other, and a concave step portion 14 is provided between them.

Next, in the process of FIG. 2, the second semiconductor portion 15 made of, for example, intrinsic silicon is formed on the first semiconductor portion 11 formed as shown in FIG. This second semiconductor section 1
5, the step portion 14 provided in the first semiconductor portion 11
The portion formed on the substrate is the channel region 16.

Next, also in FIG. 2, a gate insulating film 17 made of, for example, silicon nitride is formed on the second semiconductor portion 15, and Al is formed on the gate insulating film 17.
Alternatively, a metal film 21 of Cr or the like is patterned after being deposited by sputtering or the like. The gate insulating film 17 and the metal film 21 are also formed with a step portion having substantially the same sectional shape as the step portion 14 of the first semiconductor portion 11.

After depositing the metal film 21, an SOG (Spin On Glass) film 22 is applied by a spin coating method or the like in order to flatten the irregularities formed on the surface. As the SOG film 22, for example, a low concentration silanol compound obtained by diluting Si (OH) ₄ with ethanol or the like is deposited on the metal film 21 by a spin coating method. Then, when the silanol-based compound is heat-treated and dried, SiO ₂ and 2H ₂ O are generated by a chemical reaction, and the SOG film 22 made of a silicon oxide film (SiO ₂ ) can be formed. At this time, the SOG film 22 preferably has an etching rate close to that of the metal film 21.

Next, in the step shown in FIG.
The G film 22 and the underlying metal film 21 are etched back to form the SOG film 2
2 is removed, and the metal film 21 is left and removed only in the step portion of the gate insulating film 17 until the surface of the gate insulating film 17 becomes flat and flat. The metal film 21 left on the step portion of the gate insulating film 17 is formed as the gate electrode 18. At this time, the gate electrode 18 has the inclined surface 18a,
18a is the source region 12 in the first semiconductor portion 11
Also, the structure substantially corresponds to the inclined end of the drain region 13.

In the process shown in FIG. 4, the gate insulating film 1
7 and the surface of the gate electrode 18 are flattened, and even if the interlayer insulating film 23 is formed thereon, the surface of the interlayer insulating film 23 is also flattened, so that the gate electrode 18 etc. Therefore, it is possible to prevent disconnection of inter-circuit wiring of a device in which a large number of TFTs are arranged in a matrix. Then, the source electrode 24 and the drain electrode 25 are formed in the contact holes formed by piercing the holes, and the source electrode 24 and the drain electrode 25 are connected to the corresponding source region 12 and drain region 13, respectively, and the manufacture of the TFT is completed.

[0013]

As described above, the T according to the present invention is
According to FT, short-circuiting and increase in leak current due to overetching of the gate electrode due to etching with good reproducibility can be suppressed, self-alignment with the ends of the source region and drain region can be achieved, and the gate insulating film can be formed. Since they are formed so as to be flush with each other, flattening of the interlayer insulating film is effective in preventing disconnection and the like, and suitable characteristics without variation can be obtained. Further, in the method of manufacturing a TFT according to the present invention, a source region and a drain region, which have been electrically activated in advance in the semiconductor portion, can be easily formed by a technique that replaces the ion implantation technique. The increase in the number of processes and capital investment can be minimized, and the stepped portion between the source region and the drain region is formed in an inverted trapezoidal shape, so that a suitable length matching the distance between the source region and the drain region can be obtained. In addition to forming a channel region, the reproducibility of etching can be improved and the gate electrode can be accurately self-aligned to take advantage of the self-alignment structure.

[Brief description of drawings]

FIG. 1 is a sectional view showing a process of an embodiment of a method for manufacturing a TFT according to the present invention.

FIG. 2 is a sectional view showing a TFT manufacturing process of the same example.

FIG. 3 is a sectional view showing a TFT manufacturing process of the same example.

FIG. 4 is a sectional view showing a TFT manufacturing process of the same example.

FIG. 5 is a cross-sectional view showing the steps of a conventional method for manufacturing a TFT.

FIG. 6 is a sectional view showing a conventional TFT manufacturing process.

FIG. 7 is a sectional view showing a TFT manufacturing process of a conventional example.

FIG. 8 is a sectional view showing a TFT manufacturing process of a conventional example.

[Explanation of symbols]

 Reference Signs List 10 substrate 11 first semiconductor portion 12 source region 13 drain region 14 concave step portion 14a inclined step side surface 15 second semiconductor portion 16 channel region 17 gate insulating film 18 source electrode 21 metal film 22 SOG film 23 interlayer insulating film 24 source electrode 25 drain electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9056-4M 627 A

Claims (5)

[Claims] 1. A first semiconductor portion having a source region and a drain region which are separated from each other, and a concave step portion is provided between the both regions, and the step portion provided on the first semiconductor portion. A second semiconductor portion whose region is a channel region, a gate insulating film provided on the second semiconductor portion, and a gate insulating film that is flush with the source region and the drain region. A thin film transistor comprising: a provided gate electrode. 2. In the stepped portion of the first semiconductor portion, each end portion of the source region and the drain region is inclined so as to gradually expand upward, and the gate electrode is provided above each inclined end portion. 2. The thin film transistor according to claim 1, wherein both ends of the thin film transistor are located. 3. The thin film transistor according to claim 1, wherein an interlayer insulating film is provided flat on the surfaces of the gate insulating film and the gate electrode which are flush with each other. 4. A source region and a drain region, which are electrically activated in advance and separated from each other, are formed, a channel region is formed in a concave step portion between both regions, and a gate insulating film is formed thereon. And forming a gate electrode flush with the gate insulating film on the gate insulating film at a position corresponding to the step portion. 5. A metal film is deposited on the gate insulating film having a step portion formed by the step portion between the source region and the drain region, and a resist film having an etching rate substantially equal to the metal film is deposited on the metal film. 5. The thin film transistor according to claim 4, wherein the gate electrode is formed by applying a film, etching the metal film and the resist film, and leaving the metal film flat in the step portion of the gate insulating film. Production method.