JPH086800A - Data processor and microprocessor - Google Patents

Abstract

PURPOSE:To enable interruption synchronized with multiplexed processors by using an external bus and processors with different clocks of internal operation in a computer system. CONSTITUTION:This processor is a data processor provided with plural bus 28-connected processors 21a, 21b, and each of the processors 21a, 21b is provided with a communication circuit 23 which notifies an internal operating state mutually between another processor and holds an interruption request from the outside, a processing stopping circuit 25 which stops the internal processing of its own processor transiently, an output stopping circuit 26 which holds the processed result of its own processor and stops output to the bus 28 transiently, and a monitoring circuit 24a which monitors the internal operation of its own processor and starts up the output stopping circuit 25 and a processing stopping circuit 26a based on the notified content of the communication circuit 23, and plural processors 21a, 21b performs the processing of the same program simultaneously at an instruction level, and a monitoring circuit 24 performs interruptive processing synchronized between the plural processors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and a data processing device for executing highly reliable data processing by connecting a plurality of microprocessors to a bus and processing the same program at the same time at the instruction level. Regarding the microprocessor used.

[0002]

2. Description of the Related Art By making the hardware of a data processing device redundant, the reliability of the entire system can be improved. One of the technologies among them is a method of providing processor redundancy by multiplexing processors. FRC is the technology for improving the system reliability by this method.
(Functional Redundancy Checking) or FRM (Fu
nctional Redundancy Monitoring). That is, the FRM is composed of a plurality of microprocessors that execute the same program synchronized at the clock level and a comparator that compares and verifies the processing results of these microprocessors.

Since the multiplexed processors execute the same program in synchronization at the clock level as described above, the same processing result will appear on the bus in synchronization if there is no abnormality in the processor. At this time, the processing result appearing on the bus is compared and monitored for each bit by the comparator, and when the processing result of the processor is different, the processor returns to the last normal operation and restarts the processing. And if it still does not give a normal result, it is reported as a permanent failure. By performing such an operation, the reliability of the system can be improved.

FIG. 3 shows the basic circuit configuration of the FRM. The internal arithmetic unit 11 operating with the same clock CK is shown in FIG.
It shows a dual computer system with processors a and 11b and processors 13a and 13b having bus interfaces 12a and 12b. Since the same programs are synchronously executed by the internal arithmetic units 11a and 11b, the processing result appears synchronously on the external bus 14, and the comparator 15 compares and verifies them.

However, as the speed of the processors 13a and 13b increases, the operating clock of the external bus 14 and the processor
It is possible that the operation clocks inside 13a and 13b may become out of synchronization. That is, it is ideal to increase the speed of the entire processor from the viewpoint of improving the efficiency of data processing, but in consideration of other external devices connected to the external bus 14, the external bus 14
In some cases, the speed of the external bus 14 and the processors 13a and 13b cannot be increased.
The operation clocks of the internal arithmetic units 11a and 11b may be speeded up separately.

When such a processor is made redundant and used in a computer system, a processing result can always be obtained on a bus between a plurality of multiplexed processors if the ratio of the clocks in the processor and the external bus is an integral multiple. To be If this is not the case, depending on the internal operation of the plurality of processors, even if the same program is started to be processed synchronously, the timing of appearing on the resulting bus may be shifted. In such a case, the comparison and verification of the processing results are performed by synchronizing the processing results with the comparator provided on the bus.

FIG. 4 shows clocks CK1 and CK2 having different internal arithmetic units 11a and 11b and bus interfaces 12a and 12b.
Shows a computer system in which processors operating asynchronously are duplicated. Dual processor here
13a and 13b execute the same program at the instruction level. Bus interfaces 12a, 12b and internal calculator 11
Since a and 11b are asynchronous with each other, the processing result may appear on the external bus 14 at different timings. However, after synchronizing the processing result with the synchronization circuit 16a, the synchronization circuit 16a
The processing result is compared and verified by the comparator 16 equivalent to the comparator 15 including 16a.

With such a configuration, the processor 13
When an external interrupt is issued to a and 13b, the external bus 14 and the processors 13a and 13b have the same clock C.
In a redundant system in which K is completely synchronized, interrupts to the multiplexed processors 13a and 13b are synchronously performed for the same instruction.

However, in a redundant system having an internal processor which operates with a clock different from the bus clock, when interrupting each of the multiplexed processors based on the processing result appearing on the bus, Because the internal operation of a processor may differ from processor to processor due to a slight deviation in the operating characteristics of each individual, an external interrupt does not occur in each processor at the same timing and with the same instruction. It is possible that different interrupt operations will be performed for each processor.

FIG. 5 exemplifies such a state.
Here, it is assumed that the same program is executed by the redundant computer system including the duplicated processors 13a and 13b similarly to the circuit configuration of FIG. 4, the same portions are denoted by the same reference numerals, and the description of the configuration is omitted. . As shown in the figure,
The program is executed in the order of instruction 0, instruction 1, instruction 2, instruction 3, instruction 4, and instruction 5. At the timing shown in the figure, the processing result of the instruction 0 is output from the processors 13a and 13b onto the external bus 14, respectively, and is compared and verified by the comparator 16 having the synchronization circuit 16a. Therefore, when viewed from the outside of the processors 13a and 13b, the processors 13a and 13b appear to be operating in synchronization. However, the instructions actually executed by the processors 13a and 13b are different due to the deviation of the synchronization between the bus interfaces 12a and 12b and the internal operation. If an interrupt is issued to the processors 13a and 13b at this time, the processor
Different instructions are interrupted for each of 13a and 13b, resulting in different processing.

[0011]

As described above, when a processor having different buses and internal operation clocks is used in an electronic computer system in which the processors are made redundant, interrupt processing synchronized with the multiplexed processors occurs. I can't let you do it.

The present invention has been made in view of the above circumstances, and an object of the present invention is to use a processor that is multiplexed by using a processor having a different external bus and internal operation clock in a redundant computer system. There is provided a data processing device capable of realizing a synchronized interrupt to a data processing device and a microprocessor used in the data processing device.

[0013]

That is, the present invention is a data processing device having a plurality of processors connected to a bus, and a notification circuit for notifying other processors of an internal operating state, and its own processor. An output stop circuit that holds the processing result of (1) and temporarily stops the output to the bus, a process stop circuit that temporarily stops the internal processing of the processor itself, and a hold circuit that holds an interrupt instruction from the outside. An individual processor is provided with a monitoring circuit that monitors the internal operation of its own processor and activates the output stop circuit and the process stop circuit based on the notification content obtained by the notification circuit,
The plurality of processors simultaneously process the same program at the instruction level, and the monitoring circuit performs interrupt processing synchronized between the plurality of processors according to the contents held in the holding circuit or the interrupt acceptance instruction arranged in advance in the program. This is done so that interrupt processing synchronized with a plurality of processors is performed.

[0014]

With the above-described structure, even in a data processing device in which processors having different clocks for internal operation and external buses are multiplexed, the processors can be reliably synchronized and highly reliable operation can be achieved. Can be kept running.

[0015]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the basic circuit configuration thereof, and here it is assumed that a redundant system having dual processors is assumed. In the figure, 21a is the primary processor and 21b
Is the secondary processor and these processors 21
a and 21b are arithmetic units 22a and 22b for executing arithmetic operations according to instructions of the same program, communication circuits 23a and 23b for communicating an internal operation state between mutual processors and holding an interrupt to the own processor, Monitoring circuits 24a, 24b for monitoring the internal operation of each processor obtained by the communication circuits 23a, 23b and controlling the processing stop circuits 25a, 25b and output stop circuits 26a, 26b to be described later to activate them, twenty four
Processing stop circuits 25a and 25b for temporarily stopping the internal operation of the self processor by controlling a and 24b, and the monitoring circuit
An output stop circuit 26a, 26b for temporarily storing the processing result of its own processor under the control of 24a, 24b and temporarily stopping output to the external bus 28, and a bus interface for transmitting / receiving data to / from the external bus 28. -Has faces 27a and 27b.

A communication bus 29 connects the two communication circuits 23a and 23b. Bus interfaces 27a, 27 of the primary processor 21a and the secondary processor 21b
The contents of the processing result of the operation output from b to the external bus 28 are compared and verified by the synchronization circuit 30a in the comparator 30 after being synchronized.

In the above-mentioned structure, the IN as an instruction for accepting an interrupt request is sent to the primary processor 21a and the secondary processor 21b used in this system.
It has a TOK command. When an instruction other than the INTOK instruction is executed, the processor does not accept an interrupt request from the outside, and when the INTOK instruction is executed, the communication circuits 23a and 23b receive information of the interrupt request from the outside. Hold.

The above-mentioned processors 21a and 21b are referred to as primary and secondary, respectively, but these are unambiguous and their constituent models, programs to be executed, etc. are all the same, and neither is weighted. .
Primary processor 21a or secondary processor
When any of the 21b recognizes the INTOK instruction, the monitoring circuit 24a (24b) determines whether or not an interrupt is issued to its own processor, and whether or not the communication circuit 23a (23b) holds information on the interrupt request. Check by

The communication circuit 23a (23b) holds information on an interrupt request to the processor 21a (21b) from the outside, and transmits this interrupt request information to the monitoring circuit 24a (24b). Unless an external interrupt is applied to the processor 21a (21b), the program execution is continued as it is. If an interrupt occurs, the processor 21a (21b) recognizes the INTOK instruction and checks the synchronization of the internal operating states of the duplicated processors 21a and 21b.

That is, the processor 21a (21b) that recognizes the INTOK instruction is a duplicated processor of the other party.
21b (21a) recognition Information of the command being executed is communicated to the communication circuit.
Obtained using 23a (23b). Next, based on the command information obtained there, the monitoring circuit 24a (24b) is used to verify whether the command information that the other party has recognized and executed is the same.

If the duplicated processors 21a and 21b execute the same INTOK instruction at the same time, it means that the two processors are synchronized at that time, so that the program continues to be executed and interrupt processing is started.

If different instructions are being executed,
Synchronization processing is performed by the synchronization circuit 30a. Processor
The synchronization processing of 21a and 21b is performed in the following procedure. That is, first, when a synchronization deviation of instruction execution is detected, the monitoring circuit
24a (24b) is used to compare the internal states to check which operation of the primary processor 21a and the secondary processor 21b is delayed or advanced. The processor 21a (21b), which has preceded the operation, executes the program by the communication circuit 23a (23b) by the processing stop circuit 25a (25
b), the output of the processing result to the external bus 28 is stopped using the output stop circuit 26a (26b), and the other processor 21b (21a) waits for the execution of the program to catch up. . This is the communication circuit 23a (23b)
The monitoring circuit 24a (24b) monitors the information of the operating state obtained by the above.

Such synchronization detection is performed every time the operating processor 21b (21a) executes the INTOK instruction, and the monitoring circuit 24a (24b) causes the processor 21b to operate.
The internal state of (21a) is checked, and the process is repeated until the internal states become equal.

When the internal operation of the duplicated processor 21a (21b) is synchronized, the monitoring circuit 24a (24b)
The own processor 21a using the processing stop circuit 25a (25b)
Restart the internal operation of (21b) and stop the output
The output of the processing result to the external bus 28 is restarted using 26a and 26b.

The monitoring circuits 24a and 24b are the communication circuit 23.
The processor 21a, 21b is caused to execute the processing for the interrupt request accepted by a, 23b. As a result, the redundant processors 21a and 21b can perform synchronized interrupt processing.

In the above embodiment, the external communication is directly received by the communication circuits 23a and 23b, and the synchronization on the external bus 28 is performed by the synchronization circuit 30a in the comparator 30. The control may be provided before the communication circuits 23a and 23b, and the external bus 28 may be configured to perform only comparative verification. Hereinafter, this will be described with reference to FIG. 2 as another configuration example of this embodiment.

FIG. 2 shows the basic circuit configuration. Here, it is assumed that the redundant system in which the processors are duplicated is assumed in the same manner as in FIG. 1 above, and its schematic configuration is similar to that shown in FIG. 1 above. To do.

The communication circuits 23a and 23b are connected to the synchronization control circuit 31 by the communication buses 32a and 32b, respectively. The synchronization control circuit 31 receives the internal operation states of the processors 21a and 21b from the communication circuits 23a and 23b and determines the synchronization state thereof, while accepting an interrupt request from the outside.
This is held to notify the communication circuits 23a and 23b that there is an interrupt request.

The processing results output from the bus interfaces 27a and 27b of the processors 21a and 21b are compared and verified by the comparator 33 on the external bus 28 as they are.

In the configuration as described above, the primary processor 21a and the secondary processor 21b always use the communication circuits 23a and 23b to control the internal operation state of the synchronous control circuit 31.
Is being sent to.

When an external interrupt request is issued to the processors 21a and 21b, the request is accepted and held by the synchronous control circuit 31. The synchronization control circuit 31 is a communication circuit.
The synchronization state is determined using the internal operation states of the processors 21a and 21b obtained from 23a and 23b.

This is performed by counting the number of times of execution of a specific instruction such as a branch instruction in a program in each of the processors 21a and 21b and performing it according to the count value.

When it is determined that the duplicated processors 21a and 21b are not operating in synchronization, the synchronization control circuit
A signal 31 determines whether one of the processors 21a and 21b precedes execution of the instruction from the internal state of the processor 21a and 21b, and causes the preceding processor 21a (21b) to start the synchronization operation. Is output.

The monitoring circuit 24a (24b) on the processor 21a (21b) side, which receives this signal by the communication circuit 23a (23b),
The process stop circuit 25a (25b) is used to temporarily stop the execution of the program, and the output stop circuits 26a and 26b temporarily stop the output of the processing result to the external bus 28.

Thus, while the execution of the program and the output of the processing result to the external bus 28 are temporarily stopped, the processor 21b (21a) on the side where the execution of the program is delayed continues the execution of the program. The synchronous control circuit 31 waits until the internal state of the processor 21b (21a) that continues executing the program is obtained by the communication circuit 23b (23a) and its operation catches up with the preceding processor 21a (21b). Then, when the operation of the sending processor 21b (21a) catches up with the operation of the preceding processor 21a (21b) and the internal operations of the duplicated processors 21a, 21b are synchronized, the synchronization is achieved. The control circuit 31 outputs a signal for canceling the temporary stop state to the processor 21a (21b) on the side on which the operation was preceded. This signal is sent to the communication circuit 23a
Monitoring circuit on the processor 21a (21b) side received by (23b)
24a (24b) releases the temporary stop state of the processing stop circuit 25a (25b) and the output stop circuit 26a (26b) to start the execution of the program and the output of the processing result to the external bus 28.

The interrupt request held in the synchronous control circuit 31 at this time is notified to the communication circuits 23a and 23b of the processors 21a and 21b, and the actual interrupt processing is started.

As described above, the synchronous interrupts can be issued by the duplicated processors 21a, 21b, and the comparator 33 for comparing and verifying the processing results of the processors 21a, 21b on the external bus 28. Since it is not necessary to perform synchronization in, the configuration can be simplified.

[0038]

As described in detail above, according to the present invention, even in a data processing device in which processors having different clocks for internal operation and external buses are multiplexed, the synchronization between the processors is ensured and reliability is improved. It is possible to maintain high performance of execution.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing another circuit configuration example according to the embodiment.

FIG. 3 is a block diagram showing a basic circuit configuration of a general FRM.

FIG. 4 is a block diagram showing a basic circuit configuration of a general FRM.

FIG. 5 is a diagram exemplifying a program execution state by a general FRM.

[Explanation of symbols]

11a, 11b ... Internal arithmetic unit, 12a, 12b, 27a, 27b ... Bus interface, 13a, 13b ... Processor, 14, 28
... external bus, 15, 16, 30, 33 ... comparator, 16a, 30a ... synchronization circuit, 21a ... primary processor, 21b ... secondary processor, 22a, 22b ... arithmetic unit, 23a, 23b ... communication circuit, 24a, 24b ... monitoring circuit, 25a, 25b ... processing stop circuit, 26a, 26b ... output stop circuit, 29, 32a, 32b ... communication bus, 31 ... synchronous control circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G06F 15/16 470 J

Claims (8)

[Claims] 1. A data processing device having a plurality of processors connected to a bus, the notification means for mutually notifying an internal operation state to another processor, and holding the processing result of its own processor, said bus Output means for temporarily stopping output to the processor, processing stop means for temporarily stopping the internal processing of the processor itself, holding means for holding an interrupt instruction from the outside, and monitoring the internal operation of the processor itself. A data processing device, wherein each processor comprises the output stopping means and a monitoring means for activating the processing stopping means based on the contents of the notification obtained by the notifying means. 2. The data processing apparatus according to claim 1, wherein the plurality of processors simultaneously process the same program at an instruction level, and the monitoring means synchronizes internal operations among the plurality of processors. 3. The plurality of processors simultaneously process the same program at an instruction level, and the monitoring means synchronizes internal operations among the plurality of processors by counting the number of executions of a specific instruction in the program. The data processing device according to claim 1 or 2. 4. The plurality of processors simultaneously process the same program at an instruction level, and the monitoring means synchronizes the internal operation among the plurality of processors according to the contents held in the holding means, thereby synchronizing interrupts. The data processing device according to claim 1, wherein the data processing device performs processing. 5. The plurality of processors simultaneously process the same program at the instruction level, and the monitoring means synchronizes the internal operation among the plurality of processors based on an interrupt acceptance instruction previously arranged in the program. 3. The data processing device according to claim 1, wherein the interrupt processing is performed in synchronism with. 6. A microprocessor for simultaneously processing the same program as another processor connected to the bus at the instruction level, and a notification means for notifying the other processor of an internal operating state, and An output stopping means for holding the processing result and temporarily stopping the output to the bus, a processing stopping means for temporarily stopping the internal processing of the own processor, and a holding means for holding an interrupt instruction from the outside, A microprocessor comprising: a monitoring means for monitoring the internal operation of the processor itself and activating the output stopping means and the processing stopping means based on the output obtained by the notifying means. 7. The microprocessor according to claim 6, wherein the monitoring means synchronizes an internal operation with another processor by counting the number of executions of a specific instruction in the program. 8. The microprocessor according to claim 6, wherein the monitoring means performs interrupt processing in synchronization by synchronizing the internal operation with another processor.