JPH0863459A - Arithmetic processing method and arithmetic processing device - Google Patents

Abstract

(57) [Summary] [Object] The present invention is suitable for use in the case where it is necessary to perform a large amount of arithmetic processing at a high speed. The present invention relates to an arithmetic processing method and an arithmetic processing apparatus for performing a summation operation, a summation operation, etc. on predetermined vector data by using VU capable of simultaneously executing the following, and a situation in which a subsequent instruction waits due to a convergence operation without increasing the physical quantity. The purpose is to solve the problem and to realize a high-speed vector processing. [Structure] VU for partial operation on predetermined vector data
After being executed by the CPU 2, the CPU 1 executes the convergence operation for the partial calculation result by the VU 2.

Description

Detailed Description of the Invention

(Table of Contents) Industrial Application Conventional Technology (FIGS. 11 and 12) Problem to be Solved by the Invention (FIGS. 11 and 12) Means for Solving the Problem (FIG. 1) Operation (FIG. 1) ) Example (FIGS. 2-10) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing method and an arithmetic processing device suitable for use in the case where it is necessary to perform a large amount of arithmetic processing at high speed, and more particularly to a central processing unit (CP).
U) and a vector processing unit (V) capable of simultaneously executing a plurality of calculations in response to a vector calculation instruction from the central processing unit.
U) and an arithmetic processing method and an arithmetic processing device for performing arithmetic processing (for example, total sum arithmetic, total product arithmetic etc.) on predetermined vector data.

[0003]

2. Description of the Related Art In recent years, in an information processing apparatus that needs to perform a large amount of arithmetic processing at high speed, a central processing unit [hereinafter referred to as CP
In addition to U (Central Processor Unit), a vector processing unit [hereinafter also referred to as VU (Vector Unit)] is provided, and a vector operation instruction is given from the CPU to this VU Performs arithmetic processing on vector data.

As this VU, there is a VU configured as shown in FIG. 11 or 12, for example. 11 and 12 each show an addition processing system for performing a summation processing, and four arithmetic units for addition are provided, and four addition processing (parallelism degree 4) can be performed at the same time. It has become so. In the VU 30A shown in FIG. 11, four arithmetic units 31-1 to 31-4 for performing addition,
Registers 32-1 to 32-4 that temporarily store the calculation results from the arithmetic units 31-1 to 31-4 and a selector 33 that performs a switching function to be described later on the input side of the arithmetic unit 31-1.
Is provided.

Each of the arithmetic units 31-1 to 31-4 has a configuration shown in FIG.
As shown in FIG.
+ 1st, 4i + 2nd, 4i + 3rd, 4i + 4th (i = 0 to n) data is sequentially input, and partial sums S1 to
S4 is calculated. That is, in each of the arithmetic units 31-1 to 31-4, the registers 32-1 to 32-4 are provided.
The result of addition up to the previous time once stored in [4i-
Result of addition up to the 3rd, 4i−2nd, 4i−1th, and 4ith data].
By repeating the process of adding the 4i + 2nd, 4i + 3rd, and 4i + 4th data, the partial sum S1 to
S4 is calculated.

At this time, the selector 33 provided on the input side of the arithmetic unit 31-1 is switched to sequentially input the 4i + 1th data of the vector data. Partial sum S by each computing unit 31-1 to 31-4
When the arithmetic processing of 1 to S4 is completed, the arithmetic unit 31-
By 1, the convergence operation for adding these partial sums S1 to S4 is executed.

That is, in the first cycle, the selector 33
By selecting the partial sum S2 from the arithmetic unit 31-2, the partial sum S2 and the partial sum S1 by the own arithmetic unit 31-1 stored in the register 32-1 are calculated by the arithmetic unit 31-1.
Add by. In the second cycle, the selector 33 selects the partial sum S3 from the arithmetic unit 31-3,
The partial sum S3 and the partial sum S1 + S2 stored in the register 32-1 are added by the calculator 31-1.

Then, in the third cycle, the selector 33
By selecting the partial sum S4 from the arithmetic unit 31-4 by means of this, the partial sum S4 and the partial sum S1 + S2 + S3 stored in the register 32-1 are added by the arithmetic unit 31-1, and the final sum, that is, the total sum S = S1 + S2 + S3 + S4 is calculated, and the sum S is notified to the CPU. Also, FIG.
The VU 30B shown in FIG. 2 includes four computing units 31-1 to 31-4 and registers 32-1 to 32-4 similar to those described above with reference to FIG. 11, and computing units 31-1 to 31-31.
4 dedicated arithmetic operation unit 34 for adding the partial sums S1 to S4, a register 35 for temporarily storing the operation result from this arithmetic unit 34, and a switching function to be described later on the input side of the arithmetic unit 34 One selector 36A, 36
B is provided.

The operation units 31-1 to 31-4 shown in FIG.
The partial sums S1 to S4 are calculated in exactly the same manner as described above, but in the VU 30B shown in FIG. 12, the convergence operation for adding these partial sums S1 to S4 is
It is executed by the arithmetic unit 34 for exclusive use of the convergence operation and the register 35 instead of the arithmetic unit 31-1. That is, in the first cycle, the selector 36A selects the partial sum S1 from the arithmetic unit 31-1, and the selector 36B selects the partial sum S2 from the arithmetic unit 31-2, whereby the partial sum S1. And S2 are added by the arithmetic unit 34 dedicated to the convergence operation.

In the second cycle, the selector 36A selects the partial sum S1 + S2 of the register 34, and
The partial sum S3 from the calculator 31-3 by the selector 36B
By selecting, the partial sum S3 and the partial sum S1 + S2 from the register 35 are added by the convergence operation dedicated arithmetic unit 34. Then, in the third cycle, the selector 36A selects the partial sum S1 + S2 + S3 of the register 34, and the selector 36B selects the partial sum S4 from the arithmetic unit 31-4, whereby the partial sum S4 and the register 35 are selected.
And the partial sum S1 + S2 + S3 from the above are added by the operation unit dedicated to the convergence operation 34, and the final sum, that is, the total sum S = S1 + S2 +
S3 + S4 is calculated, and the sum S thereof is notified to the CPU.

The VU described above with reference to FIGS.
30A and 30B describe the case where the total sum calculation process is performed, but the total product calculation process can be performed in exactly the same manner.

[0012]

By the way, in a vector processing section for simultaneously performing a plurality of operations, it is necessary to calculate a partial sum and then perform a converging operation of further adding all the partial sums. Therefore, in the vector processing unit 30A described above with reference to FIG. 11, the converging operation is performed by the arithmetic unit 31-1. However, in the vector processing unit 30A, execution of the next arithmetic instruction is waited until the converging operation ends. become. Since this convergence operation normally requires several tens of τ, waiting for the execution of the next arithmetic instruction during that time is a major factor in the deterioration of the vector processing performance.

Further, in the vector processing unit 30B described above with reference to FIG. 12, the convergence operation dedicated arithmetic unit 34 is provided so that the convergence operation is not shown. As a result, unlike the vector processing unit 30A shown in FIG. 11, the next operation instruction does not have to wait for the convergence operation, but since the operation unit 34 and the register 35 dedicated to the convergence operation are required, the physical quantity is increased. Is increased, which is not preferable.

The present invention was devised in view of such a problem, and solves the situation that the subsequent instruction waits due to the convergence operation without increasing the physical quantity and realizes the speedup of vector processing. It is an object to provide a processing method and an arithmetic processing device.

[0015]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1 is a central processing unit (CP).
U) and 2 are vector processing units (V) that can execute a plurality of operations at the same time by receiving a vector operation instruction from the central processing unit 1.
U), these central processing unit 1 and vector processing unit 2
An arithmetic processing unit is constituted by and.

In the present invention, the vector processing section 2 is configured to perform the arithmetic processing on the predetermined vector data.
The central processing unit 1 executes a partial operation on predetermined vector data, and the central processing unit 1 executes a convergence operation on the result of the partial operation by the vector processing unit 2 (claim 1,
5). At this time, when the arithmetic processing for the predetermined vector data is the total sum arithmetic processing, the vector processing unit 2 executes the partial arithmetic for obtaining the partial sum of the predetermined vector data, and the central processing unit 1 causes the partial sum by the vector processing unit 2 to be executed. A convergence operation of adding is executed (claims 2 and 6).

Also, when the arithmetic processing for the predetermined vector data is the total product arithmetic processing, similarly, the vector processing unit 2 executes the partial arithmetic for obtaining the partial product of the predetermined vector data, and the central processing unit 1 A convergence operation for multiplying the partial products by the vector processing unit 2 is executed (claims 3 and 7).
The vector processing unit 2 is provided with a register for storing a partial calculation result, and a partial calculation end signal output unit that outputs a partial calculation end signal to the central processing unit 1 when all the partial calculation by the vector processing unit 2 is completed is provided with a vector processing unit. In addition to the unit 2, the central processing unit 1 may be configured to execute a convergence operation for the partial operation result stored in the register when receiving the partial operation end signal from the partial operation end signal output unit (claim). Items 4, 8).

At this time, the partial operation end signal output unit stores the vector length of the vector data (which is transmitted from the central processing unit 1 together with the vector data and the vector operation instruction) with the vector length register and the partial operation processing by 1. A subtraction unit that subtracts the degree of parallelism of the vector processing unit 2 (the number of partial operation processes simultaneously performed in one cycle) from the value stored in the vector length register every cycle, and stores it again in the vector length register, and this subtraction unit And a comparator for outputting a partial operation end signal when the subtraction result becomes 0 or less (claim 9).

Further, it is provided with an arithmetic queue for storing arithmetic instructions from the central processing unit 1, and the central processing unit 1 outputs the vector arithmetic instruction to the vector processing unit 2 and at the same time, the vector processing unit 2 registers in the arithmetic queue. When the instruction to execute the convergence operation for the stored partial operation result is stored and the partial operation end signal from the partial operation end signal output unit is received, according to the instruction stored in the operation queue,
You may comprise so that a convergence operation may be performed with respect to the partial calculation result stored in the register (Claim 10).

[0020]

In the arithmetic processing method and the arithmetic processing apparatus of the present invention described above with reference to FIG. 1, when performing arithmetic processing such as total sum arithmetic processing and total product arithmetic processing on predetermined vector data, partial arithmetic (partial sum arithmetic) on predetermined vector data is performed. , Partial product calculation) by the vector processing unit 2 as usual, and then the central processing unit 1 executes a convergence operation (addition of partial sums, multiplication of partial products) for the partial calculation result by the vector processing unit 2.

Therefore, in the vector processing unit 2, subsequent vector operation instructions are not made to wait by the convergence operation, and it is not necessary to separately provide the vector processing unit 2 with an arithmetic unit dedicated to the convergence operation (claims 1 to 3). , 5
~ 7). When all the partial calculations are completed in the vector processing unit 2 and the partial calculation results are stored in the register, the partial calculation end signal output unit of the vector processing unit 2 outputs the partial calculation end signal. When the central processing unit 1 receives the partial operation end signal, the central processing unit 1 executes the convergence operation for the partial operation result stored in the register (claims 4 and 8).

At this time, in the partial calculation end signal output section of the vector processing section 2, the vector length of the vector data notified from the central processing section 1 is stored in advance in the vector length register, and the partial calculation processing is performed for one cycle. For each time, the subtraction unit subtracts the parallelism of the vector processing unit 2 from the value of the vector length register. Then, when the subtraction result becomes 0 or less, it can be determined that the partial operation processing for all the vector data has been completed, and a partial operation end signal is output from the comparison section (claim 9).

Further, the central processing unit 1 issues a vector operation instruction to the vector processing unit 2, and at the same time, inputs an instruction to execute a convergence operation for the partial operation result stored in the register into the operation queue. As a result, on the side of the central processing unit 1, the vector operation instruction is released and controlled, and other operation processing can be continued (claim 10).

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the overall configuration of an arithmetic processing unit as an embodiment of the present invention. In FIG.
Reference numeral 1 is a central processing unit (hereinafter referred to as CPU), and 2 is a vector processing unit (hereinafter referred to as VU) capable of receiving a vector calculation instruction from the CPU 1 and simultaneously executing a plurality of calculations.

The CPU 1 is configured as described below with reference to FIG. 4 and the control unit 3 that operates according to the flowchart described later in FIG. 7 to control the CPU 1.
The calculation processing unit 4 that operates according to the flow chart described later is included. Similarly, the VU 2 includes a control unit 5 that operates according to a flowchart described below with reference to FIG. 9 to control the VU 2, and an arithmetic processing unit 6 that is configured as described below according to FIG. 3 and operates according to a flowchart described below with reference to FIG. It is configured to include.

Reference numeral 7 denotes a partial sum end signal output unit (partial operation end signal output unit) provided in the operation processing unit 6 of the VU2. The partial sum end signal output unit 7 completes all partial sum operations by the VU2. Then, a partial sum end signal is output to the CPU 1 to notify the CPU 1 that the VU 2 has obtained all the partial sums, and this embodiment is configured as described later with reference to FIG.

Further, 8-1 to 8-4 are VU2, respectively.
The partial sum register for temporarily storing the partial sums S1 to S4 calculated as will be described later, 9 is an operation queue,
The operation queue 9 stores the operation command from the CPU 1. When the CPU 1 outputs the vector operation command to the VU 2, the CPU 1 outputs the partial sum stored in the partial sum registers 8-1 to 8-4 from the VU 2 at the same time. An addition instruction to execute the addition (convergence operation) of S1 to S4 is stored (queuing).

By the way, in the present embodiment, in order to explain the case of performing the total sum calculation process as the vector calculation process, the calculation processing unit 6 of the VU 2 is shown in FIGS.
Also, the configuration of the addition processing system of the arithmetic processing unit 4 of the CPU 1 is shown. As shown in FIG. 3, the arithmetic processing unit 6 of the VU 2
Is provided with four arithmetic units 10-1 to 10-4 for addition, like the conventional one shown in FIGS.
One addition process (parallelism 4) can be performed at the same time. Further, the arithmetic processing unit 6 includes each arithmetic unit 10-1 to 10-1.
Register 11- for temporarily storing the calculation result from 10-4
1 to 11-4, a partial sum end signal output unit 7 described later with reference to FIG. 5 is provided.

Here, the arithmetic processing unit 6 of the VU 2 of the present embodiment.
To briefly explain the operation of the above, the VU2 executes the total sum instruction to calculate the four partial sums S1 to S4 as in the conventional one shown in FIGS. In addition, in the arithmetic processing unit 6 of the VU 2 of this embodiment shown in FIG.
Although the case of creating 4 is explained, even if the degree of parallelism is 2 even 8
But it can be more than that.

In the case of the present embodiment with the parallel degree of 4, for example, the arithmetic unit 10-1 among the four arithmetic units 10-1 to 10-4 has the 1,5,9, ..., 4n + 1th of the vector data. Of the vector data are sequentially fetched into the arithmetic unit 10-2. Similarly, in the arithmetic unit 10-3, among the vector data, 3, 7, 11, ..., 4n + 3
The th data is sequentially fetched, and the arithmetic unit 10-4
Of the vector data, the 4,8,12, ..., 4n + 4th data are sequentially fetched.

The data fetched by each of the arithmetic units 10-1 to 10-4 is added to the data looped on the loop back path via the registers 11-1 to 11-4, and each arithmetic unit 10- The addition processing is performed until there is no input data to each of the arithmetic units 10-1 to 10-4.
The partial sums S1 to S4 are calculated from 0-4. And
Partial sum S calculated by each of the arithmetic units 10-1 to 10-4
1 to S4 are partial sum registers 8-1 to 8-4, respectively.
The partial sum end signal is simultaneously output from the partial sum end signal output unit 7 to notify the CPU 1.

On the other hand, as shown in FIG. 4, the arithmetic processing unit 4 of the CPU 1 stores the parts stored in the partial sum registers 8-1 to 8-4 so as to execute the convergence operation of adding the partial sums S1 to S4. An arithmetic unit 12 for adding the sums S1 to S4 and a register 13 for temporarily storing the arithmetic result from the arithmetic unit 12.
And two selectors 14A and 14B that perform a switching function described later on the input side of the arithmetic unit 12.

The configuration of the arithmetic processing unit 4 shown in FIG.
It has the same configuration as the conventional operation unit 34 for exclusive use of the convergence operation, the register 35, and the selectors 36A and 36B shown in FIG. 12, and their operations and functions are also the same. However, in the present embodiment, the arithmetic unit 12, the register 13, the selector 1
4A and 14B are not separately provided as in the conventional case for performing the converging operation, but are configured by using a portion normally provided in the CPU 1.

The convergence operation of the arithmetic processing unit 4 of the CPU 1 of this embodiment will be briefly described below. When the arithmetic processing unit 4 of the CPU 1 receives the partial arithmetic end signal from the partial sum end signal output unit 7 of the VU 2. A convergence operation for adding the partial sums S1 to S4 stored in the partial sum registers 8-1 to 8-4 is executed in accordance with the instruction stored in the operation queue 9.

In the convergence operation, in the arithmetic processing unit 4 of the present embodiment, in the first cycle, the selector 14A selects the partial sum S1 from the partial sum register 8-1 and the selector 14B selects the partial sum register 8-1. By selecting the partial sum S2 from -2, these partial sums S1 and S2 are added by the arithmetic unit 12, and the addition result is stored in the register 13.

In the second cycle, the selector 14A selects the data (partial sum S1 + S2) looped by the loopback path from the register 13, and the selector 14B selects the partial sum S3 from the partial sum register 8-3. By selecting, the partial sum S3 and the partial sum S1 + S2 from the register 13 are added by the arithmetic unit 12, and the addition result is stored in the register 13.

Then, in the third cycle, the selector 14
The partial sum S1 + S2 + S3 of the register 13 is selected by A, and the partial sum register 8 is selected by the selector 14B.
By selecting the partial sum S4 from -4, the partial sum S4 and the partial sum S1 + S2 + S3 from the register 13 are added by the calculator 12, and the final sum, that is, the total sum S = S1 + S2 +
S3 + S4 is calculated, and the convergence operation by the arithmetic processing unit 4 of the CPU 1 is completed.

Now, the configuration of the partial sum end signal output unit 7 provided in the arithmetic processing unit 6 of the VU 2 will be described with reference to FIG. In FIG. 5, reference numeral 15 is a VL counter register (vector length register), and the VL counter register 15 is a vector length VL of vector data transmitted from the CPU 1 together with vector data and a vector operation instruction [length of vector processing element. (The number of data)]
Is stored, and then the calculation result by the adder 16 described later is updated and stored.

Reference numeral 16 is an adder (ADD, subtraction unit), and this adder 16 is stored in the VL counter register 15 every time one cycle of partial operation processing is performed by each of the operation units 10-1 to 10-4. In order to subtract the parallelism of VU2 (the number of partial arithmetic operations performed simultaneously in one cycle) from the value,
In this embodiment, -4 is added. This adder 1
The calculation result of 6 is V through a selector 17 described later.
It is adapted to be updated / written in the L counter register 15. If the parallelism of VU2 is 8, naturally, the value added by the adder 16 is -8.

Reference numeral 17 is a selector, and this selector 17 is
At the start of the vector instruction, the vector length VL from the CPU 1 is selected and written in the VL counter register 15, and thereafter, the operation result from the adder 16 is selected and written in the VL counter register 15. 1
Reference numeral 8 denotes a VL counter checking unit (comparing unit). The VL counter checking unit 18 compares the operation result of the adder 16 with 0, and when the operation result becomes 0 or less, the partial sum for all vector data is obtained. It is determined that the arithmetic processing has been completed, and the instruction end signal is output as ON (High) for 1τ (1 control cycle).

In this embodiment, when the output (instruction end signal) from the VL counter check unit 18 rises, this is not immediately output as the partial sum end signal, and the instruction at this time is the sum total instruction. Considering whether or not it is the sum instruction, the operation code register 19, the decoder 20 and the A code are output so that the output (instruction end signal) from the VL counter check unit 18 is output as the partial sum end signal only when it is the sum instruction.
An ND gate 21 is provided.

That is, the operation code register 19 is
The instruction code (operation code) from U1 is stored, and the decoder 20 decodes the instruction code stored in the operation code register 19 and outputs a signal that rises when it is a sum instruction. The AND gate 21 takes the logical product of the output from the VL counter check unit 18 (instruction end signal) and the output from the decoder 20 and outputs it as a partial sum end signal to the CPU 1. That is, when the instruction from the CPU 1 is the sum instruction, when the output (instruction end signal) from the VL counter check unit 18 rises, the signal is output to the CPU 1 as the partial sum end signal.

The operation of the partial sum end signal output unit 7 of this embodiment will be briefly described with reference to FIG. For example, if the vector length VL = 17, the degree of parallelism is 4, and the sum instruction is given from the CPU 1, at the start of the instruction, VL
The value stored in the VL counter register 15 by the adder 16 every time the arithmetic unit 10-1 to 10-4 performs a partial sum operation process by writing "17" as the V value into the counter register 15. The parallel degree of 4 is subtracted from the output of the adder 16 and the VL counter register 1
The values of 5 are "13", "9", "5", "1", "-".
It is updated as 3 ”and“ −7 ”.

When the output of the adder 16 becomes "-3", the output (command end signal) from the VL counter check unit 18 rises for 1τ. At this time, since the instruction from the CPU 1 is the sum instruction, the output from the decoder 20 is also rising, and the AND gate 2
The partial sum end signal from 0 rises for 1τ and the CPU
1 is notified that the partial sum operation is completed.

Next, in the arithmetic processing unit of the present embodiment configured as described above, the operations of the control unit 3 and the arithmetic processing unit 4 of the CPU 1 and the control unit 5 and the arithmetic processing unit 6 of the VU 2 are performed.
The operation will be described with reference to FIGS. First,
When the control operation is started in the control unit 3 of the CPU 1,
As shown in FIG. 7, an externally applied instruction is decoded (step A1), and it is determined whether the instruction is a vector instruction (step A2). If it is not a vector instruction, it is judged to be a scalar instruction and the scalar instruction is executed (step A3), and then the program counter is updated (step A4).

On the other hand, if it is determined in step A2 that it is a vector instruction, it is determined whether or not the instruction is a summation instruction (step A5). If it is a summation instruction, it is stored in the operation queue 9. , A partial sum addition instruction is input (step A6), the total addition instruction is input to the VU (vector unit) 2, and the total addition instruction is executed (step A7). If it is determined in step A5 that it is not the sum instruction, the processing in step A6 is omitted, the vector instruction is input to VU2, and the vector operation processing corresponding to the vector instruction is executed (step A).
7). After the vector instruction is input to VU2, the program counter is updated (step A4), and the process returns to step A1.

The control unit 5 of the VU 2 constantly determines whether or not there is an unexecuted vector instruction (step C1). If there is no unexecuted vector instruction, the CPU 1 sends the vector instruction. Is waiting until is input. If it is determined in step C1 that there is an unexecuted vector instruction, that instruction is decoded (step C
2) It is determined whether the vector instruction can be executed (step C3). When it is in a non-executable state, that is, when the arithmetic processing is being executed by the arithmetic units 10-1 to 10-4, etc., it waits until it becomes the executable state. Then, if the vector instruction can be executed, the vector instruction is activated (step C4).

Then, the arithmetic processing unit 6 of the VU 2 always determines whether or not the vector instruction is activated from the control unit 5 (step D1), and stands by until the vector instruction is activated. When the vector instruction is activated, the vector instruction is executed (step D2), and whether or not the vector instruction is finished is output from the VL counter check unit 18 of the partial sum end signal output unit 7 described above with reference to FIG. The determination is made based on the rising edge of the (command end signal) (step D3).

When the output (instruction end signal) of the VL counter check unit 18 rises, it is determined that the vector instruction has ended. In the present embodiment, the instruction end signal output from the VL counter check unit 18 is further determined. Is based on the sum instruction (step D4). That is, when the summation instruction is completed, as shown in FIG.
As described above with reference to FIG. 6, the output of the decoder 20 rises, and the AND gate 21 notifies the CPU 1 of the instruction end signal of the VL counter check unit 18 as a partial sum end signal (step D5).

Further, the arithmetic processing unit 4 of the CPU 1 always determines whether or not the partial sum end signal is sent from the VU 2 (step B1), and waits until the partial sum end signal is sent. There is. When the partial sum end signal is sent, the partial sums S1 to S4 obtained by the VU2 are in the states stored in the partial sum registers 8-1 to 8-4, respectively. The partial sum addition instruction (convergence operation instruction) in the queue 9 is executed as described above with reference to FIG. 4 (step B2). When the converging operation is completed, the arithmetic processing unit 4 discharges (dequeues) the partial sum addition instruction from the arithmetic queue 9 (step B3), and again enters the partial sum end signal standby state.

Thus, according to one embodiment of the present invention,
VU for normal partial sum operation on predetermined vector data
By executing the converging operation of adding the partial sums S1 to S4 by the CPU 1 after being executed by 2, the subsequent vector operation instruction in the VU 2 is not made to wait by the converging operation, and the vector processing is significantly speeded up. In addition, since the CPU 1 performs the converging operation, it is not necessary to separately provide the VU 2 with an arithmetic unit dedicated to the converging operation, and the physical quantity is not increased.

Further, according to this embodiment, the vector length VL and VU2 are controlled by the partial sum end signal output unit 7 of VU2.
Since it is possible to reliably determine whether or not the partial sum calculation processing for all vector data has been completed based on the degree of parallelism of the CPU, the partial sum end signal can be accurately output, and the CPU
In 1, the convergence operation can be reliably started and executed.

Further, according to this embodiment, at the same time when the CPU 1 issues a vector operation instruction, the operation queue 9
By inputting a partial sum addition instruction (convergence operation instruction), the CPU 1 side controls the vector operation instruction to be ejected, and other operation processing can be continued. In other words, by sharing the vector operation processing between the CPU 1 and the VU 2, it is possible to efficiently use the VU 2 and significantly improve the processing performance without increasing the physical quantity.

In the above-described embodiment, the case where the vector operation instruction is the sum instruction is explained, but the present invention is not limited to this, and the operation result can be obtained even if the vector operation instruction changes the operation order. If it is an arithmetic instruction that does not change (for example, a total product instruction), it is applied in the same manner as in the above-mentioned embodiment, and the same effect as the above-mentioned embodiment can be obtained.

[0055]

As described above in detail, according to the arithmetic processing method and the arithmetic processing apparatus of the present invention, the partial arithmetic operation (the partial sum arithmetic operation, the partial product arithmetic operation) on the predetermined vector data is executed by the vector processing section as usual. Then, the central processing unit executes the convergence operation (addition of partial sums, multiplication of partial products) for the partial operation result, so that the subsequent vector operation instruction in the vector processing unit does not wait by the convergence operation. Not only can the vector processing speed be significantly increased, but since the central processing unit performs the convergence operation, it is no longer necessary to separately provide an arithmetic unit or the like dedicated to the convergence operation in the vector processing unit, which does not lead to an increase in the physical quantity. Items 1-3, 5-7).

When all the partial calculations are completed in the vector processing section and the partial calculation results are stored in the registers, the vector processing section outputs a partial calculation end signal.
The central processing unit can surely execute the convergence operation for the partial operation result stored in the register in accordance with the partial operation end signal (claims 4 and 8). Further, according to the arithmetic processing unit of the present invention, the partial arithmetic end signal output unit of the vector processing unit ends the partial arithmetic processing for all vector data based on the vector length of the vector data and the parallelism of the vector processing unit. Since it is possible to reliably determine whether or not the partial operation is completed, the partial operation end signal can be accurately output, and the central processing unit can reliably start the converging operation (claim 9).

Further, at the same time that the central processing unit issues the vector operation instruction, the instruction to execute the convergence operation is input to the operation queue, so that the vector operation instruction is released and controlled on the side of the central processing unit. Other arithmetic processing can be continued. That is, by sharing the vector calculation processing between the central processing unit and the vector processing unit, it is possible to efficiently use the vector processing unit and significantly improve the processing performance without increasing the physical quantity. 10).

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing an overall configuration of an arithmetic processing unit as one embodiment of the present invention.

FIG. 3 is a block diagram showing a main configuration of a vector processing unit according to the present embodiment.

FIG. 4 is a block diagram showing a main configuration of a central processing unit of the present embodiment.

FIG. 5 is a block diagram showing a configuration of a partial sum end signal output unit in the vector processing unit of the present embodiment.

FIG. 6 is a time chart for explaining the operation of the partial sum end signal output unit in the vector processing unit of this embodiment.

FIG. 7 is a flowchart for explaining the operation of the control unit in the central processing unit of this embodiment.

FIG. 8 is a flowchart for explaining the operation of the arithmetic processing unit in the central processing unit of the present embodiment.

FIG. 9 is a flowchart for explaining the operation of the control unit in the vector processing unit of this embodiment.

FIG. 10 is a flowchart for explaining the operation of the arithmetic processing unit in the vector processing unit of this embodiment.

FIG. 11 is a block diagram for explaining a conventional vector processing unit and its summing operation processing operation.

FIG. 12 is a block diagram for explaining another example of a conventional vector processing unit and its total operation processing operation.

[Explanation of symbols]

 1 Central Processing Unit (CPU) 2 Vector Processing Unit (VU) 3, 5 Control Unit 4, 6 Arithmetic Processing Unit 7 Partial Sum End Signal Output Unit (Partial Operation End Signal Output Unit) 8 Partial Sum Register 9 Arithmetic Queue 10-1 -10-4,12 arithmetic unit 11-1-11-4,13 register 14A, 14B, 17 selector 15 VL counter register (vector length register) 16 adder (ADD, subtraction unit) 18 VL counter check unit (comparison unit) ) 19 opcode register 20 decoder 21 AND gate

Claims (10)

[Claims] 1. An arithmetic processing device comprising a central processing unit and a vector processing unit capable of receiving a vector arithmetic instruction from the central processing unit and simultaneously executing a plurality of arithmetic operations, thereby performing arithmetic processing on predetermined vector data. When performing, the central processing unit performs a partial operation on the predetermined vector data by the vector processing unit, and then performs a convergence operation on the partial operation result by the vector processing unit by the central processing unit. Method. 2. When the arithmetic processing for the predetermined vector data is a total sum arithmetic processing, a partial arithmetic operation for obtaining a partial sum of the predetermined vector data is executed by the vector processing unit, and then the partial sum by the vector processing unit is added. The arithmetic processing method according to claim 1, wherein the convergence operation is performed by the central processing unit. 3. When the calculation process for the predetermined vector data is a total product calculation process, a partial calculation for obtaining a partial product of the predetermined vector data is executed by the vector processing unit, and then the partial product is calculated by the vector processing unit. 2. The arithmetic processing method according to claim 1, wherein the convergence operation for multiplication is executed by the central processing unit. 4. When all the partial operations by the vector processing unit are completed, a partial operation end signal is output from the vector processing unit to the central processing unit, and the convergence occurs when the central processing unit receives the partial operation end signal. The arithmetic processing method according to any one of claims 1 to 3, wherein an operation is executed. 5. An arithmetic processing device comprising a central processing unit and a vector processing unit capable of receiving a vector arithmetic instruction from the central processing unit and executing a plurality of arithmetic operations at the same time. When performing, the vector processing unit executes a partial operation on the predetermined vector data, and the central processing unit executes a convergence operation on the result of the partial operation by the vector processing unit. . 6. When the arithmetic processing for the predetermined vector data is a summation arithmetic processing, the vector processing unit executes a partial arithmetic operation for obtaining a partial sum of the predetermined vector data,
The arithmetic processing device according to claim 5, wherein the central processing unit executes a converging operation for adding partial sums by the vector processing unit. 7. When the arithmetic processing on the predetermined vector data is a total product arithmetic processing, the vector processing unit executes a partial arithmetic operation for obtaining a partial product of the predetermined vector data,
The arithmetic processing unit according to claim 5, wherein the central processing unit executes a converging operation for multiplying a partial product by the vector processing unit. 8. A partial calculation end signal output for providing a register for storing a partial calculation result by the vector processing unit, and outputting a partial calculation end signal to the central processing unit when all the partial calculations by the vector processing unit are completed. A vector processing unit, the central processing unit, when receiving the partial operation end signal from the partial operation end signal output unit, executes a convergence operation for the partial operation result stored in the register. The arithmetic processing unit according to any one of claims 5 to 7, which is characterized. 9. A vector length register for storing the vector length of the vector data sent from the central processing unit together with the vector data and the vector operation instruction to the partial operation end signal output section, and the partial operation processing. Every time one cycle is performed, the parallelism of the vector processing unit is subtracted from the value stored in the vector length register, and the subtraction unit re-stores the value in the vector length register, and the subtraction result by the subtraction unit is compared with 0. , The subtraction result is 0
9. The arithmetic processing device according to claim 8, further comprising: a comparison unit that outputs the partial calculation end signal when the following occurs. 10. An arithmetic queue for storing arithmetic instructions from the central processing unit, wherein the central processing unit outputs the vector arithmetic instruction to the vector processing unit, and at the same time, the vector processing unit outputs the vector arithmetic instruction to the arithmetic queue. When the central processing unit receives the partial operation end signal from the partial operation end signal output unit, an instruction to execute a convergence operation for the partial operation result stored in the register is stored in the operation queue. The arithmetic processing unit according to claim 8 or 9, wherein a converging operation is performed on the partial operation result stored in the register according to the stored instruction.