JPH0846002A - Code setting circuit - Google Patents

Abstract

PURPOSE:To provide a code setting circuit in which a transistor in the circuit is protected from the breakdown caused by a high voltage noise pulse which is produced when a thin film cutting voltage is supplied at the time of the trimming of a reference voltage and which generates a highly reliable code. CONSTITUTION:A parallel connection circuit composed of p-type transistors P1 and P2 and an n-type transistor N1 are connected in series and this series circuit is inserted between a cutting voltage supply pad 8 and a power supply voltage VDD. An inverter 2 whose input terminal is connected to the connection point A1 and whose output terminal is connected to the gate electrode of the transistor P1 and an inverter 5 whose input terminal is connected to the connection point A1 and whose output terminal is connected to a decoder 1 are provided. The pad 8 is connected to a grounding potential GND through a thin film resistor 14. A plurality of the code setting circuits like this are connected to the decoder 1. Control signals SP which are temporarily in high level states when a power supply is turned on and turn on the transistors P2, P4 and P6 are supplied to the gate electrodes of the transistors P2, P4 and P6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code setting circuit, and more particularly to a code setting circuit provided inside a semiconductor integrated circuit (IC) and having a thin film resistance fuse for trimming in a reference voltage generating means.

[0002]

2. Description of the Related Art With the recent progress in high performance and high integration of IC devices, there is a demand for high precision and low power consumption of condition setting means for operating internal circuits of IC under predetermined conditions. Is getting stronger and stronger. In an IC device or the like, in order to obtain a highly accurate reference voltage from a reference voltage generating circuit used in an analog circuit or the like, it is necessary to trim the reference voltage setting element with respect to temperature dependence, manufacturing variation, and the like. Setting these reference voltage values,
Or, as for the setting of circuit current, etc., its analog standard is very strict, so by trimming the reference voltage value or current value during the manufacturing process, trimming is performed to adjust each value so that it falls within the desired standard. A circuit is needed.

Since this trimming is such that the setting state is fixed once it is set in the manufacturing process, it is possible to readjust these set values during the operation of the circuit to which this IC is applied. It is a property that cannot be changed over the years because it cannot. Therefore, a highly reliable trimming setting circuit without malfunction is required for this trimming.

For example, referring to FIG. 5A showing a circuit diagram for explaining an example of adjusting a voltage at a Vref voltage input point of a reference voltage generating circuit by a trimming code,
This circuit is an example of the case of the trimming code of 2 bits, and resistors R51 to R54 having a resistance value of 1 K ohm are connected in series between the power supply voltage 5V and the ground potential. Series connection point of resistors R51 and R52 and voltage follower 5
3 (+) terminal and transistors M51 and M5
3 are connected in series, and a transistor M52 is connected between this series connection point and the series connection point of the resistors R52 and R53. Similarly, transistors M54 and M56 are connected in series between the series connection point of the resistors R53 and R54 and the (+) terminal of the voltage follower 53, and the series connection point and the other end (ground potential) of the resistance R54 are connected. A transistor M55 is connected between them. These transistors M5
The first trimming code from the decoder (not shown) is applied to the gate electrodes of 2 and M55, and the first trimming code is applied to the gate electrodes of the transistors M51 and M54 via the inverter 51.
Inversion signals of the trimming code of are respectively supplied.
Similarly, the second trimming code is supplied to the gate electrode of these transistors M56, and the inverted signal of the second trimming code is supplied to the gate electrode of the transistor M53 via the inverter 52. .

Here, whether or not the fuse is blown is generated by the decoder as a trimming code, and the resistance value as the reference voltage adjusting means is set to the voltage value corresponding to the code by this code. For example, if the first and second trimming codes are "0" and "0", respectively, the transistors (M31 and M53) cause the (+) terminal, that is, A in the figure.
A value of (3/4) × 5V is supplied to the point, and if it is “1” and “0”, it is (1/2) × 5V, “0” and “1”.
If there is (1/4) × 5V, and if there is “1” and “1”, 0V is supplied.

An example of a conventional code setting circuit of this type is described in Japanese Patent Application Laid-Open No. 4-150050. Referring to FIG. 5B showing the circuit diagram of the code setting circuit described in the publication, the disconnection voltage supply pad 8 and the power supply voltage VDD
A parallel connection circuit composed of p-channel transistors P1 and P2 and an n-channel transistor N1 are connected in series between the two. An input end is connected to each of the series connection points A1 and an output end is a p-channel transistor P1.
Has an inverter 2 connected to the gate electrode and an inverter 5 having an output terminal connected to the decoder 1. The disconnection voltage supply pad 8 is connected to the ground potential GND via the thin film resistor 14.
It is connected to the.

A plurality of such code setting circuits (three bits in this example) are connected to the decoder 1, and the gate electrodes of the p-channel transistors P2, P4 and P6 are temporarily set to low level at power-on. Then, a control signal SP for turning on these transistors is supplied.

In such a structure, the p-channel transistors P2, P4 and P6 are turned on by the signal SP only when the power is turned on to form a ratio circuit with the thin film resistors 14-16. Normally, this thin film resistor 14-1
Since 6 is set to about 50Ω, for example, the on-resistance of the p-channel transistors P2, P4 and P6 is set to 1
If it is set to KΩ or more, the connection points A1 to A3 are at low levels when the thin film resistors 14 to 16 are not disconnected. Therefore, the inverters 5 to 7 output the high level to the decoder 1.

For example, when the pulse voltage is supplied to the thin film resistor 15 through the disconnection voltage supply pad 9 to disconnect it, the connection point A2 becomes high level by the p-channel transistor P4, and the inverter 6 sets low level to the decoder 1. Output.

As described above, the p-channel type transistors P2, P4 and P6 are temporarily turned on only when the power is turned on. However, the p-channel transistors P2, P4 and P6 are turned on by the inverters 2-4 which invert and output the levels of the connection points A1-3. Off-controlled p-channel transistors P1, P3 and P
5 exists, the levels of the connection points A1 to A3, which have been set once, are stably maintained.

Here, n-channel type transistors N1 to N1
The action of N3 will be described. If these transistors do not exist and the p-channel transistors P2, P4, and P6 are directly connected to the disconnection voltage supply pads 8 to 10, the p-channel transistor P
Since the forward biased PN junction formed by the diffusion layer exists in the drain electrodes of P2, P4 and P6, the power supply line of the power supply voltage VDD is connected to the disconnection voltage supply pads 8 to 10 through this PN junction. It is equivalent to being connected.

That is, the cutting voltage supply pads 8 to 10
Therefore, the wiring capacitance of the power supply voltage VDD is added, and the rising speed of the pulse voltage applied to the pad becomes very slow. It is generally known that, when the thin film resistor is cut, the higher the rising speed of the pulse of the cutting voltage, the better the cutting. Therefore, in this conventional circuit, n-channel type transistors N1 to N are respectively provided between the cutting voltage supply pads 8 to 10 and the drain electrodes of the p-channel type transistors P2, P4 and P6.
3 is inserted, the power supply voltage VDD becomes P in the forward direction.
Each cutting voltage supply pad 8 to 1 through the N-junction diode
I am trying not to be supplied to 0.

[0013]

In the above-mentioned conventional code setting circuit, when the thin film resistor is cut in the manufacturing process, a voltage pulse is supplied from the external power supply to the cutting voltage supply pad. When the thin film resistor is cut off, the impedance of the cutting voltage supply pad rapidly increases. Therefore, the external power supply instantaneously boosts the voltage pulse and a high-voltage noise pulse is supplied to the disconnection voltage supply pad. This noise pulse voltage is n
If it is higher than the breakdown voltage between the diffusion layers of the electrodes of the channel transistors N1 to N3 and the substrate, the diffusion layers of the electrodes of the n channel transistors N1 to N3 connected to the disconnection voltage supply pad cause junction breakdown. Therefore, a leak current is generated between the diffusion layer and the substrate. As a result, the input levels of the inverters 2 to 4 may fluctuate and cause trimming failure.

The object of the present invention is made in view of the above-mentioned drawbacks, and in the circuit, the high voltage noise pulse generated when the cutting voltage for cutting the thin film resistor is supplied at the time of trimming the reference voltage. An object of the present invention is to provide a code setting circuit capable of preventing a transistor from being destroyed and capable of highly reliable code generation.

[0015]

The code setting circuit of the present invention is characterized by a first cutting voltage supply pad to which a predetermined cutting voltage is supplied from the outside, the first cutting voltage supply pad and a low voltage source. A thin film resistor for trimming a reference voltage, which is inserted between the first disconnection voltage and the first disconnection voltage supply pad; And a series connection circuit in which a first second conductivity type transistor is inserted in series connection, and a second connection circuit connected in parallel to the first first conductivity type transistor and conducting with a predetermined control signal only when power is turned on. 1
A conductivity type transistor, a first inverter for inverting and outputting the potential at the series connection point to the gate electrode of the first first conductivity type transistor, and a second inverter for inverting and outputting the voltage at the series connection point as a code signal. Inverter and this second
In a code setting circuit having a plurality of decoders for decoding the output of the inverter as a predetermined code signal according to the presence or absence of the thin film resistor, a noise absorbing means for absorbing a noise pulse generated from an external power source when the thin film resistor is cut off. Between the thin film resistor and the low voltage source.

Further, the noise absorbing means uses the first disconnection voltage supply pad as a fixed voltage supply pad fixed to a predetermined constant potential, and a second disconnection voltage supply pad between the thin film resistor and the low potential power supply. A second transistor of the second conductivity type may be inserted in series and the gate electrode thereof may be connected to a high voltage source.

Further, the noise absorbing means is the first
Directly connecting the parallel connection circuit composed of the first and second first conductivity type transistors and the respective input terminals of the first and second inverters to the fixed voltage supply pad without using the second conductivity type transistor of You can also connect.

Furthermore, the first conductivity type transistor and the second conductivity type transistor are replaced with each other, and the fixed voltage supply pad and the second disconnection voltage supply pad are also replaced with each other. The voltage supplied to the voltage supply pad can also be a voltage with a predetermined opposite polarity.

[0019]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1A is a circuit diagram showing a first embodiment of the code setting circuit of the present invention. Referring to FIG. 1A, a part different from the conventional code setting circuit shown in FIG. 5B is that another cutting voltage supply pad 11 is provided between the thin film resistors 14 to 16 and the ground potential. ~ 13 and n-channel type transistors N4 to N6 are respectively connected in series,
That is, each gate electrode was connected to the power supply voltage VDD terminal. At this time, the conventional first cutting voltage supply pads 10 to 10 are fixed voltage supply pads. The other configuration is the same as that of the circuit shown in FIG. 5B, the same components are designated by the same reference numerals, and the description of the configuration will be omitted.

On the other hand, referring to FIG. 1B, which is a sectional view showing the structure of the main part of the above-mentioned structure, an n ⁺ diffusion forming the drain and source electrodes of the transistors N1 and N2 on the p-type semiconductor substrate. Layer regions are provided to form the source and drain electrodes of the n-channel transistors N1 and N4 in the n ⁺ diffusion layer regions, respectively, and the gate formed on the upper surface of the channel region between the drain and source electrodes. The electrodes are connected to the power supply voltage VDD terminal, respectively. The n ⁺ diffusion layer region of the drain electrode of the n-channel transistor N1 is connected to the connection point A1, and the n ⁺ diffusion layer of the source electrode is the fixed voltage supply pad 8,
It is connected to the n ⁺ diffusion layer of the drain electrode of the transistor N4 via the thin film resistor 14 and the cutting voltage supply pad 11. The source electrode of the n-channel transistor N4 is connected to the ground potential GND terminal.

In the structure of FIG. 1A, the thin film resistor 14
Cutting voltage supply pads 11 to 13 for cutting
A case where a disconnection voltage pulse is applied from an external power source will be described.

First, when power is supplied to this circuit, a control signal SP that temporarily becomes low level is supplied only when power is supplied, and in response to this signal SP, the P-channel transistors P2, P4 and P6 are momentarily supplied. It becomes conductive.
Therefore, the potentials of the connection points A1 to A3 are raised to a high level by the power supply voltage VDD, and the high level pulse voltage is inverted to a low level by the inverters 2 to 4 and is applied to the gate electrodes of the P-channel transistors P1, P3 and P5. Each is supplied. These low-level pulse voltages bring the P-channel transistors P1, P3, and P5 into a conductive state, and the potentials at the connection points A1 to A3 are reset to a high level again. Inverted to the level, P-channel transistor P1,
It is supplied to the gate electrodes of P3 and P5, respectively. Since this cycle is repeated thereafter, the potentials at the connection points A1 to A3 continue to be at a high level even if the signal SP is an instantaneous pulse.

At this time, the ground potential is supplied as a fixed voltage to the fixed voltage supply pads 8 to 10. In this state, for example, the disconnection voltage supply pads 11 to 13 from the external power supply
A 10V disconnection voltage pulse is applied to. As a result, a large current flows from the fixed voltage supply pads 8 to 10 to the ground potential GND terminal via the thin film resistor 14, and the thin film resistor 14 to 10
When 16 is disconnected, the impedances of the disconnection voltage supply pads 11 to 13 are rapidly increased, and the external power supply for supplying the disconnection voltage is instantaneously boosted to generate high voltage noise.

As a result of the experiment, when the cutting voltage supply pulse voltage is 10 V and the supply period is 1.5 ms and the thin film resistor is cut, the pulse width is instantaneously 100 ns and the voltage is 2
A noise pulse generation of 3.1 V was observed.

Referring again to FIG. 1B, n-channel type transistors N4 to N6 (N5 and N6 are not shown).
The breakdown voltage between the n ⁺ diffusion layer and the semiconductor substrate forming the electrode is 19 V, which is higher than this voltage.
A noise pulse of 3.1V causes a PN junction of the n-channel transistors N4 to N6 (diode symbol J in the figure
D) is destroyed.

However, since the thin film resistor is already cut by the supply of the cutting voltage supply pulse voltage,
There is no influence on the circuit portion for setting the code, that is, the p-channel type transistors P1 to P6, the inverters 2 to 6 and the n-channel type transistors N1 to N3.

As described above, the fixed voltage supply pads 8 to 1
Since 0 is fixed to the ground potential, after the thin film resistance is cut off, the connection points A1 to A3 are changed by the ratio ratios of the p channel transistors P1, P3 and P5 and the n channel transistors N1 to N3. The potential of is maintained at a low level.

In the above description, the cutting voltage supply pad 11
To 13 to supply the cutting voltage to all the thin film resistors 14 to 16
Although the example in which all of the above are disconnected is described, the disconnection voltage supply pad 1
1 to 13 are selected as necessary, and the fixed voltage supply pad and the disconnection voltage supply pad connected to the unselected thin film resistors are opened to connect the connection points A1 to A1.
Since a predetermined inverter output potential of A3 maintains a high level, the predetermined outputs of the inverters 5 to 6 which invert and output the voltage become a low level code signal, and by combining these, a desired trimming code can be generated. Good.

Next, referring to FIG. 2 (a) showing the circuit diagram of the code setting circuit of the second embodiment, this circuit is different from the first embodiment shown in FIG. 1 (a). That is, the n-channel transistors N1 to N3 are removed from the circuit of the first embodiment, and the p-channel transistors P1 to P6 are directly connected to the disconnection voltage supply pads 8 to 10.
The rest of the configuration is the same as that of the first embodiment, the same components are assigned the same reference numerals, and the description of the configuration is omitted.

In this circuit configuration, when the circuit is powered on, a control signal SP is supplied, and in response to this signal SP, P-channel type transistors P2, P4 and P are provided.
6 is instantaneously turned on, and the potentials at the connection points A1 to A3 are raised to a high level by the power supply voltage VDD. The high level pulse voltage is inverted to a low level by the inverters 2 to 4 and supplied to the gate electrodes of the p-channel transistors P1, P3 and P5, respectively. With these low level pulse voltages, the p-channel transistor P
1, P3 and P5 become conductive, and connection points A1 to A
The potential of 3 is reset to the high level again. This connection point A
1 to A3 high level → inverter 1 to 3 output low level → P
The voltage maintaining cycle of the channel type transistors P2 to P4 and P6 conduction → the connection points A1 to A3 at the high level is the same as that of the first embodiment.

Here, the p-channel type transistors P1 to P1
A fixed voltage of -5 V is applied to the fixed voltage supply pads 8 to 10 so that the PN junction is not biased in the forward direction by the drain diffusion layer of P6. In this state, for example, 5
The cutting voltage pulse of V is set to the cutting voltage supply pads 11 to 13.
(In this case, it is also the connection points A1 to A3).

As a result, the cutting voltage supply pads 11 to 13
To the fixed voltage supply pads 8 to 10 via the thin film resistor 14.
When a large current flows to the fixed power supply side connected to the thin film resistors 14 to 16 and the thin film resistors 14 to 16 are disconnected, the disconnection voltage supply pads 11 to
The impedance of 13 suddenly increases, and the external power supply that supplies the disconnection voltage is instantaneously boosted to generate high-voltage noise.

Since this noise pulse is a pulse voltage of 23.1 V, which is higher than the breakdown voltage 19 V of the n-channel type transistors N4 to N6 as described above,
The PN junctions of the n-channel transistors N4 to N6 (indicated by the diode JD in the figure) are destroyed. However, since the thin film resistors 14 to 16 are cut off, in this case as well, there is no effect on the circuit portion for setting the code.

Since the fixed voltage supply pad is fixed at -5V potential, the connection points A1 to A1 are cut after the thin film resistor is cut off.
The voltage of A3 becomes low level and maintains that state.

In the above description of the second embodiment, the cutting voltage is supplied to all the cutting voltage supply pads 8 to 10 to cut all the thin film resistors 14 to 16, but the cutting voltage supply pads are required. The fixed voltage supply pad and the disconnection voltage supply pad that are connected to the thin film resistors that are selected according to
Since the predetermined potential of A3 is maintained at the high level, the predetermined outputs of the inverters 5 to 6 which invert and output the voltage become the low-level code signals, and these may be combined to generate the desired trimming code.

In the case of the second embodiment, since the n-channel transistors N1 to N3 are deleted, the number of constituent elements can be made smaller than that of the first embodiment, so that the chip area can be made smaller.

Next, referring to FIG. 3 (a) showing the circuit diagram of the code setting circuit of the third embodiment, this circuit is different from the first embodiment shown in FIG. 1 (a). , N-channel transistor and p-channel transistor in the first embodiment, fixed voltage supply terminal and disconnection voltage supply terminal,
In addition, the polarity of the fixed voltage and the polarity of the disconnection voltage are all opposite to each other. That is, the cutting voltage supply pad 8
The p-channel transistor P1 is connected between the power supply voltage VDD terminal and the power supply voltage VDD, and its gate electrode is at the ground potential GND.
It is connected to the terminal. A thin film resistor 14 is connected between the cutting voltage supply pad 8 and the fixed voltage supply terminal 11.
Between the fixed voltage supply pad 11 and the ground potential GND terminal, a p-channel type transistor P4 and an n-channel type transistor N, whose gate electrodes are connected to the ground potential GND terminal, are provided.
A parallel connection circuit composed of 1 and N2 is inserted in series connection. An input terminal is connected to each of the serial connection points A1 and an output terminal is connected to the gate electrode of the n-channel transistor N1.
And an inverter 5 connected to.

A plurality of such code setting circuits (three bits in this example) are connected to the decoder 1, and P1 and P2 are connected.
And P3, P4 and P5 and P6, N1 and N3 and N5, N2 and N4 and N6, pads 8 and 9 and 1
0, pads 11 and 12 and 13, inverters 2 and 3 and 4, and inverters 5 and 6 and 7, respectively. Further, a control signal SP for turning on these n-channel transistors N2, N4 and N6 for turning on these transistors is supplied to the gate electrodes of the n-channel transistors N2, N4 and N6 when the power is on.

Referring to FIG. 3B, which is a sectional view showing the structure of the main part of the above-described structure, an n well region is formed on the p-type semiconductor substrate, and the transistor P is formed on the n well region.
P ⁺ forming the source and drain electrodes of 1 and P4
Diffusion layer regions are provided to form the source and drain electrodes of the p-channel transistor P1 in these p ⁺ diffusion layer regions, and a gate electrode formed on the upper surface of the channel region between the source and drain electrodes. Are respectively connected to the ground potential GND terminal. p
The p ⁺ diffusion layer region of the source electrode of the channel type transistor P1 is connected to the power supply voltage VDD terminal, and the p of the drain electrode is p.
^{The +} diffusion layer is connected to the p ⁺ diffusion layer of the source electrode of the transistor P4 via the cutting voltage supply pad 8, the thin film resistor 14 and the fixed voltage supply pad 11. The drain electrode of the p-channel transistor P4 is connected to the connection point A.

In the structure of FIG. 3A, the thin film resistor 14
A case where a disconnection voltage pulse is applied from an external power supply to the disconnection voltage supply pads 8 to 10 for disconnecting disconnections 16 to 16 will be described.

First, when the circuit is powered on, the control signal SP is supplied, and in response to the signal SP, the n-channel type transistors N2, N4 and N6 are instantaneously turned on. Therefore, the potentials of the connection points A1 to A3 are pulled down to a low level by the ground potential GND, and the low level voltage is inverted to a high level by the inverters 2 to 4 and applied to the gate electrodes of the n-channel transistors N1, N3 and N5, respectively. Supplied. Due to these high level pulse voltages, n-channel transistors N1, N3 and N
5 becomes conductive, the potentials at the connection points A1 to A3 are reset to the low level again, and this low level is again set to the inverter 2
Inverted to a high level at ~ 4 and supplied to the gate electrodes of the n-channel transistors N1, N3 and N5, respectively. Since this cycle is repeated thereafter, the signal SP
Even if the pulse is an instantaneous pulse, the potentials at the connection points A1 to A3 maintain a low level potential.

At this time, the fixed voltage supply pads 11 to 13
Is supplied with a ground potential as a fixed voltage. In this state, a cutting voltage pulse, for example, -10V is applied to the cutting voltage supply pads 8 to 10 from an external power source. As a result, a large current flows from the disconnection voltage supply pads 8 to 10 to the -10V power source side through the thin film resistor 14, and the thin film resistor 1
When 4 to 16 are cut, the cutting voltage supply pads 8 to 10
The impedances of 1 and 2 are suddenly increased, and the external power supply that supplies the disconnection voltage is instantaneously boosted to generate high-voltage noise as in the cases 1 and 2.

Referring again to FIG. 3B, p-channel type transistors P1 to N3 (P2 and P3 are not shown).
The breakdown voltage between the p ⁺ diffusion layer that forms the electrode of the semiconductor substrate and the semiconductor substrate is 19 V, and the noise pulse higher than this voltage causes the p-channel transistors P1 to
The P3 PN junction (indicated by diode JD in the figure) is destroyed.

However, since the thin film resistor has already been cut by the supply of the cutting voltage supply pulse voltage,
There is no influence on the circuit portion for setting the code, that is, the n-channel type transistors N1 to N6, the inverters 2 to 6 and the p-channel type transistors P4 to P6.

Since the fixed voltage supply pad is fixed to the ground potential GND terminal as described above, after the thin film resistor is cut off, the potentials at the connection points A1 to A3 are low and the outputs from the inverters 5 to 7 are low. Maintain a high level.

In the above description, the cutting voltage supply pads 8 ...
Although the example in which the cutting voltage is supplied to all 10 to cut all the thin film resistors 14 to 16 has been described, the cutting voltage supply pad is selected as necessary and connected to the unselected thin film resistors as in the first embodiment. The fixed voltage supply pad and the disconnection voltage supply pad to be connected are opened by connecting them to the connection point A.
Since a predetermined potential of 1 to A3 maintains a high level, the outputs of the inverters 5 to 6 which invert and output the voltage become a low level code signal, and if these are combined to generate a desired trimming code. Good.

Next, referring to FIG. 4A showing the circuit diagram of the code setting circuit of the fourth embodiment, the difference between this circuit and the second embodiment shown in FIG. , An n-channel transistor and a p-channel transistor in the second embodiment, a fixed voltage supply terminal and a disconnection voltage supply terminal,
And a circuit in which the polarities of the fixed voltage and the disconnection voltage are all opposite to each other. The specific configuration is such that the p-channel transistors P4, P5 and P6 are deleted from the configuration of the third embodiment, and Channel type transistors N1 to N
6 and the input ends of the inverters 2 to 7 are directly connected to the fixed voltage supply pads 11 to 13, respectively. The other configuration is the same as that of the third embodiment, and the same components are designated by the same reference numerals and the description of the configuration is omitted.

Referring to FIG. 4B, which is a sectional view showing the structure of the main part of the above-described structure, an n-channel transistor N1 and an n-well region are formed on a p-type semiconductor substrate, and on this n-well region. Regions of p ⁺ diffusion layers that form the source and drain electrodes of the transistor P1 are provided respectively, and these p ⁺ diffusion layer regions form the source and drain electrodes of the p-channel transistor P1, and the source and drain of these transistors are formed. The gate electrode formed on the upper surface of the channel region between the electrode and the electrode is connected to the ground potential GND terminal. The p ⁺ diffusion layer region of the source electrode is connected to the power supply voltage VDD terminal, and the p ⁺ diffusion layer of the drain electrode is connected to the source electrode n of the transistor N1 via the cutting voltage supply pad 8, the thin film resistor 14 and the fixed cutoff voltage supply pad 11. ⁺
Connected to the diffusion layer. This n-channel transistor N
The drain electrode of No. 1 is connected to the fixed voltage supply pad 11 (connection point A1 in this case).

In the structure of FIG. 4A, the thin film resistor 14
A case where a disconnection voltage pulse is applied from an external power supply to the disconnection voltage supply pads 8 to 10 for disconnecting disconnections 16 to 16 will be described.

The operation of this circuit is such that, when the circuit is powered on, the control signal SP is supplied, and in response to this signal SP, the n-channel type transistors N2, N4 and N6 momentarily become conductive, and the signal Even if SP is an instantaneous pulse, the potential at the connection point A maintains a low level potential, and the basic operation is the same as in the third embodiment.

In particular, in this embodiment, the p-channel type transistors P4 and P6 in the third embodiment are omitted, so that a fixed voltage of 5V is supplied to the fixed voltage supply pads 11 to 13. In this state, a cutting voltage pulse, for example, -5V is applied to the cutting voltage supply pads 8 to 10 from the external power source. As a result, the voltage is supplied from the fixed voltage supply pads 11 to 13 through the thin film resistors 14 to −5.
When a large current flows to the V power supply side and the thin film resistors 14 to 16 are disconnected, the impedances of the disconnection voltage supply pads 8 to 10 rapidly increase, and the external power supply that supplies the disconnection voltage as in the actual cases 1 and 2. Instantaneously boosts and generates high-voltage noise on the negative side.

Referring again to FIG. 4B, p-channel type transistors P1 to P3 (P2 and P3 are not shown).
The breakdown voltage between the p ⁺ diffusion layer that forms the electrode of the semiconductor substrate and the semiconductor substrate is 19 V, and the noise pulse higher than this voltage causes the p-channel transistors P1 to
The P3 PN junction (indicated by diode JD in the figure) is destroyed.

However, since the thin film resistor is already cut by the supply of the cutting voltage supply pulse voltage,
As in the above, the circuit portion for setting the code, that is, the n-channel type transistors N1 to N6 and the inverters 2 to 6 is not affected at all.

Since the fixed voltage supply pad is fixed to the voltage of 5 V, after the thin film resistor is cut off, the connection points A1 to
The potential of A3 maintains a high level and the outputs of the inverters 5 to 7 maintain a low level.

Also in the above description, the cutting voltage supply pads 8 to 8
Although the example in which the cutting voltage is supplied to all 10 to cut all the thin film resistors 14 to 16 has been described, the cutting voltage supply pad is selected as necessary and connected to the unselected thin film resistors as in the first embodiment. The fixed voltage supply pad and the disconnection voltage supply pad to be connected are opened by connecting them to the connection point A.
Since a predetermined potential of 1 to AA3 maintains a high level, the outputs of the inverters 5 to 6 which invert and output the voltage become a low level code signal, and these may be combined to generate a desired trimming code. .

[0057]

As described above, the code setting circuit of the present invention includes the second disconnection voltage supply pad and the second disconnection voltage supply pad between the series connection circuit including the first disconnection voltage supply pad and the thin film resistor and the ground potential. Since the n-channel transistor having the gate electrode connected to the power supply potential is inserted in series connection, the first disconnection voltage supply pad is set to a fixed voltage and the disconnection voltage pulse is applied from the external power supply to the second disconnection voltage supply pad. By absorbing the momentary high-voltage pulse generated when the
It is possible to prevent noise from entering the original code generator. In addition, a circuit configuration in which the n-channel transistor and the p-channel transistor, the fixed voltage supply terminal and the first disconnection voltage supply terminal, and the polarities of the fixed voltage and the disconnection voltage are all opposite polarities is also possible. It is possible to prevent noise from entering the code generator. Therefore, the level of the output of the code generator connected to the first disconnection voltage supply pad can be maintained constant, and this constant output is supplied to the decoder through the inverter.
The reliability of trimming can be improved.

[Brief description of drawings]

FIG. 1A is a circuit diagram showing a first embodiment of a code setting circuit of the present invention. FIG. 3B is a sectional view showing the structure of the main part of the code setting circuit in the first embodiment.

FIG. 2A is a circuit diagram showing a second embodiment of the code setting circuit of the present invention. FIG. 7B is a sectional view showing the structure of the main part of the code setting circuit in the second embodiment.

FIG. 3A is a circuit diagram showing a third embodiment of the code setting circuit of the present invention. FIG. 9B is a sectional view showing the structure of the main part of the code setting circuit in the third embodiment.

FIG. 4A is a circuit diagram showing a fourth embodiment of the code setting circuit of the present invention. FIG. 9B is a sectional view showing the structure of the main part of the code setting circuit in the fourth embodiment.

FIG. 5A is a circuit diagram showing an example for explaining an example of adjusting a voltage by a trimming code.
(B) is a circuit diagram showing an example of a conventional code setting circuit.

[Explanation of symbols]

 1 Decoder 2-7 Inverter 8-10 Fixed or cut voltage supply pad 11-13 Cut or fixed voltage supply pad 14-16 Thin film resistance P1-P6 p-channel type transistor N1-N6 n-channel type transistor

Claims (4)

[Claims] 1. A first cutting voltage supply pad to which a predetermined cutting voltage is supplied from the outside, and a selective insertion in response to the cutting voltage which is inserted between the first cutting voltage supply pad and a low voltage source. And a first thin film resistor for trimming the reference voltage, a first first conductivity type transistor and a first second conductivity type transistor connected in series between the high voltage source and the first cutting voltage supply pad. The inserted series connection circuit, the second first conductivity type transistor which is connected in parallel to the first first conductivity type transistor and which conducts with a predetermined control signal only when power is turned on, and the potential at the series connection point are A first inverter that inverts and outputs to the gate electrode of the first first conductivity type transistor, a second inverter that inverts and outputs the voltage at the series connection point as a code signal, and a second inverter of the second inverter. In a code setting circuit having a plurality of sets of decoders, each of which decodes an output as a predetermined code signal according to the presence or absence of the thin film resistor, a noise absorbing means for absorbing a noise pulse generated from an external power source when the thin film resistor is cut A code setting circuit characterized in that it is provided between a resistor and a low voltage source. 2. The noise absorbing means uses the first disconnection voltage supply pad as a fixed voltage supply pad fixed at a predetermined constant potential, and a second voltage supply pad is provided between the thin film resistor and the low potential power supply.
2. The code setting circuit according to claim 1, wherein the disconnection voltage supply pad and the second transistor of the second conductivity type are inserted in series and the gate electrode thereof is connected to the high potential voltage source. 3. The noise absorbing means includes the first and second noise absorbing means.
A parallel connection circuit composed of the first and second first conductivity type transistors and respective input terminals of the first and second inverters are directly connected to the fixed voltage supply pad without using a conductivity type transistor. The code setting circuit according to claim 2, wherein: 4. The first conductivity type transistor and the second conductivity type transistor are replaced with each other, and the fixed voltage supply pad and the second disconnection voltage supply pad are also replaced with each other, and these voltages are set. 4. The code setting circuit according to claim 1, wherein the voltage supplied to the supply pad is also a voltage having a predetermined opposite polarity.