JPH0834221B2 - Semiconductor device with current detection function - Google Patents

Description

The present invention relates to a semiconductor device having a current detection function of detecting a current flowing.

[Conventional technology]

For example, a vertical type MOSFET (Me
tal Oxide Semiconductor Field Effect Transistor)
Is shown in FIG. In the figure, the structure is such that an N ⁻ type silicon substrate 1a having a low impurity concentration is laminated on the upper surface of an N ⁺ type silicon substrate 1b having a high impurity concentration, and both are used as drains. Then, the P-type region 2 is diffused at a predetermined interval in a predetermined region in the N ⁻ type silicon substrate 1a,
It is electrically connected to the source electrode 7 and diffuses into the N ⁺ type region 3 having a relatively high impurity concentration. A gate electrode 6 made of polycrystalline silicon or the like is formed on at least a portion near the surface of the P type region 2 where the N ⁺ type region 3 is not formed as a channel portion 4 with an insulating film 5 made of SiO ₂ or the like interposed therebetween. ,
Insulating film 11 formed by oxidizing gate electrode 6
And the source electrode 7 made of an aluminum film or the like is formed on the surfaces of the N ⁺ type region 3, the P type region 2 and the interlayer insulating film 9.

Here, the drain current or the source current of this MOSFET (means the energization current.
In the prior art, a resistance for current detection is connected to the source electrode 7 and the drain current is detected from the voltage drop due to this resistance. This will be described with reference to FIGS. 4 and 5. MOSF as shown in FIG.
In an electric circuit as an example using ET, the source terminal S is connected to the ground g via the current detection resistor 57,
The drain current I _D is reduced by the current detection resistor 57 to the drop voltage V
It can be detected by _s9 . That is, (However, R ₅₇ is the resistance value of the current detection resistor 57.) The drain current I _D is obtained.

Next, the operation of FIG. 4 will be described with reference to the waveform chart shown in FIG. When the switch 51 is turned on and off in a certain cycle, the gate applied voltage V _G alternates between 0 and V ₁₀ (Fig. 5 (1)). When V _G = 0, the MOSFET 58 turns off and V _G = V _{At 10} o'clock, a conductive path is formed in the channel portion 4 and it turns on. This ON, OF
As shown in FIG. 5 (2), the drain current I _D flows through the inductance 54 as a load and the current detection resistor 57 by F. The waveform of the voltage drop V _s9 of the current detection resistor 57 (Fig. 5 (4)) and the waveform of the drain current I _D are shown in Fig. 5 (2) as shown in the proportional relationship associated with the equation (1). ，
(4) is similar, and it is understood that the drain current I _D can be detected. In FIG. 4, reference numeral 50 is a DC power source, and 52 is a resistor for reducing the gate applied voltage V _G to 0 when the switch 51 is open.

However, the current detecting resistor 57 as shown in FIG.
However, the conventional technique using the following has the following problems.

The resistor 57 is necessary for current detection, the size of the electronic device is correspondingly increased, the number of parts is increased, and the cost is increased.

The current detection resistor 57 needs to be cooled because Joule heat is generated.

Effective use of the power supply voltage is hindered by the voltage drop due to the current detection resistor 57.

In order to avoid the above-mentioned problem, conventionally, the drain current I _D is detected from the drain-source voltage V _DS by using the on-resistance of the MOSFET without using the current detection resistor. That is, However, R _DS is the on resistance (drain
Resistance between sources).

The drain current I _D is obtained by using the relationship of.

In Figure 5, the period between the drain and the source is on (e.g., t ₀ ~t _1), the waveform of the drain-source voltage V _DS of the waveform (FIG. 5 (3)) and the drain current I _D, ( 2)
As shown in the proportional relationship associated by the equation, it is understood that FIGS. 5 (2) and 5 (3) are similar, and the drain current I _D can be detected.

[Problems to be solved by the invention]

However, among the above-mentioned conventional techniques, the one using on-resistance has the following problems.

As shown in FIG. 5 (3), when the MOSFET 58 changes from ON to OFF (for example, time t ₁ ), a high voltage flyback pulse V _P due to the inductance 54 is generated.

As shown in FIG. 5C, the voltage V ₂₁ of the DC power supply 55 is applied to the value of the drain-source voltage V _DS when the MOSFET 58 is OFF (for example, t _{1 to} t ₂ ).

Due to the above problem, when the drain current I _D is 0, the drain-source voltage V _DS does not become 0, so that accurate detection cannot be performed. Moreover, high voltage flyback pulse
Since V _P is generated, in the worst case, there is a problem that the electric circuit for detecting V _DS is damaged.

Therefore, the present invention was devised in view of the above problems, and detects a detection signal according to the energized current when energized, and detects when deenergized without externally attaching a current detection resistor. An object of the present invention is to provide a semiconductor device having a current detection function such that a signal becomes 0.

[Means for solving problems]

In order to achieve the above object, a semiconductor device with a current detection function of the present invention is formed in a semiconductor substrate having a first conductivity type and electrically connected to a drain electrode, and in a predetermined region on the main surface side in the semiconductor substrate. Second conductivity type diffusion layer of the second conductivity type, and first conductivity type first layer formed in the second conductivity type diffusion layer
A conductive type diffusion layer, a source electrode electrically connected to the first conductive type diffusion layer and the second conductive type diffusion layer, and a predetermined distance from the second conductive type diffusion layer on the main surface side in the semiconductor substrate. A second-conductivity-type shield region formed by having a probe region, a first-conductivity-type probe region formed in the shield region, a probe electrode electrically connected to the probe region, and the first-conductivity-type diffuser. A layer, the second conductivity type diffusion layer, and an insulating film formed on the semiconductor substrate, and the first conductivity type diffusion layer formed on the insulation film and on the surface in the second conductivity type diffusion layer. Channels are simultaneously formed in the first channel region between the semiconductor substrate and the second channel region between the probe region and the semiconductor substrate on the surface in the shield region and facing the first channel region. The game to be formed And a potential detection circuit that is electrically connected to the probe electrode and that detects a potential of the semiconductor substrate according to the energizing current through the channel formed in the second channel region. .

〔Example〕

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. FIG. 1 shows a sectional view of a first embodiment in which the present invention is applied to a vertical MOSFET. In the figure, the MOSFET shown in FIG.
The same components as in FIG. In other symbols, 10 is an N ^- type silicon substrate 1a
Has a higher impurity concentration than the impurity concentration of, N between P-type region 2 ^- the -type silicon substrate 1a, or, N of the element perimeter ^- the -type silicon substrate 1a (FIG former) deep predetermined spreading the Is the probe region that is diffused. And this probe area
A probe electrode 8 made of an aluminum film or the like is formed so as to be electrically connected to 10. Therefore, since both of them are formed, the structure on the main surface is different from that of FIG. 3, and the gate electrode 6a has the insulating film 5a at least on the channel portion 4 on the probe region 10. The insulating film 11a and the interlayer insulating film 9a cover only those portions. The source electrode 7a is formed so as to be electrically insulated from the probe electrode 8. still,
The present invention is effective if the probe electrode 8 is formed even if the probe region 10 is not formed, but the contactability of the probe electrode 8 is improved by forming the probe region 10.

Next, how the drain current is detected by the MOSFET having the above structure will be described with reference to FIGS. 6 and 7. FIG. 6 shows an electric circuit diagram using the above MOSFET. In the figure,
The same components as those of the electric circuit diagram shown in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted. Reference numeral 59 is a symbol indicating the MOSFET of the present embodiment, which includes a drain D, a gate G, and a source S.
It has four terminals with a probe P newly added thereto, and the probe P means the probe electrode 8.

Next, the operation of the electric circuit in FIG. 6 will be described with reference to the waveform chart shown in FIG. At time t ₀ , switch 51 is OF
When F → ON, the gate applied voltage V _G shown in FIG. 7 (1) changes from 0 → V ₁₀ . Where V ₁₀ turns on MOSFET 59
The voltage is set high enough to cause the MOSFET 59 to change from OFF to ON at time t ₀ . The drain current _ID shown in FIG. 7 (2) becomes ₀ with the lapse of time after time t 0.
Monotonically increases from. In this embodiment, since the MOSFET 59 is an N-channel type, the carriers of the drain current _ID are electrons, and the electrons flow from the source terminal S to the drain terminal D. Focusing on this electron flow, in FIG. 1, the electrons flowing from the N ⁺ type region 3 into the channel portion 4 pass near the probe region 10 and pass through the N ⁻ type silicon substrate 1a and the N ⁺ type silicon substrate 1b. Reach drain D. Here, a voltage drop that occurs when electrons pass through the channel portion 4 appears as a potential difference V _PS between the probe region 10 and the N ⁺ type region 3. That is, the probe-source voltage V _PS is expressed by the following equation using the channel resistance R _ch and the drain current I _D.

V _PS = I _D × R _ch (3) Since the channel resistance R _ch is constant, V _PS is I _D
In proportion to, as shown in FIGS. 7 (2) and (4), the MOSFET
During the ON period of 59 (for example, t _{0 to} t ₁ ), the waveforms of V _PS and _ID are similar to each other. Therefore, if the probe-source voltage V _PS is measured, the drain current I _D can be detected using the equation (3).

When the switch 51 changes from ON to OFF at time t ₁ ,
The gate applied voltage V _G shown in FIG. 7 (1) changes from V ₁₀ → 0. In this embodiment, the MOSFET 59 is set to the enhancement type and is turned off when V _G = 0, so that the MOSFET 59 changes from ON to OFF at time t ₁ . As a result, the drain current I _D shown in FIG. 7 (2) has a maximum value I at time t ₁ .
After taking ₁₀ , it rapidly decreases to 0. At this time, the drain-source voltage V _DS shown in Fig. 7 (3) rises sharply from V _20, and after the flyback pulse V _P is generated, the DC power supply 55
The voltage drops to V ₂₁ and stabilizes. That is, the time t ₁ after the drain-source voltage V _DS becomes the voltage value higher, as shown in this case the first drawing, N ^- -type silicon substrate
A depletion layer 12 generated at the PN junction between 1a and the P-type region 2 mainly extends in the N ⁻ type silicon substrate 1a, and the depletion layer 12 electrically insulates the probe region 10 from the surroundings. Therefore, for example, the probe-source voltage V _PS shown in FIG. 7 (4) becomes 0 during the period of t _{1 to} t ₂ . Here, in order that the depletion layer 12 can completely cover the probe region 10, it is better to make the impurity concentration of the N ⁻ type silicon substrate 1a sufficiently low,
Further, as another consideration, the interval between the P-type regions 2 may be narrowed.

As described above, according to the first embodiment, the probe
Source voltage V _PS becomes faithful voltage proportional to the drain current I _D, the probe source by an insulating effect of the depletion layer 12 even when the drain current I _D is the voltage V _DS between the drain and source when the 0 is not 0 The inter-voltage V _PS becomes 0, and the drain current I _D can be accurately detected.

Next, FIG. 8 shows a sectional view of a second embodiment as an application of the first embodiment. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals as those in FIG. 1, and non-corresponding parts are indicated by new reference numerals. That is, the non-corresponding portion is the P-type region 2 on the surface of the N ^- type silicon substrate 1a in FIG.
The P-type shield region 13 is diffused at positions separated from each other, and the probe region 10 is formed in the P-type shield region 13. Then, the P-type shield region where the probe region 10 is not formed
13 A part near the surface is used as a probe channel portion 14, and a gate electrode 6a made of polycrystalline silicon or the like is extended on the probe channel portion 14 from above the channel portion 4 to above the probe channel portion 14 via an insulating film 5a made of SiO ₂ or the like. Together with P-type shield area
Shield electrode 15 made of aluminum film, etc. on the surface of 13
And a probe electrode 8a made of an aluminum film or the like is provided on the surface of the probe region 10 so that both electrodes are electrically insulated, and the shield electrode 15 is electrically connected to the source electrode 7a. Has been done. The P-type shield region 13 can be formed simultaneously with the P-type region 2 in the same diffusion process.

Also in the second embodiment, the same effect as the first embodiment can be obtained. The contents will be described with reference to FIGS. 6 to 8. However, the MOSFET 59 shown in FIG. 6 is the MOSFET of the second embodiment shown in FIG. Further, in the description of FIGS. 6 and 7, the description will be omitted while omitting the same parts as those of the first embodiment described above.

Similar to the first embodiment, the switch 51 is turned from OFF to ON at time t _0.
Changes to, the voltage V ₁₀ is applied to the gate electrode 6a and the MOS
The FET 59 is turned on, a conductive path is formed in the channel portion 4, and the drain current I _D starts to flow. In the MOSFET 59 shown in FIG. 8, the carrier of the drain current I _D is an electron, and this electron is
When it flows from the N ⁺ type region 3 into the channel portion 4, passes through the channel portion 4 and reaches the N ⁻ type silicon substrate 1a, the flow direction is changed to the direction of the N ⁺ type silicon substrate 1b immediately below the gate electrode 6a. And passes through the N ⁻ type silicon substrate 1a and the N ⁺ type silicon substrate 1b in sequence to reach the drain D.

Here, when the voltage V ₁₀ is applied to the gate electrode 6a, the gate electrode 6a is not limited to the channel 4 and the probe channel.
14 is also turned on, and the potential of the portion of the N ⁻ type silicon substrate 1a immediately below the gate electrode 6a can be detected by the probe region 10 via the probe channel 14. That is, the potential of the electrons flowing into the N ⁻ type silicon substrate 1a from the channel 4 can be detected in the probe region 10, and the voltage drop generated when the electrons pass through the channel 4 is the same as in the first embodiment described above. It appears as a potential difference V _PS between the probe region 10 and the N ⁺ type region 3, and the drain current I _D can be detected from V _PS .

Next, at time t ₁ , when the switch 51 changes from ON to OFF, the voltage applied to the gate electrode 6a becomes 0, and the MOSF
The ET59 is turned off and the conduction path of the channel portion 4 is extinguished so as not to be energized, so that the drain current I _D rapidly decreases and reaches 0.
Then after time t ₁ (t ₁ ~t ₂₎ is the drain current I _D is zero. Here, when the applied voltage to the gate electrode 6a becomes 0, the gate electrode 6a is not limited to the channel portion 4 and the probe channel.
14 also disappears the conductive path and does not energize. That is, during the period from t _{1 to} t ₂ , the probe region 10 is an N ⁻ type silicon substrate.
Loss the conductive path electrically connected to 1a, and the source electrode 7a (N ⁺
It is electrically insulated from the surroundings by the shield electrode 15 (P-type shield region 13) electrically connected to the mold region 3). As a result, the potential difference V _PS between the probe region 10 and the N ⁺ type region 3 becomes 0 during the period from t _{1 to} t ₂ as shown in FIG. 7 (4). Here, the probe region 10 is doubly insulated from the drain D by the depletion layer 12 and the P-type shield region 13.
Compared with the insulation using only the depletion layer 12 in the first embodiment described above, the insulation of the second embodiment can be made more reliably, and V _PS at t _{1 to} t ₂ can be made exactly 0. .

As described above, according to the second embodiment, the probe
Source voltage V _PS becomes faithful voltage proportional to the drain current I _D, the drain current I _D is 12 and the P-type shield region 13 the depletion layer even when the drain-source voltage V _DS is not 0 when 0 Due to the insulation effect, V _PS becomes 0, and the drain current I _D can be detected more accurately.

Further, in the second embodiment, since the shield electrode 15 is electrically connected to the source electrode 7a having the ground potential, the leakage current,
The influence of the drain potential due to the stray capacitance existing between the P-type shield region 13 and the drain D is bypassed by the electric path, and does not affect the plow electrode 8a. Therefore, high impedance (Hi
gh-Impedance) is also good and highly sensitive detection is possible. Also when not energized, the current passing path N ^-
In order to block the type silicon substrate 1a and the probe region 10,
Even when a flyback pulse is generated from the source electrode 7a or the drain electrode D, the potential detection circuit (not shown) can be protected. Further, since the channel portion 4 (first channel region) and the probe channel 14 (second channel region) face each other, the N ⁻ type silicon substrate 1a near the channel portion 4 through which the current actually passes is formed. It is possible to accurately detect the electric potential of 1 through the probe channel 14. In the second embodiment, the P-type shield region
13 can be formed in the same size as the P-type region 2 by the same diffusion process, but the size is not limited at all.

FIG. 2 shows a sectional view of a third embodiment in which the present invention is applied to a vertical bipolar transistor (hereinafter referred to as "BPT"). In the figure, in this embodiment, N ⁻ type and N ⁺ type silicon bases 1a and 1b are used as collectors, and P is electrically connected to a base electrode 6b at predetermined intervals in predetermined regions in the N ⁻ silicon base 1a.
The type region 2a is diffused to serve as a base, the emitter electrode 7b is electrically connected to the inside of the P type region 2, and the N ⁺ type region 3a having a relatively high impurity concentration is diffused to serve as an emitter.
Here, the thickness d'in the vicinity 4a of the surface of the P-type region 2a is less than or equal to the thickness d in the vicinity of the bottom for the reason described later. And P
Between the mold regions 2a N ^{− In the} type silicon substrate 1a or N ^{− in the} peripheral portion of the element
The probe region 10 is formed in the type silicon substrate 1a (in the figure, the former) with a predetermined diffusion depth, and has an impurity concentration higher than that of the N ⁻ type silicon substrate 1a. Further, the probe electrode 8 made of an aluminum film or the like is attached to the probe region 10 thereof.
Electrically connect to. Incidentally, 5b is an insulating film such as a Si oxide film.

Next, the manner of detecting the collector current (current flowing in the present invention) according to this embodiment will be described with reference to FIGS. 9 and 10. FIG. 9 is an electric circuit diagram to which the BPT of the third embodiment is applied, and the BPT is represented by the symbol 60. That is, it is a symbol of a semiconductor device having a collector C, a base B, an emitter E and four terminals to which a probe P is newly added, and the probe P means the probe electrode 8. The structure of the electric circuit shown in FIG. 9 is almost the same as the structure of the electric circuit of the first embodiment shown in FIG. 6 described above, and the portions corresponding to those in FIG. 6 are designated by the same reference numerals as those in FIG. The description is omitted. The only non-corresponding parts are that the MOSFET 59 of the first embodiment is changed to the BPT 60 of the third embodiment and that the base input resistor 61 is added.

FIG. 10 shows a waveform chart of each part in the above configuration. FIG. 10 is also the same as FIG. 7 of the waveform chart of each part of the first embodiment described above, except that the semiconductor device has been changed from the MOSFET 59 to the BPT 60 and the terminal names have been changed. In the MOSFET 59, the gate applied voltage V _{G is used} for control, whereas in the BPT 60, the base current I _{b is used} for control. In the description of FIG. 9 and FIG. 10, parts which are important with respect to the first embodiment described above are omitted, and particularly BPT6
0 of the probe-emitter voltage V _PE is the waveform shown in FIG. 10 (4), a similar to the waveform of the collector current I _C shown in FIG. 10 (2), the collector than the voltage V _PE between the probe and the emitter It will be described below that the current I _C can be detected.

In the BPT60 shown in FIG. 2, the electron as the carrier is N
Implanting from the ⁺ type region 3a to the P type region 2a, and N ⁻ type and N type
^{Reach +} type silicon substrates 1a and 1b. Here, the P-type region 2a
The thickness d'in the vicinity of the surface 4a is less than or equal to the thickness d in the vicinity of the bottom so that the current can easily flow in the vicinity of the surface 4a. Further, the thickness d near the bottom is designed thin to improve the characteristics of BPT. This is because the electrons flowing near the surface 4a are in the probe area.
This is because it passes the vicinity of 10. Then, by detecting the voltage drop due to the conductive resistance R _C (corresponding to the channel resistance R _ch in the first embodiment) near the surface 4a as the probe-emitter voltage V _PE , this probe
Since the emitter-to-emitter voltage V _PE follows the same relationship as the equation (3) of the first embodiment (V _PE = I _C × R _{C in} this embodiment), the probe-emitter voltage V _PE to the collector current I _C Can be detected. Further, when the BPT60 is OFF, the depletion layer 12 grows and electrically insulates the probe region 10 from the surroundings as shown in FIG.
V _PE becomes 0.

As described above, according to the third embodiment, the probe
Emitter voltage V _PE becomes a voltage proportional to the collector current I _C, V the insulating effect of any depletion layer 12 when the collector current I _C is non-zero collector-emitter voltage V _CE when the 0
There is an effect that _PE becomes 0 and an accurate collector current I _C can be detected.

In the third embodiment, the probe region 10 is set to the second
If the P-type shield region as shown in the embodiment is electrically insulated from the surroundings, more accurate collector current detection becomes possible.

Next, a specific configuration of a power transistor (for example, a power MOSFET) adopting the semiconductor device with a current detection function of the present invention and a signal processing circuit thereof will be described with reference to FIGS. 11 to 14.

FIG. 11 and FIG. 12 show an example thereof, which is an example incorporating a function of amplifying and outputting a signal of which current is detected by an operational amplifier. Then, FIG. 11 is a top view showing a specific arrangement of each element of this example, and FIG. 12 is an equivalent circuit diagram thereof.

As shown in the figure, power MOSFE is formed on the same semiconductor substrate 100.
A power control unit 110 in which T is formed and a signal processing unit 120 that amplifies the signal are arranged. Then, the probe electrode 113 having the structure as shown in FIG. 1 or FIG.
And the electric signal generated between the source electrode 111 and the source electrode 111 are input to the operational amplifier 121 via the load resistor 122, and the resistors 127 and 128 are connected.
It is amplified by the amplification factor determined by and output from the output terminal 129.

FIGS. 13 and 14 show another example.A current detection signal is amplified by an operational amplifier and output, and at the same time, it is compared with a set value by a comparator, and when the signal is larger than the set value, the element is prevented from being destroyed. For this reason, this is an example that incorporates a self-blocking function. Then, FIG. 13 is a plan view showing a specific arrangement of each element of this example, and FIG. 14 is an equivalent circuit thereof.

As shown in the figure, the power control unit 2 is provided on the same semiconductor substrate 200.
10 and a signal processing unit 220 that performs processing such as amplification and comparison of the signal are arranged.

Then, the electric signal generated between the probe electrode 213 and the source electrode 211 is input to the operational amplifier 221 and the comparator 222 via the load resistance 224.

The operational amplifier 221 is amplified by the amplification factor determined by the resistors 227 and 228 as in the above example, and is output from the output terminal 229. On the other hand, when the comparator 222 determines that the current value is larger than the current value set by the comparison voltage V _ref, the output of the comparator 222 changes from low level to high level, the MOS transistor 223 is turned on, and the power control unit 210 The gate electrode 212 is set to the ground potential to forcibly stop its operation to prevent destruction. Incidentally, FIGS. 11 to 14
In the figure, 112 is a gate electrode, and 114 and 214 are drain electrodes formed on the back surface of the semiconductor substrate.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. For example, in the first and second embodiments, the N-channel type is used, but the P-channel type is also applicable, and the insulating film 5a does not have to be an oxide (Oxide) but Si ₃
It may be a film made of another insulator (Insulator) such as N ₄ . In the third embodiment, the NPN type is used, but the PNP type is also applicable. In addition, a conductivity modulation type MOSFET in which the N ⁺ type silicon substrate 1b is changed to a P type silicon substrate (Japanese Patent Laid-Open No. 60-1969).
The present invention can also be applied to, for example, Japanese Patent Publication No. 74).

〔The invention's effect〕

Since the energized current is detected from the voltage between the drain electrode and the probe electrode, it is possible to output a detection signal proportional to the energized current when energized without externally attaching a current detection resistor. Since the current passage path and the probe current can be cut off during energization, the number of parts can be reduced, the cost can be reduced, and the size of the semiconductor device can be made relatively small.

Further, since the current passage path and the probe electrode are cut off when the power is not supplied, the potential detection circuit can be protected even when a flyback pulse is generated from the source electrode or the drain electrode.

Further, since the first channel region and the second channel region are opposed to each other, the potential of the semiconductor substrate in the vicinity of the first channel through which the current actually passes can be set to the channel formed in the second channel region. It is possible to detect it with high accuracy.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment in which the present invention is applied to a vertical MOSFET, FIG. 2 is a sectional view of a third embodiment in which the present invention is applied to a vertical bipolar transistor, and FIG. FIG. 4 is a sectional view of a vertical MOSFET of FIG. 4, FIG. 4 is an electric circuit diagram using the MOSFET in FIG. 3, FIG. 5 is a waveform diagram for explaining the operation of the electric circuit in FIG. 4, and FIG. And an electric circuit diagram using the MOSFET in FIG. 8, FIG. 7 is a waveform diagram for explaining the operation of the electric circuit in FIG. 6, and FIG. 8 is a sectional view of a second embodiment as an application of the first embodiment. FIG. 9 is an electric circuit diagram using the bipolar transistor in FIG.
FIG. 10 is a waveform diagram for explaining the operation of the electric circuit in FIG. 9, FIG. 11 is a top view of an example of a concrete configuration of the power transistor and its signal processing circuit, and FIG. 12 is an equivalent circuit in FIG. FIG. 13 is a top view of another example of the specific configuration of the power transistor and its signal processing circuit, and FIG.
It is an equivalent circuit diagram in the figure. 1a ... N ^- type silicon substrate, 1b ... N ⁺ type silicon substrate, 2 ...
… P type region, 3 …… N ⁺ type region, 4 …… Channel part, 5 …… Insulating film, 6a …… Gate electrode, 6b …… Base electrode, 7a …… Source electrode, 7b …… Emitter electrode, 8 ...... Probe electrode, 10 ...... Probe area, 12 ...... Depletion layer, 13 ...... P-type shield area, 14
...... Probe channel, 15 ...... Shield electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hirohiko Saito 1-1, Showa-cho, Kariya city, Aichi Prefecture Nihon Denso Co., Ltd. (72) Inventor Kunihiko Hara 1-1-cho, Showa town, Kariya city, Aichi Nidec Incorporated (56) References JP-A-53-94186 (JP, A) JP-A-58-223369 (JP, A)

Claims (4)

[Claims] 1. A semiconductor substrate having a first conductivity type and electrically connected to a drain electrode, and a second substrate formed in a predetermined region on the main surface side in the semiconductor substrate.
A conductive type second conductive type diffusion layer, a first conductive type first conductive type diffusion layer formed in the second conductive type diffusion layer, the first conductive type diffusion layer and the second conductive type diffusion layer A source electrode electrically connected to the layer, a second conductivity type shield region formed on the main surface side of the semiconductor substrate at a predetermined distance from the second conductivity type diffusion layer, and a shield region in the shield region. A first conductivity type probe region, a probe electrode electrically connected to the probe region, the first conductivity type diffusion layer, the second conductivity type diffusion layer, and an insulation formed on the semiconductor substrate. A film, a first channel region formed on the insulating film in the second conductivity type diffusion layer between the first conductivity type diffusion layer and the semiconductor substrate, and a surface in the shield region. Between the probe region and the semiconductor substrate, A gate electrode that forms a channel at the same time in a second channel region facing the first channel region, and a channel that is electrically connected to the probe electrode and is formed in the second channel region according to the conduction current. And a potential detecting circuit for detecting the potential of the semiconductor substrate. 2. The semiconductor substrate has a high-concentration impurity concentration, a high-concentration base layer electrically connected to the drain electrode, and a low-concentration impurity layer that is stacked on the high-concentration base layer and has at least one layer. The semiconductor device with a current detecting function according to claim 1, which is composed of a low-concentration base layer having a concentration. 3. The first channel region and the second channel region are formed adjacent to each other, and the gate electrode comprises:
The semiconductor device with a current detecting function according to claim 1, wherein the semiconductor device is formed over the first channel region and the second channel region. 4. The potential detection circuit comprises an operational amplifier having two input lines, one input line of the operational amplifier is electrically connected to the probe electrode, and the other input line is electrically connected to the source electrode. A semiconductor device with a current detection function according to any one of claims 1 to 3.