JPH08330596A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE: To improve the productivity of a thin film transistor, and increase the conductivity of an ion implantation film at a low temperature, by simultaneously performing crystallization and activation of a semiconductor film. CONSTITUTION: On an insulating substrate 1 like glass, an undoped amorphous silicon film, i.e., a-Si film 20 is deposited in an SiH4 -H2 -Ar atmosphere, and then patterned. On the insulating substrate 1 and the a-Si film 20, a gate insulating film 11 is deposited which is formed from TEOS by a plasma CVD method. After an N-type a-Si film 21 is deposited on the gate insulating film 11 above the central part of the a-Si film 20, an aperture 22 reaching the a-Si film 20 is formed in the gate insulating film 11 on the right and left of the N<+> a-Si film 21, by using HF aqueous solution buffered by ammonium fluoride. Phosphorus is ion-implanted in the N<+> a-Si film, and an N<+> implantation film 23 of amorphous crystal structure is formed in regions of a gate, a drain and a source. In order to reduce resistance, heat treatment is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a semiconductor device used in office automation equipment, measuring instruments and the like.

[0002]

2. Description of the Related Art A liquid crystal display device having improved contrast by using a field effect transistor is becoming mainstream.

FIG. 3 is a plan view of an active matrix type liquid crystal display device using field effect transistors.

As shown in FIG. 3, the insulating substrate 1 has a thickness of 5
A semiconductor film 2 made of non-doped polycrystalline silicon of 00Å is provided.

Further, on the semiconductor film 2, a gate 3 of a field effect transistor made of n ₊ -type polycrystalline silicon having a thickness of 900 Å is provided so as to divide the semiconductor film into two, with a gate insulating film interposed therebetween.

Further, a drain electrode 4 of the field effect transistor is formed on the left side of the gate and a source electrode 5 of the field effect transistor is formed on the left side of the gate, which is made of metal and has a thickness of 11000Å so as to contact both ends of the semiconductor film 2. Has been done.

A field effect transistor formed of such a thin film is called a thin film transistor because its constituent elements are thin films.

A gate line 6 for transmitting a scanning signal for switching the thin film transistor from the external circuit to the thin film transistor is connected to the gate 3, and a drain line 7 for transmitting a display signal controlled by the thin film transistor, which is a switch, to the thin film transistor is connected to the drain electrode 4. To
A transparent ITO display electrode 8 for applying a display signal passing through the thin film transistor to the liquid crystal is connected to the source electrode 5, respectively.

Generally, by providing the gate lines and the drain lines, the thin film transistors are arranged in a matrix on the insulating substrate.

Since the main point of the present invention is the heat treatment step,
For the sake of clarity, a cross-sectional view of one thin film transistor in which the thin films have a laminated structure is shown below.

FIG. 4 is a sectional view of the liquid crystal display device taken along line IV-IV in FIG.

In FIG. 4, a thickness 500 is formed on the insulating substrate 1.
Å The semiconductor film 2 made of non-doped polycrystalline silicon is provided.
And P (phosphorus) is applied to the left and right sides of the semiconductor film at 5 × 10, respectively.^Fifteen
cm ^-2Drain 9 and a low resistance
10 is provided.

The semiconductor film is crystallized by heat treatment to increase the crystallinity of the operating layer between the drain and the source and to activate the semiconductor layer to reduce the resistance of the drain and the source.

However, the crystallization step and the activation step are often performed separately to confirm whether each step is correct.

Returning to FIG. 4, the temperature of the semiconductor film 2 is 1000 ° C. for the thermal oxide film or 600 ° C. for the CVD film.
With a thickness of 1000Å made of silicon dioxide 1
1 is formed, and further, a gate 3 made of polycrystalline silicon is deposited on the gate insulating film 11 between the drain and the source by ion implantation of P (phosphorus) by 5 × 10 ¹⁵ cm ^−2. ing.

On the gate made of polycrystalline silicon, an interlayer insulating film 12 made of plasma nitride and made of silicon nitride and having a thickness of 1200 Å is formed as an insulating film between the gate line and the drain line. There is.

Further, the interlayer insulating film 12 having a slightly large unevenness.
A transparent ITO auxiliary capacitance electrode 13 with a thickness of 600 Å on top
Is a 1400Å-thick silicon oxide auxiliary capacitance insulating film 1
4 and the display electrode 8 having a thickness of 600Å.

Then, in the drain electrode 4 and the source electrode 5, the lower layer is made of titanium silicide (T
i: Si = 1: 1) and the upper layer has a two-layer structure of aluminum with a thickness of 10000Å.

Then, the drain electrode 4 and the source electrode 5
An alignment film 15 made of polyimide having a thickness of 2000 Å is formed on the top.

The alignment film 15 is a liquid crystal 16 having a thickness of 6 μm.
It is in direct contact with one of the interfaces.

Here, a transparent counter substrate 17 that faces the insulating substrate 1 with the liquid crystal 16 in between is provided.

ITO having a thickness of 1000 Å is formed on the counter substrate 17.
A counter electrode 18 made of polyimide and a counter alignment film 19 made of polyimide having a thickness of 1500 Å are laminated, and the counter alignment film 19 is in contact with the other interface of the liquid crystal.

When a nematic liquid crystal is actually used as the liquid crystal, a pair of polarizing plates is required on the outside, but it is omitted in FIG.

In FIG. 4, the heat treatment is mainly required for crystallization of the semiconductor film 2 and activation of impurities introduced into the drain 9, the source 10 and the gate 3. The manufacturing process of the field effect transistor until the gate of the above is activated will be described below.

FIG. 5 is a manufacturing process diagram of a conventional field effect transistor.

First, as shown in FIG. 5a, a transparent insulating substrate 1 made of quartz or the like and having a thickness of 500 at a temperature of 350.degree.
Å non-doped amorphous silicon film, that is, aS
The i film 20 is deposited by the plasma CVD method and then patterned.

Second, as shown in FIG. 5b, a-Si
The film is heat-treated at a temperature of 600 ° C. for 75 hours (hr) to be crystallized and converted into the semiconductor film 2 made of non-doped polycrystalline silicon.

Third, in FIG. 5c, the temperature 3 is applied on the insulating substrate 1 and the semiconductor film 2 made of polycrystalline silicon having a thickness of 500 Å.
A 1000 Å thick gate insulating film 11 made of TEOS is deposited at 00 ° C.

Fourth, as shown in FIG. 5d, after depositing an n ₊ -type n ₊ a-Si film 21 having a thickness of 900 Å on the gate insulating film 11 above the center of the semiconductor film 2 at a temperature of 350 ° C. ,
N ₊ a-S with HF aqueous solution buffered with ammonium fluoride
Openings 22 reaching the semiconductor film 2 are formed in the gate insulating film 11 on the left and right of the i film 21.

Fifth, as shown in FIG. 5e, a temperature of 4
P (phosphorus) is ion-implanted at an acceleration voltage of 30 keV at 00 ° C.
5x dose in the gate, drain and source regions
10 ^Fifteencm^-2The three n₊The injection film 23 is formed.

Sixth, as shown in FIG. 5f, in order to reduce the resistance of the n ₊ implantation film 23, the temperature is 600 ° C. and the time is 75.
When heat treatment is performed for a time (hr) to activate the implanted atoms, the n ₊ implantation film in the gate, drain and source regions is converted into a gate 3, a drain 9 and a source 10 having a surface resistance of 700Ω / □, respectively. It

As described above, if the crystallization and the activation of the semiconductor film are performed in different steps, the productivity of the thin film transistor is not improved.

Further, the surface of the polycrystalline silicon film forming the semiconductor film 2 of FIG. 5e has irregularities of about 500 Å,
Furthermore, the inside of the polycrystalline silicon film has many interface states due to crystal defects.

Therefore, due to the unevenness, the gate insulating film 11 is formed.
Is disturbed, leakage between the gate and drain of the field effect transistor is increased, and the number of carriers in the operating layer is influenced by the interface state.
In many cases, this caused a decrease in current and an increase in OFF current.

Although the above-mentioned conventional example is the field effect transistor, the same can be said for the bipolar transistor.

FIG. 6 is a plan view of the bipolar transistor.

In FIG. 6, a thickness 500 is formed on the insulating substrate 1.
An n ₋ type semiconductor film 2 of Å is formed, and a metal emitter electrode 24 and a collector electrode 25 are connected to the left and right of the semiconductor film.

A base film 26 made of p ₊ type polycrystalline silicon is formed so as to cross the semiconductor film 2, and is connected to a p type base provided in the semiconductor film.

Further, the base film 26 made of polycrystalline silicon is used.
A base electrode 27 made of metal is connected to.

It is necessary to activate more impurities in the bipolar transistor than in the case of the field effect transistor described above.

Therefore, the bipolar transistor of FIG. 6 is cut along the line VII-VII to be described below with a sectional view.

FIG. 7 is a sectional view of the bipolar transistor.

In FIG. 7, a semiconductor film 2 made of polycrystalline silicon having a thickness of 500 Å is formed on an insulating substrate 1, and an n ₊ type emitter 28 and a p type base 28 are arranged in the semiconductor film from the left side of the figure. 29, n ₋ type and n ₊ type collectors 30 are arranged.

Further, as shown in FIG. 7, a silicon dioxide base insulating film 31 formed on the semiconductor film by thermal CVD.
Is deposited, and the p ₊ -type base film 26 is a p-type base film 29.
You can only contact them.

Further, on the base film 26 having a thickness of 900Å or the base insulating film 31 having a thickness of 1000Å, an interlayer insulating film 12 made of silicon dioxide and having a thickness of 1200Å is formed by sputtering.

The base insulating film 31 and the interlayer insulating film 12 on the emitter 28 and the collector 30 are partially removed to form an opening, and the lower layer has a thickness of 10 from the formed two openings.
00Å molybdenum silicide, upper layer is 10000 thick
The emitter electrode 24 and the collector electrode 25, which are made of aluminum of Å, are connected to the emitter 28 and the collector 30, respectively.

Further, the interlayer insulating film 12 and the emitter electrode 24
A protective film 32 made of silicon dioxide and having a thickness of 5000Å is provided on the collector electrode 25 and for stabilizing the characteristics of the bipolar transistor.

Next, as in the case of the field effect transistor, the manufacturing process of the conventional bipolar transistor will be shown to point out the problem.

FIG. 8 is a manufacturing process diagram of a conventional bipolar transistor.

First, as shown in FIG. 8a, an n ₋ -type polycrystalline silicon film 33 having a thickness of 500 Å is deposited on a transparent insulating substrate 1 at a temperature of 400 ° C., and the polycrystalline silicon film is formed into a predetermined shape. To

Second, as shown in FIG. 8b, the temperature 600
The polycrystalline silicon film is heat-treated at 75 ° C. for 75 hours (hr) to crystallize the polycrystalline silicon film to form the n ₋ type semiconductor film 2.

Third, in FIG. 8c, the acceleration voltage is 30 ke.
V, by ion implantation at a temperature 400 ° C., in two positions of the left and right of the semiconductor film 2 a dose of 5 × 10 ¹⁵ cm ^{over 2} P (phosphorus)
The n ₊ layer 34 is formed having the, also forms a p layer 35 there a dose of 5 × 10 ¹³ cm ^-2 of B (boron) adjacent to the left of the n ₊ layer.

Fourth, as shown in FIG. 8d, the base insulating film 31 is formed on the semiconductor film and the insulating substrate at a temperature of 500 ° C., and the n ₊ film 34 and the p film 3 on the left and right of the semiconductor film are formed.
Three openings 22 are formed in the base insulating film 31 on the substrate 5.

Fifth, as shown in FIG. 8e, B having a thickness of 900Å is formed on the base insulating film 31 sandwiched between the left and right openings.
A p ₊ -type p ₊ polycrystalline silicon film 36 having (boron) is formed, and the p ₊ polycrystalline silicon film 36 and the p film 35 are brought into contact with each other through the central opening.

Sixthly, in FIG.
After holding for 5 hours, the impurities in the semiconductor film are activated, and the left n ₊ film 34 serves as the emitter 28, the p film 35 adjacent to the left n ₊ film 34 serves as the base 29, and the right n ₊ film 34 serves as the right n ₊ film 34. Collector 3
Convert to 0 respectively.

As shown in FIG. 8, if the crystallization and activation of the semiconductor film are performed in separate steps, there is a drawback that the productivity of the thin film transistor is not improved.

The surface of the polycrystalline silicon film forming the semiconductor film 2 of FIG. 8f has irregularities of about 500 Å,
Furthermore, the inside of the polycrystalline silicon film has many interface states due to crystal defects.

Therefore, the base insulating film 31 is formed due to the unevenness.
In many cases, the leakage current between the base and collector of the bipolar transistor is increased, and the number of carriers is influenced by the interface state, resulting in a decrease in ON current and an increase in OFF current of the bipolar transistor.

Alternatively, when the polycrystalline Si is ion-implanted, the implanted ions are less likely to be activated at a low temperature as compared with the case of ion-implanting a-Si, and the conductivity is lowered.

In the field effect transistor shown in FIG. 5 as well as the bipolar transistor shown in FIG. 8, crystallization of a semiconductor film such as an amorphous silicon film or a polycrystalline silicon film and activation of impurities introduced into the semiconductor film are performed separately. Therefore, the productivity of either the bipolar or field effect thin film transistor was extremely low.

[0061]

SUMMARY OF THE INVENTION It is an object of the present invention to shorten the total time required for crystallization and activation of a semiconductor film to improve the productivity of thin film transistors and to increase the conductivity of ion-implanted films at low temperatures. And

[0062]

A method of manufacturing a thin film transistor according to the present invention is a method of simultaneously crystallizing and activating a semiconductor film.

In the second method of manufacturing a thin film transistor of the present invention, the steps before crystallization and activation are performed at a temperature of 550 ° C.
After the following, temperature 550 ~ 600 ℃, time 5 ~ 10
This is a manufacturing method in which the semiconductor film is heat-treated at 0 hr.

Then, a third method of manufacturing a thin film transistor of the present invention is a method of converting a semiconductor film, which is an amorphous silicon film, into a polycrystalline silicon film by simultaneous crystallization and activation immediately after impurity implantation. .

[0065]

In the present invention, the crystallization and activation of the semiconductor film are performed at the same time, so that the time of the heat treatment step is halved.

As a result, not only a high yield of thin film transistors can be achieved due to the reduction in the number of steps, but also a semiconductor having almost no crystallinity is obtained as compared with the case where impurities are introduced into a semiconductor film having high crystallinity and then activated by heat treatment. In the case of crystallizing after introducing impurities into the film, the control of the resistance is easier, and thus the reproducibility and uniformity of the characteristics of the thin film transistor are improved.

This is interpreted as follows.

Activation means that injected atoms such as P and B enter the lattice points of Si as substitutional impurities due to thermal motion and covalently bond with surrounding Si atoms to generate one extra electron or hole. This is a phenomenon in which free electrons are generated to improve the conductivity of the injection film.

Therefore, when the heat treatment is carried out after implanting impurities into a-Si, the growth proceeds while incorporating P and B into the lattice points in the same manner as Si during crystal growth, so that crystallization and activation occur. It becomes a one-of-a-kind and easy to activate.

However, when impurities are implanted into crystalline Si (polycrystalline Si, single crystal Si), Si atoms on the crystal lattice are knocked on and knocked out of the lattice to become amorphous when implanted.

Therefore, due to the heat treatment, many defects are left in the crystal even if the crystal is re-crystallized after the implantation, and it is necessary to newly replace the Si atom with the impurity atom, so that crystallization (activation) occurs. ) Is inhibited, and activation is less likely to occur.

As a separate action, since the second method for manufacturing a thin film transistor of the present invention is a pretreatment step in which crystallization and activation are less likely to occur, not only the characteristics of the thin film transistor are unlikely to change due to differences in the previous steps. The interface between the semiconductor film and the gate insulating film becomes flat during crystallization.

On the other hand, in the third method of manufacturing a thin film transistor according to the present invention, the semiconductor film which is an amorphous silicon film is converted into a polycrystalline silicon film by the simultaneous progress of crystallization and activation immediately after the implantation of impurities. Is easy to control.

[0074]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a manufacturing process chart of a method for manufacturing a field effect transistor of the present invention.

FIG. 1 is characterized in that the number of steps is reduced by one as compared with the manufacturing process diagram of FIG. 5 of the prior art.

First, as shown in FIG. 1a, a non-doped amorphous silicon film having a thickness of 500 Å at a temperature of 400 ° C. in a SiH ₄ —H ₂ —Ar atmosphere on a transparent and insulating insulating substrate 1 such as glass, that is, Plasma C is applied to the a-Si film 20.
Patterning is performed after depositing by the VD method.

Second, referring to FIG. 1b, TEO was performed on the insulating substrate 1 and the a-Si film 20 having a thickness of 500 Å at a temperature of 400 ° C.
A 1000 Å thick gate insulating film 11 is deposited from S by plasma CVD.

Third, as shown in FIG. 1c, a-Si
A temperature of 400 ° C. is formed on the gate insulating film 11 above the center of the film 20.
After depositing an n ₊ -type n ₊ a-Si film 21 having a thickness of 900 Å, a n ₊ a solution is formed by using an HF aqueous solution buffered with ammonium fluoride.
The a-Si film 2 is formed on the left and right gate insulating films 11 of the -Si film 21.
An opening 22 reaching 0 is formed.

Fourth, as shown in FIG. 1d, temperature 4
P (phosphorus) is n ₊ a-Si at an acceleration voltage of 30 keV at 00 ° C.
Ion implantation into the film and the a-Si film under the opening to form a gate,
Dose amount 5 × 10 ¹⁵ cm ^{-2 in the} drain and source regions
Of three n ₊ injection films 23 are formed. At this time, the crystal structure of the n ₊ injection film 23 becomes amorphous.

Fifth, as shown in FIG. 1e, heat treatment is performed at a temperature of 600 ° C. for 75 hours (hr) in order to reduce the resistance of the n ₊ implantation film 23.

Then, between FIG. 1d and FIG. 1e, aS
At the same time as the i film 20 is crystallized and converted into the semiconductor film 2 made of polycrystalline silicon, the atoms implanted in the semiconductor are activated, and the n ₊ implantation films in the gate, drain and source regions are respectively formed. It is converted into a gate 3, a drain 9 and a source 10 having a surface resistance of 400Ω / □.

The injection film having a surface resistance of 400 Ω / □ at 75 hr is 2 kΩ / □ at 5 hr, and a surface resistance of 1 at 25 hr.
It becomes kΩ / □ and does not change much at 100 hours or more.

The sheet resistance 2 kΩ / □ is a sheet resistance selected so that the deformation of the signal passing through the field effect transistor does not adversely affect the image.

As described above, in the method of manufacturing the field effect transistor (FETr) of the present invention, the number of manufacturing steps is reduced because the crystallization and activation of the amorphous silicon film (a-Si film) are performed at the same time.

FIG. 2 is a manufacturing process diagram of a method for manufacturing a bipolar transistor of the present invention.

FIG. 2 is characterized in that the number of steps is reduced by one as compared with the manufacturing process chart of FIG. 8 of the prior art.

First, as shown in FIG. 2a, a non-doped a-Si film 20 having a thickness of 500Å is deposited on a transparent insulating substrate 1 at a temperature of 400 ° C. to form an amorphous silicon film into a predetermined shape.

Second, in FIG. 2b, the acceleration voltage is 30 ke.
By ion implantation at V and a temperature of 400 ° C., a dose amount of 5 × 10 ¹⁵ c is applied to the left and right two places of the non-doped a-Si film 20.
The n ₊ layer 34 having the P (phosphorus) of the ^m-2 form, also, a dose of 5 × 10 ¹³ cm ^-2 so as to be adjacent to the left of the n ₊ layer B
A p film 35 having (boron) is formed.

Third, as shown in FIG. 2c, TEOS was applied to the amorphous silicon film and the insulating substrate at a temperature of 4 ° C.
A base insulating film 31 is formed at 00 ° C., and three openings 22 are formed in the base insulating film 31 on the left and right n ₊ films 34 and p films 35 of the amorphous silicon film.

Fourth, as shown in FIG. 2d, B having a thickness of 900Å is formed on the base insulating film 31 sandwiched between the left and right openings.
Forming a p ₊ -type p ₊ a-Si film 37 with (boron),
The p ₊ a-Si film 37 and the p film 35 are brought into contact with each other through the central opening.

Fifth, in FIG.
It is kept for 5 hours to crystallize the amorphous silicon film and activate the impurities contained in the amorphous silicon film.

Then, the amorphous silicon film is crystallized and converted into the semiconductor film 2 made of polycrystalline silicon, and at the same time, the impurities in the amorphous silicon film are activated,
The n ₊ film 34 on the left is an emitter 28 with a surface resistance of 400Ω / □.
And the p-film 35 adjacent to the left n ₊ film 34 is the base 29.
On the right, the n ₊ film 34 on the right is a collector 3 with a surface resistance of 400Ω / □.
0, the p ₊ a-Si film 37 is converted into the base film 26 having a surface resistance of 600Ω / □.

Comparing FIG. 2 and FIG. 8, the 900 Ω / □ base film and the 700 Ω / □ emitter of the conventional manufacturing process of FIG. 8 are the same as the 600 Ω / □ base film of the manufacturing process of the present invention of FIG. It can be seen that the surface resistance of the emitter of 400 Ω / □ is improved.

This means that if the base film is connected between a plurality of bipolar transistors, the wiring resistance between the bipolar transistors can be reduced.

As described above, in the method of manufacturing the bipolar transistor (BiTr) of the present invention, the number of manufacturing steps is reduced because the amorphous silicon film is crystallized and activated at the same time.

[0096]

According to the method of manufacturing a thin film transistor of the present invention, since the semiconductor film is crystallized and activated at the same time, a high yield of the thin film transistor due to the reduction in the number of steps can be achieved, and the crystalline semiconductor can be obtained. Compared to the case where impurities are introduced into the film, the case where impurities are introduced into the amorphous semiconductor film makes it easier to control the resistance, and therefore the reproducibility and uniformity of the characteristics of the thin film transistor can be improved.

Further, as an individual effect, since the second method of manufacturing a thin film transistor of the present invention is a pretreatment process in which crystallization and activation are less likely to occur, characteristic changes of the thin film transistor occur due to temperature difference in the previous process. Not only is it difficult, but the interface between the semiconductor film and the gate insulating film becomes flat during crystallization, and the on / off ratio of the thin film transistor becomes high.As a result, when applying the thin film transistor to a liquid crystal display device, the screen of the liquid crystal display device is Can be sharpened.

On the other hand, in the third method of manufacturing a thin film transistor of the present invention, since the semiconductor film which is an amorphous silicon film is converted into a polycrystalline silicon film by simultaneous progress of crystallization and activation immediately after the impurity implantation, the wiring resistance is reduced. Is relatively low, and further, the liquid crystal display device can be made finer by a relatively low temperature process.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a field effect Tr of the present invention in which crystallization and activation are simultaneously performed.

FIG. 2 is a manufacturing process diagram of a bipolar Tr in which crystallization and activation are simultaneously performed according to the present invention.

FIG. 3 is a plan view of a liquid crystal display device.

FIG. 4 is a cross-sectional view of a liquid crystal display device using a field effect Tr.

FIG. 5: Conventional electric field effect T for performing crystallization and activation separately
It is a manufacturing-process figure of r.

FIG. 6 is a plan view of a bipolar Tr.

FIG. 7 is a cross-sectional view of a bipolar Tr.

FIG. 8 is a manufacturing process diagram of a bipolar Tr in which conventional crystallization and activation are separately performed.

[Explanation of symbols]

1 Insulating Substrate 2 Semiconductor Film 3 Gate 4 Drain Electrode 5 Source Electrode 6 Gate Line 7 Drain Line 8 Display Electrode 9 Drain 10 Source 11 Gate Insulating Film 12 Interlayer Insulating Film 13 Auxiliary Capacitance Electrode 14 Auxiliary Capacitance Insulating Film 15 Alignment Film 16 Liquid Crystal 17 Counter substrate 18 Counter electrode 19 Counter orientation film 20 a-Si film 21 n ₊ a-Si film 22 Opening 23 n ₊ Injection film 24 Emitter electrode 25 Collector electrode 26 Base film 27 Base electrode 28 Emitter 29 Base 30 Collector 31 Base insulating film 32 protective film 33 polycrystalline silicon film 34 n ₊ film 35 p film 36 p ₊ polycrystalline silicon film 37 p ₊ a-Si film

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/324 H01L 21/265 A 27/12

Claims (3)

[Claims] 1. A method of manufacturing a thin film transistor, which comprises simultaneously crystallizing and activating a semiconductor film. 2. The step before crystallization and activation is performed at a temperature of 550.
After the temperature is below ℃, the temperature is 550 to 600 ℃, the time is 5-1
The method of manufacturing a thin film transistor according to claim 1, wherein the semiconductor film is heat-treated at 00 hr. 3. The method of manufacturing a thin film transistor according to claim 1, wherein the semiconductor film, which is an amorphous silicon film, is converted into a polycrystalline silicon film by the simultaneous progress of crystallization and activation immediately after impurity implantation.