JPH08293862A - Charging system for data transmission - Google Patents

Abstract

PURPOSE: To improve the reliability of charging processing for data transmission. CONSTITUTION: A CF period abnormality detection circuit 60 is provided in a charging part 50. In the CF period abnormality detection circuit 60, a period storage memory 61 is provided with '27' as the pulse generation period of a cell frame signal CF in a normal state before software. Counters 62 and 63 are counted up by the clock signal of 9MHz to be utilized for charging processing and whenever the pulse of the cell frame signal CF is received, the counting value is reset. A comparing circuit 64 compares a value set by the period storage memory 61 and the counting values outputted by the counters 62 and 63. A flip-flop 65 takes in the output signal of the comparing circuit 64 with the timing with which the pulse of the cell frame signal CF is inputted and outputs it as information showing the normality/abnormality of the pulse generation period of the cell frame signal CF.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charging system for high speed data transmission, and more particularly to a charging system in SMDS.

[0002]

2. Description of the Related Art In recent years, as information processing apparatuses such as workstations and personal computers have become higher in performance, data transmission between these information processing apparatuses and data transmission between LANs accommodating those information processing apparatuses have become faster. Is required.

SMDS is known as one of the services for realizing high-speed data communication as described above. SMDS (Switch
ed Multi-megabit Data Service) is 1.5 Mbps or 45
It is a connectionless data exchange service based on the transfer rate of Mbps.

The ATM method is known as a method for realizing a high-bandwidth ISDN, and SMDS can be provided by using this ATM network. In this case, an SMDS processing device (SMDS message handler) is provided for a given ATM switch to accommodate SMDS subscribers and SMDS subscribers.
PVC (Permanent Virtual Circuit) is connected to the SMDS processor.
t or Permanent Virtual Channel), the connectionless data output from the SMDS subscriber is transferred to the SMDS processing device, and the processing device performs the routing process and the like.

Here, the connectionless data is
Generally, it is a variable length packet (variable length data frame), but since the above PVC is a path set up on the ATM network, connectionless data is converted into an ATM cell format before being input to the ATM switch ( Will be disassembled).
This cell is based on a 53-byte structure consisting of a 48-byte payload part and a 5-byte header part.

FIG. 15 schematically shows this data conversion. L3-PDU (Layer 3 protocol data
Unit) corresponds to the above connectionless data,
Destination address of the data DA (Destination Addres
s), a header part storing a source address SA (Source Address) and the like, and a payload part. The L2-PDU (Layer 2 Protocol Data Unit) corresponds to the above cell and is composed of BOM (first cell), COM (intermediate cell), and EOM (last cell). The source address SA and destination address DA of the connectionless data are stored in the BOM. Also, the number of COMs generated depends on the data length of the connectionless data. For the sake of simplicity, fixed-length cells are associated with L2-PDU and variable-length data frames are associated with L3-PDU.

When the data output from the SMDS subscriber and converted into the cell format is input to the SMDS processing device via the PVC set up on the ATM network, L3-P may be input as necessary.
It is assembled into a DU or higher layer data format, and routing information is analyzed and various checks are performed. After that, it is disassembled into cells again and is routed according to the above analyzed information.

[0008] The SMDS charging process is performed, for example, in the United States Be.
Technical Referenc issued by ll Communication Research
e TR-TSV-000775. In this billing process,
When data is transferred from the SMDS subscriber A to the SMDS subscriber B, the charging is performed at the data receiving side, that is, the SMDS processing device accommodating the SMDS subscriber B. Then, the following data is collected in the billing process. -Destination address DA (address of SMDS subscriber B) -Source address SA (address of SMDS subscriber A) -Carrier (from SMDS processor accommodating SMDS subscriber A)
Information identifying the communication service provider of the route to the SMDS processing unit accommodating SMDS subscriber B) SNI address (subscriber of SMDS subscriber B network interface address) segment count (of L2-PDU) Packet count (number of L3-PDUs) The SMDS processing device consists of a line unit that sends and receives cell format data and a common unit that monitors and controls the overall processing of the SMDS processing device. A billing unit is provided. When receiving the cell data, the line unit generates a cell frame signal having a pulse synchronized with the cell data and a cell enable signal indicating whether the cell data is a valid cell or an invalid cell, and outputs the signals. The data is transferred to the common unit in parallel with the cell data at a predetermined timing synchronized with the cell data.

The billing unit recognizes the cell data delimiter according to the cell frame signal, and also uses the cell frame signal as a refresh (switching) signal of the DRAM for billing data storage. In the charging process, when the cell enable signal indicates that the cell is a valid cell, the information stored in the valid cell (such as the information to be collected) is taken out.

[0010]

By the way, in the ATM network used by SMDS, data can be transferred at a desired rate, but either valid cells or invalid cells are transferred at regular intervals. Therefore, the line unit in the SMDS processor outputs a cell frame signal having a pulse at regular intervals according to the input of cells (including valid cells and invalid cells). Here, if the pulse period of the cell frame signal is disturbed or is not generated due to a failure in the line unit, the charging unit may not be able to perform the charging process.

For this reason, the SMDS processing device needs to monitor the pulse period and the disconnection state of the cell frame signal for billing processing, and when a failure is detected, it is necessary to perform processing corresponding to the failure. In the conventional SMDS processor,
Although it is known that a function of monitoring the disconnection state of the cell frame signal is provided, it does not have a function of monitoring the pulse cycle of the cell frame signal.

Further, as described above, when the cell enable signal indicates the valid state, the information stored in the cell is collected as billing data. For this reason, if the cell enable signal goes into the valid state even when a cell with an invalid cell or a cell containing a transmission error is input due to a failure in the line section, etc. There is a risk of being charged.

For this reason, the SMDS processing apparatus is required to take some measures in case of abnormality in the cell enable signal in order to improve the reliability of the charging processing. Was not provided with such a feature.

The problem concerning the reliability of the charging process is important not only to the communication service provider but also to the user. However, in the conventional SMDS charging process, it is assumed that the cell frame signal and the cell enable signal are normal. The check function and the fail-safe function when an abnormality occurs in these signals themselves are not always sufficient.

The above problem is not caused only by SMDS, but is common to systems that perform charging processing using timing information of transfer data or valid / invalid information of the transfer data.

An object of the present invention is to solve the above problems, and an object thereof is to improve the reliability of the charging system in data transmission.

[0017]

The means of the present invention will be described with reference to FIG. FIG. 1 (a) shows the first embodiment of the present invention.
It is a principle block diagram of the aspect (corresponding to the first embodiment). A first aspect of the present invention is premised on a billing system for data transmission in which a data unit is transferred at predetermined intervals and a billing process is performed using a timing signal generated for the data unit. Have.

The period detecting means 1 is a circuit for detecting the period of the timing signal, and is composed of, for example, a counter that counts up with a clock signal of a predetermined frequency and resets the count value each time the timing signal is received. The count value at reset is the cycle of the timing signal. Here, the data transmission method used an ATM network.
In the case of SMDS, the timing signal is a cell frame signal pulse.

The notifying means 2 compares the cycle detected by the cycle detecting means 1 with the cycle of the timing signal in the normal state, and notifies the processor controlling the billing process of the comparison result. The cycle of the timing signal in the normal state is set in advance. Further, when the comparison results do not match, the above notification is an abnormality occurrence notification.

The charging processing means 3 controls the charging processing in accordance with the notification from the notification means 2. That is, when the comparison results match, it is regarded as a normal state, and the billing data collection process and the like are performed. On the other hand, if the above comparison results do not match,
Considering that an abnormality has occurred, the processor that has received the abnormality notification activates a program that describes the processing when a failure occurs in the charging processing, and the charging processing means 3 executes the processing according to the instruction from the processor. .

FIG. 1B is a block diagram showing the principle of the second aspect of the present invention (corresponding to the second embodiment). A second aspect of the present invention is premised on a billing system for data transmission in which a billing process is executed for a data unit to be transferred when the data unit to be transferred contains valid data, and has the following means. In addition, the data transmission method is SMDS using ATM network.
, The cell enable signal indicates whether or not the transferred data unit contains valid data.

The extracting means 6 extracts predetermined information from the transferred data unit, for example, predetermined bits in the source address of the data unit. The notification means 7 compares the predetermined information extracted by the extraction means 6 with the predicted value of the predetermined information, and notifies the processor that controls the charging process of the comparison result. The predicted value of the predetermined information is set in advance. Further, when the comparison results do not match, the above notification is an abnormality occurrence notification.

The billing processing means 8 performs billing processing according to the notification from the notifying means 7. That is, when the transferred data unit contains valid data and the comparison results match, it is regarded as a normal state, and normal charging processing is performed. On the other hand, even if the data unit to be transferred contains valid data, if the comparison result does not match, it is considered as an abnormal state, and the processor notified of the abnormal state has a failure in the charging process. The program describing the processing when it occurs is started, and the billing processing means 8 executes the processing according to the instruction from the processor.

[0024]

In the billing system according to the first aspect of the present invention, when the cycle of the timing signal used for billing processing is disturbed, the above comparison result becomes inconsistent, and the notifying means 2 informs the processor for controlling the billing processing. Notify to that effect. When the processor recognizes the occurrence of the abnormal state by the notification,
The charging processing means 3 is instructed to perform processing corresponding to the abnormal state. The billing processing means 3 stops the billing process in accordance with an instruction from the processor, or switches the system when the system is configured as a duplex system. Thus, it is possible to prevent the charging process from being adversely affected by the disturbance of the cycle of the timing signal.

In the accounting method of the second aspect, the normality of data transfer is confirmed by comparing the predetermined information extracted from the transferred data unit with the predicted value of the predetermined information. Then, the billing processing means 8 performs billing processing only when the transferred data unit contains valid data and the comparison result is in agreement, and the transferred data unit contains valid data. Also in the above, if the comparison results do not match, it is considered that an abnormal state has occurred, and the processing corresponding to the failure occurrence is performed according to the instruction from the processor. The process corresponding to the occurrence of the failure is, for example, the stop of the charging process, the system switching, or the like. In this way, since it is determined whether or not to perform the charging process based on both the signal indicating the input of valid data and the comparison result, the reliability of the charging system for charging the valid data is improved. In particular, it is effective against a failure such that a signal indicating the input of valid data is generated on the charging unit side.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, SMDS using an ATM network will be described as an example of a connectionless data communication service.

First, a configuration common to the first and second embodiments of the present invention will be described. FIG. 2 is an overall schematic configuration diagram of the SMDS system. Line interface device 11
Inputs the data received from the subscriber to the ATM switch 12 and transfers the data output from the ATM switch 12 to a predetermined subscriber. In addition, the line interface device 1
When handling data in formats other than ATM cells, 1 performs format conversion between the data and ATM cells.
For example, when receiving connectionless data,
Conversion (disassembly / assembly) as shown in FIG. 15 is performed. The ATM switch 12 outputs the cell to a predetermined transfer destination according to the routing information added to each cell. The signaling devices 13 and 14 control the transfer of information between the ATM switch 12 and the call processors 17 and 18.

The main processor 15 is provided for the ATM switch 12, and the ATM switch 12 and the call processing processors 16 to 18, the signaling devices 13 and 14, the SMDS processing device 2 are provided.
0 and the like are comprehensively managed, and bandwidth management, failure monitoring, setting instructions for each device, and the like are performed. The call processor 16 sends and receives information to and from the main processor 15 and the SMDS processor 2
Initialization information and station data are transferred to 0, and SMDS
The failure of the processing device 20 is notified to the main processor 15. SM
The DS processing device 20 is a device that processes communication between SMDS subscribers, and its configuration and function will be described later.

FIG. 3 is a block diagram of a data transfer system between SMDS subscribers. Here, the SMDS subscriber A accommodated in the line circuit 11-1 is accommodated in the line circuit 11-2.
A case where connectionless data is transferred to the SMDS subscriber B will be described.

When the subscriber A transfers data to the subscriber B, the subscriber B terminal sets the address of the subscriber B as the destination address DA of the data in the terminal of the subscriber A.
The address of the subscriber A is set as the source address SA. Then, the data is transferred to the line interface device 1
Transfer to 1. The line interface device 11 is shown in FIG.
As shown in FIG. 5, the connectionless data is decomposed into cell format data, and the PVC (fixed path or semi-fixed path) 31 set between the line circuit 11-1 and the SMDS processing device 20 is designated. Identification information (VPI / VCI) is added to these cells and output to the ATM switch 12. At this time, the destination address DA and the source address SA are
The data length information stored in the (first cell) and representing the size of the connectionless data is stored in the EOM (last cell).

The transmission side line unit (SMLP) 21 receives the cell transferred from the line interface device 11 via the PVC 31, and based on the transmission destination address DA stored in the BOM, the subscriber B To the SMDS processing device (in FIG. 3, the SMDS processing device 20 in which subscriber A and subscriber B are both accommodated in the SMDS processing device 20). And SMDS accommodating subscriber B
Identification information designating the PVC 32 set between the processing device and each cell is added to each cell, and the cell is output to the ATM switch 12 again.

The receiving side line unit (RMLP) 22 receives the cell transferred from the transmitting side line unit 21 via the PVC 32, and based on the destination address DA, the destination subscriber (subscriber B). Include those cells when they are housed in themselves. Then, the PVC 33 set between the SMDS processing device 20 and the line circuit 11-2 accommodating the subscriber B is used.
The identification information designating the cell number is added to the cells and output to the ATM switch 12. The line interface device 11 is
When a cell is received from the receiving side line unit 22 via the PVC 33, connectionless data is assembled and transferred to the subscriber B.

The above-mentioned processing of the SMDS processor 20 is controlled by the cooperation between the common unit (COM) 23 and the processors 16 and 15 (call control processor 16 and main processor 15) provided in the SMDS processor 20. It

The billing process associated with the above-mentioned data transmission is performed on the called side. That is, the receiving side line unit 22 of the SMDS processing device 20 accommodating the subscriber B who is the destination subscriber.
And its common part 23 (indicated by diagonal lines in the figure).

FIG. 4 is a block diagram of the common unit 23 mainly showing the charging unit which is the main part of the present invention. When receiving the cell from the ATM switch 12, the receiving side line unit 22 generates a cell frame signal CF having a pulse at a timing synchronized with the cell data and transfers the cell frame signal CF to the common unit 23. Here, in the ATM network used by SMDS, when valid cells and invalid cells are combined, cells are transferred at regular intervals. Therefore, the receiving-side line unit 22 uses a cell frame signal having pulses at regular intervals in accordance with cell input. Output CF.

The receiving side line unit 22 also generates a cell enable signal CEN indicating whether the cell received from the ATM switch 12 is a valid cell or an invalid cell.
Specifically, it is a valid cell when the destination address DA is a subscriber accommodated in itself among the cells (excluding empty cells and error cells) that actually store the transfer data. As shown in FIG. 5, the receiving side line unit 22 transfers the cell frame signal CF and the cell enable signal CEN in parallel to the common unit 23 in synchronization with the cell data.

The common section 23 includes a traffic monitoring section 41,
It has a management unit 42 and a charging unit 50. The traffic monitoring unit 41 collects and monitors traffic information of cells detected by the transmission side line unit 21 or the reception side line unit 22. The billing unit 50 collects billing information and totals it at predetermined intervals. The management unit 42 notifies the call control processor of the collected information. The management unit 42 also generates a clock used in the common unit 23.

The charging unit 50 includes a CF disconnection detection circuit 51, a data extraction unit 52, a clock generation unit 56, a charging RAM 57-
1, 57-2 and MID holding unit 58. The CF disconnection detection circuit 51 will be described later.

The data extracting section 52 is provided in the receiving side line section 22.
Cell data CD according to the cell frame signal CF received from
It recognizes the 0-15 delimiter and also recognizes the status (BOM, COM, EOM) of each cell. First, BOM (first cell)
The destination address DA, source address SA, carrier information, etc. stored in the cell are extracted by the DA compression unit 5
3. The SA compression unit 54 and the SA / carrier compression unit 55 are used to compress the extracted information. This compression process is
The description is omitted because it is not directly related to the present invention. Then, the number of L3-PDUs is counted by receiving the EOM (last cell), and L2-P is calculated based on the data length information stored in the EOM.
Calculate the DU number. Then, these data are stored in the billing RAM 5
It is stored in 7-1 and 57-2. The clock generator 56
A 9 MHz clock signal is created from the clock generated by the management unit 42. Billing RAM 57-1, 57-2
Is provided with two memories having the same capacity, and is switched and used at predetermined time intervals. Then, at the time of switching, the accounting information data stored in the accounting RAMs 57-1 and 57-2 is notified to the processors 16 and 15 (or read by the processors). When the BOM is received, the MID holding unit 58 stores the identifier MID of the BOM, and holds it until the EOM having the same identifier MID is received. The identifier MID is an identifier given to each cell when one connectionless data is decomposed into a plurality of cells, and will be described later.

FIG. 5 is a timing chart of signals and clocks input to the common section 22. The cell frame signal CF, the cell enable signal CEN, and the cell data CD are synchronized with each other. The cell frame signal CF has an "L" level pulse at the timing of the beginning of each cell.
The cell enable signal CEN is a valid cell (in FIG. 5,
The “L” level is assigned to (indicated by diagonal lines) and the “H” level is assigned to invalid cells. The cell frame signal CF has a pulse generated at its head position regardless of whether the input cell is a valid cell or an invalid cell.

In the charging unit 50, each cell is processed in synchronization with the 9 MHz clock signal, but one cell is processed in 27 clocks. Therefore, the cell frame signal CF
, A pulse is generated every 27 clock time intervals, and the cell enable signal CEN is 27 for one valid cell.
It goes to "L" level only for the clock time. First Embodiment FIG. 6 is a block diagram of the first embodiment of the present invention. In the first embodiment, the charging unit 50 uses the cell frame signal CF
In order to check the normality of the CF disconnection detection circuit 51 and the CF cycle abnormality detection circuit 60.

The CF break detection circuit 51 has a one-shot pulse generation circuit 58. One-shot pulse generation circuit 5
The reference numeral 8 outputs a pulse having a pulse width determined by the constants of the resistor R and the capacitance C when the input of the rising edge or the falling edge is detected. Here, the resistance R and the capacitance C are set so that the output pulse width is the time corresponding to 30 cycles (30 clocks) of the 9 MHz clock signal, and the resistance R and the capacitance C are set to 30 each time the rising edge or the falling edge is detected. Outputs "L" pulses for the clock.

When the pulse of the cell frame signal CF is input to the CF disconnection detection circuit 51, the one-shot pulse generation circuit 58
Detects its rising edge and outputs an "L" pulse for 30 clocks. Therefore, in the normal state, the pulse of the cell frame signal CF is generated at predetermined intervals (27 clocks), so that the output of the one-shot pulse generation circuit 58 is always at the “L” level.

However, when the pulse of the cell frame signal CF is not input for 30 clock hours or more due to a failure in the receiving side line section 22, the output of the one-shot pulse generation circuit 58 becomes "H" level. . As described above, when the CF disconnection detection circuit 51 detects the “disconnection state” of the cell frame signal CF, the output thereof is set to the “H” level.

The CF cycle abnormality detection circuit 60 has a cycle storage memory 61, counters 62 and 63, a comparison circuit 64, and a flip-flop 65. “27” is set in the cycle storage memory 61 by the firmware of the charging unit 50 based on the pulse generation cycle of the cell frame signal CF being 27 clock times.

The counters 62 and 63 are 4-bit counters, and the cell frame signal CF is input to each load terminal L. Then, when the pulse of the cell frame signal CF is input, the counters 62 and 63 read the value “0” set in the data terminal D. That is, the count value is reset. The 9 MHz clock signal is input to the clock terminal CP of the counter 62, and the clock is incremented by this clock.
Then, a carry pulse is output at the 16th count. This carry pulse is input to the clock terminal CP of the counter 63 and increments the count value of the counter 63. That is, the counter 63 counts the upper bits of the counter 62. It should be noted that although two 4-bit counters are used in this embodiment, 1 having a large number of bits is used.
It may be composed of one counter.

The comparison circuit 64 compares the value set in the cycle storage memory 61 with the count value output by the counters 62 and 63. When the values do not match, the "H" level is output, and when the values match, "L" level is output.
Output level. That is, “2
Since "7" is set, the output of the comparison circuit 64 becomes "L" when the count values of the counters 62 and 63 become "27".

The flip-flop 65 receives the output signal of the comparison circuit 64 at its data terminal D. The cell frame signal CF is input to the clock terminal CP.
Therefore, the flip-flop 65 outputs the output signal of the comparison circuit 64 at the timing when the pulse of the cell frame signal CF is input to the OR circuit 66.

When the cell frame signal CF is in a normal state, the counters 62 and 63 count up the count value to "27" and then the cell frame signal CF.
The operation to be reset by the pulse of CF is repeated. That is, when the pulse of the cell frame signal CF is input, the count values of the counters 62 and 63 are “27”.
And the output of the comparison circuit 64 becomes "L". And
At this timing, the flip-flop 65 is driven by the cell frame signal CF of the clock terminal CP of the flip-flop 65.
(CF cycle abnormality detection circuit 60) outputs the "L" level.

On the other hand, if the interval at which the pulse of the cell frame signal CF is generated is deviated due to a failure in the receiving side line section 22, the CF cycle abnormality detection circuit 60 outputs the "H" level. That is, the interval at which the pulse of the cell frame signal CF is generated is shortened. For example, if the next pulse is input at the 26th clock, the count values of the counters 62 and 63 are reset at the time point when the count value is increased to "26". , The comparison result of the comparison circuit 64 does not match, the comparison circuit 64 does not become the “L” level and continues to output the “H” level. At this time, since the pulse is input to the flip-flop 65 at the 26th clock, the CF cycle abnormality detection circuit 60 outputs the “H” level. Further, the interval at which the pulse of the cell frame signal CF is generated becomes long, and for example, if the next pulse is input at the 28th clock, the count values of the counters 62 and 63 are counted up to "28", so the comparison circuit 64 Output becomes "L" level once at the 27th clock and then becomes "H" level at the 28th clock, and the flip-flop 65 reads the "H" level which is the output of the comparison circuit 64 at the 28th clock. Therefore, the output of the CF cycle abnormality detection circuit 60 also becomes "H" level.

Thus, the CF cycle abnormality detection circuit 60 is
When the "cycle shift" of the cell frame signal CF is detected, its output is set to "H" level. CF break detection circuit 51 and CF
The outputs of the cycle abnormality detection circuit 60 are the OR circuits 66, respectively.
Is input to Therefore, the CF disconnection detection circuit 51 and the CF
When at least one of the cycle abnormality detection circuits 60 detects an abnormal state, the output of the OR circuit 66 becomes the “H” level, which causes the charging section 50 to notify the CF abnormality. The OR circuit 66 may not be provided and the outputs of the CF disconnection detection circuit 51 and the CF cycle abnormality detection circuit 60 may be used as independent abnormality notification signals.

By the way, as described above, the cell frame signal CF is used by the charging unit 50 to recognize the division (timing) of the cell data, and the charging RA is used.
Since it is also used as a refresh signal for the DRAM used as M, if the pulse cycle of this signal is shifted, the billing process may become inaccurate. According to the first embodiment of the present invention, the reliability is improved by preventing inaccurate billing processing when the pulse cycle of the cell frame signal CF is deviated. Second Embodiment FIG. 7 is a block diagram of the second embodiment of the present invention. In the second embodiment, the charging unit 50 uses the cell enable signal.
The SA abnormality detection circuit 70 is provided in order to increase the reliability of the charging process in consideration of the case where an abnormality occurs in CEN. The SA abnormality detection circuit 70 includes an SA setting unit 71, an extracted SA holding unit 72,
It has a comparison circuit 73 and an abnormality determination unit 74.

The SA setting unit 71 stores the predicted value of the source address SA which is software set by the firmware of the charging unit 50. The extraction SA holding unit 72 is a data extraction unit 52.
The source address SA (source address SA stored in the first cell BOM) extracted from the input cell is stored. The comparison circuit 73 includes an SA setting unit 71 and an extraction SA.
The two source addresses SA stored in the holding unit 72 are compared, and the comparison result is notified to the abnormality determination unit 74. The abnormality determination unit 74 receives the BOM detection signal from the data extraction unit 52 together with the cell frame signal CF and the cell enable signal CEN. Then, when the abnormality determination unit 74 recognizes that the BOM (leading cell) is input from the detection signal, it determines the SA abnormality based on the comparison result by the comparison circuit 73 at that time.

Here, the format of the source address SA in the SMDS will be described with reference to FIG. As shown in FIG. 8 (a), the SMDS transmission source address SA is a total of 64-bit information composed of a 4-bit address type and a 60-bit address. The address type is
Currently, it is set to "1100" for all SMDS data communications. The first 4 bits of the address currently contain all
It is set to "0001" in SMDS data communication. Following the first 4 bits, a 40-bit real address corresponding to the telephone number of the sender subscriber is set, and at the end, 16 bits in which all values are fixed to "1" are set.

Thus, the source address SA of SMDS is
Currently, the leading 8 bits and the trailing 16 bits have fixed values, so the source address of the transfer data
The head 8 bits and the tail 16 bits of the SA can be predicted in advance on the receiving side. Therefore, the receiving side prepares the first 8 bits or the last 16 bits of this source address SA, and the source address extracted from the transfer data.
By comparing with the corresponding bit of SA, it is possible to check whether or not the data is transferred normally.

Returning to FIG. The SA setting unit 71 considers the format of the source address SA, and considers the source address.
Set "11000001" as the predicted value of the upper 8 bits of SA. In addition, the data extraction unit 52 uses the BOM in the input data.
The source address SA stored in (first cell) is extracted and transferred to the extracted SA holding unit 72. Then, the comparison circuit 7
3 is the source address SA set in the SA setting unit 71
The predicted value of the upper 8 bits of the above is compared with the upper 8 bits of the source address SA stored in the extracted SA holding unit 72, and the comparison result (match / mismatch) is notified to the abnormality determination unit 74. Here, if they match, it is considered that the data has been transferred normally, and if they do not match, it is considered that an error has occurred in the data transfer.

By the way, the following two are considered as abnormal states regarding the cell enable signal CEN. The first abnormal state is a fault in which the cell enable signal CEN becomes "L" level indicating the input of a valid cell although the valid cell is not actually input. In this case, the charging process may be executed based on the reception of the wrong cell enable signal CEN, and the wrong subscriber may be charged. Contrary to the first abnormal state, the second abnormal state is a fault in which the cell enable signal CEN becomes the "H" level indicating the input of the invalid cell although the valid cell is actually input. In this case, it may not be possible to charge the subscriber who actually transferred the data. In order to detect such an abnormal state, the circuit shown in FIG. 9 is provided in the abnormality judging section 74.

FIG. 9 is a circuit diagram of a main part of the abnormality judging section 74. In the figure, the exclusive OR circuit 75 receives the cell enable signal CEN and the comparison result signal from the comparison circuit 73. Here, the comparison result signal is "0" when the comparison results in the comparison circuit 73 match, and "1" when they do not match. The BOM detection signal is input to the clock terminals CP of the flip-flops 76 and 77,
The flip-flop 76 fetches the output data of the exclusive OR circuit 75 at the timing synchronized with the input of BOM (first cell), and the flip-flop 77 fetches the comparison result signal at the timing synchronized with the input of BOM.

In the above structure, first, in the normal state,
Cell enable signal when BOM (first cell) is input
CEN becomes “0” indicating that it is a valid cell. Also,
Since the upper 8 bits of the source address SA stored in the BOM and the upper 8 bits of the source address SA stored in the SA setting unit 71 match, the comparison result signal also becomes “0”. Therefore, the output of the exclusive OR circuit 75 becomes "0", and the output of the flip-flop 76 also becomes "0: normal". After this, COM (intermediate cell) and EO following the BOM above
Cell enable signal when M (last cell) is input
If CEN indicates valid cells, charging is performed for those cells.

As described above, the charging unit 50 of the second embodiment.
Does not perform charging processing only when the cell enable signal CEN is a valid cell, and the cell enable signal CEN is a valid cell and at the same time, the BOM
If the upper 8 bits of the transmission source address SA of the transfer data stored in the BOM match the preset predicted value, the billing process is performed on the message to which the BOM belongs.
The message to which the BOM belongs is, for example, 1 shown in FIG.
It means one connectionless data, and collects and aggregates the source address SA, the destination address DA, the carrier information, the data length information, etc., which are stored in the cell obtained by disassembling the connectionless data. This processing is performed by the data extraction unit 52 when the output of the flip-flop 76 becomes "0: normal".

When one connectionless data is decomposed into a plurality of cells, a common identifier MID (Message Identif
ier) is given. Then, when the BOM is received, the cell enable signal CEN is in a state indicating that it is a valid cell, and the source address stored in the BOM is set.
If the value of the upper 8 bits of SA matches the predicted value,
The billing unit 50 extracts the billing information stored in the BOM and holds the assigned identifier MID.
Then, after that, when the COM and EOM to which the same identifier MID is given is received, the billing information is extracted as necessary. In this way, charging is performed for each connectionless data, that is, for each identifier MID.

Here, the relationship between connectionless data and cells and the connectionless communication protocol will be described. The services provided in the respective embodiments of the present invention are targeted for, for example, SMDS which transfers connectionless data communicated by a LAN user on the ATM network. This connectionless data communication is an upper layer of the ATM layer. AAL (ATM Adaptation Layer) Type 3 /
4 is used. AAL Type 3/4 provides variable speed, non-timed transfer of various normal data communications to upper layers between source and destination. In addition, AAL type 3/4 is AAL-SDU (AAL
Service Data Unit) from one AAL-SAP to one or more AAL-SAP. AAL user (upper layer)
Can select the AAL-SAP associated with the QOS such as the delay and loss required to send the AAL-SDU. Also, one AT
By setting multiple AAL connections for M layer connections, multiplexing in the adaptation layer can be realized.

The AAL type 3/4 protocol has a three-layer structure. FIG. 10 shows the relationship between the PDU (protocol data unit), header, and trailer of each layer. Further, FIG. 11 shows the format of three layers of the AAL type 3/4 common part.

Each cell (SAR-PDU in FIG. 10) has its own BOM, COM, EO according to the segment type display.
Displays whether it is M or SSM. BOM, COM, EOM
Are the first cell, the intermediate cell, and the last cell, respectively, as described above, and the SSM is a single segment message indicating that the cell is converted into only one cell when one connectionless data is decomposed. Is. In addition, each cell has a SAR-PDU payload length display.
SAR-PDU Displays the number of octets of SAR-SDU information in the payload.

In FIG. 10, the connectionless data of this embodiment corresponds to CPCS-PDU (CS common part protocol data unit) or the data of its upper layer. In addition, data simply described as a cell in this embodiment is SAR-PDU.
(Cell disassembly / assembly sublayer protocol data unit). And connectionless data (CP
CS-PDU) is one or more disassembled cells (SAR-PD).
It is stored in the payload part of U). In addition, each cell (SAR-
PDU) is stored and transferred in the payload section (ATM-SDU) of the ATM cell in the ATM network.

One connectionless data (CPCS-PD
When U) is decomposed into one or more cells (SAR-PDU), the same MID (message identifier or multiple identifier) is displayed in each cell. And using this MID, a single
It provides multiplexing and demultiplexing of multiple connectionless data (CPCS-PDU) at the same time on the ATM connection. A cell interleaved connectionless server can be realized by using this function.

Next, the communication protocol for connectionless data will be described. As a form of providing connectionless data service via B-ISDN, as in the case of communication within the local area network LAN, there are an indirect providing method and a direct providing method depending on the place where the connectionless service function is installed. There is. Recommendation I. 364 defines a method and protocol for providing a broadband connectionless data service via B-ISDN.

The functions of the physical layer and the ATM layer are the same as those of other communications, and are treated the same as the ATM cell by the ATM node. As the adaptation layer, AAL type 3/4 that uses the message identifier MID is used.

Generally, in communication between computers (communication between LANs), a considerably long message (SC-PDU) is transferred, but as shown in FIG. 11, one SC-PDU is divided into cell units, and SAR-PDU is divided. Since the same MID is given to each, it is possible to distinguish from different SC-PDU, and one AT
Multiple communication can be performed by performing cell interleaving of multiple SC-PDUs on the M connection. In addition, by providing a pipelining function in the streaming service mode, a stage in which a part of transfer messages is accumulated in cell units without waiting for one transfer message to be accumulated in each connectionless service function (CLSF) With the method of successively transferring to the next transfer destination, many messages can be highly multiplexed with low delay.

A connectionless protocol on the adaptation layer (that is, a higher-level protocol of AAL type 3/4) is called a connectionless network access protocol (CLNAP). This protocol is terminated by the connectionless service function, and the routing process is performed by referring to the destination address and the source address set for each message.

The ATM layer, AAL type 3/4, and CLNAP protocols correspond to the LAN media access control (MAC) layer in the end-to-end protocol stack. The difference from MAC is in its address and routing. The MAC in the LAN has various media control formats such as CSMA / CD and token ring, but basically the routing is performed by the device-specific MAC address assigned to each node. On the other hand, ATM
Layer, AAL type 3/4 and CLNAP protocols,
Routing is performed by an ISDN number (public network number based on Recommendation E.164) that is independent of the equipment, and ISDN is sent from the terminal.
The entire network looks as if it were one wide area LAN.

As the upper layer of CLNAP, a logical link control (LLC) which is a layer 2 protocol of LAN is arranged, and an LLC link is established between both terminals (routers). That is, the B-ISDN network is treated as one sub-network from the entire LAN network. The routing protocol of the router on the sending side transfers (encapsulates) the packet that should be transferred to the LAN on the receiving side without processing, and sends it out to the B-ISDN network via LLC. Sub-network access protocol (SNAP) is a protocol that performs such encapsulation.

The protocol for communication using SMDS (DQDB is also the same) is almost the same as the above-mentioned B-ISDN. Both protocol stacks do not correspond one-to-one, but the physical layer of SMDS corresponds to the physical layer of B-ISDN above, and the level 2 of subscriber interface protocol SIP of SMDS above is the ATM layer of B-ISDN above. And AAL type 3 /
Corresponding to 4 SAR, SMDS SIP level 3 is above B-ISDN.
Equivalent to AAL type 3/4 CPCS and CLNAP.

The difference between SMDS and B-ISDN (ATM) is that ATM performs flow control from the terminal to the network at the layer for cell transfer and slot transfer, whereas SMDS allows access to distributed media. Take control. Same as AAL type 3/4 and essentially SMDS. In addition, the connectionless network access protocol (CLNA
P) and SMDS subscriber interface protocol SIP level 3 are basically the same.

As described above, the SMDS defines communication by a protocol equivalent to AAL type 3/4, and when transferring connectionless data through the ATM network,
The MID added to each cell that decomposes the connectionless data identifies it from other connectionless data. Then, this MID can be used to charge for each connectionless data.

Returning to FIG. When the first abnormal state occurs, the cell enable signal CEN indicates that the cell is a valid cell, but since the valid cell is not actually input, the data extraction unit 52 extracts the source address SA. Therefore, the comparison result of the comparison circuit 73 becomes “mismatch”. Therefore, the abnormality determination unit 74 outputs “1:” from the comparison circuit 73.
"Mismatch" is received. In other words, the abnormality determination unit 74 is
Since "0: Match" is not received from the comparison circuit 73, the charging process is not started. In this way, when the first abnormal condition occurs, the cell enable signal CEN indicates that the cell is valid, but the BOM storing the source address SA (the upper 8 bits is "11000001") is received. I don't
The charging process is not performed, and the charging process is not executed based on the reception of the incorrect cell enable signal CEN to collect the incorrect charging information. Then, the abnormality determination unit 74 issues an SA abnormality notification. This notification is forwarded to the main processor 15 via the call control processor 16.

When the second abnormal condition occurs, assuming that there is no error in data transfer, when the BOM is received, the upper 8 bits of the source address SA stored in the BOM are received.
Source address whose bits are stored in the SA setting unit 71
Since the predicted value of the upper 8 bits of SA matches, the abnormality determination unit 74 receives “0: match” from the comparison circuit 73. However, since the cell enable signal CEN indicates the invalid cell state, the output of the flip-flop 76 becomes "1: abnormal". On the other hand, the flip-flop 77 outputs the comparison result signal “0” received from the comparison circuit 73 as it is. Therefore, the charging unit 50 causes the flip-flop 76 to
It is possible to recognize that some kind of abnormality has occurred by the output of, and it is possible to recognize that the type of the abnormality is CEN abnormality by the output of the flip-flop 77. Then, the abnormality determination unit 74 issues a CEN abnormality notification. This notification is forwarded to the main processor 15 via the call control processor 16.

When the cell enable signal CEN indicates an invalid cell and the comparison result by the comparison circuit 73 is "mismatch", the output of the exclusive OR circuit 75 is "0". However, the upper 8 bits of the source address SA extracted from the transfer data and the predicted source address
Since it does not match that of the SA, the billing process will not be started and incorrect billing will not occur.

FIG. 12 is a diagram showing another structure of the second embodiment. The configuration shown in the figure corresponds to a system conforming to one embodiment of the SMDS processing system. In this method, when cells are transferred between SMDS processors (in FIG. 3,
When transferring from the transmission side line unit 21 to the reception side line unit 22 via the PVC 32), as shown in FIG.
(First cell) is converted to INT-BOM and SIP-BOM. The source address SA stored in the BOM before conversion is stored in the INT-BOM, and the carrier information indicating the route through which the transfer data has passed is stored. on the other hand,
The destination address DA is stored in the SIP-BOM. Also, CO
M (intermediate cell) and EOM (final cell) remain unchanged, and data length information is stored in EOM.

The charging unit 50 shown in FIG. 12 uses the cell data CD together with the cell frame signal CF and the cell enable signal CEN.
When 0-15 is received from the reception side line unit 22, the cell division extraction unit 81 recognizes the type of each cell, INT-BOM, SIP-BO
Transfer M and EOM to the billing data collection unit 82. The billing data collection unit 82 extracts the source address SA, the carrier information, the destination address DA, the data length information, the identifier MID, etc. from the received cell as billing-related information, and the DA compression unit 83, the SA compression unit 84, The compression processing by the SA / carrier compression unit 85 and the L2-PDU and L3-P by the charging processing unit 86
The number of DUs is calculated and stored as billing data. This billing data is processed for each identifier MID stored in the MID holding unit 87. The cell division extraction unit 81 and the billing data collection unit 82 correspond to the data extraction unit 52 of FIG.

The charging section 50 shown in FIG. 12 has an SA abnormality detection circuit 90. In the SA abnormality detection circuit 90, INT-
The normality of the transfer data is confirmed by comparing the upper 8 bits of the source address SA stored in the BOM with the preset higher 8 bits of the predicted value of the source address SA.

That is, the firmware of the charging unit 50 sets "1" as the predicted value of the upper 8 bits of the transmission source address SA.
1000001 "is set in the temporary storage memory 91, and the value is further stored in the SA high-order 8-bit holding unit 92. Further, the SA high-order 8-bit extraction unit 93 is set by the cell division extraction unit 81 to IN
When the source address SA retrieved from the T-BOM is received,
The upper 8 bits are extracted and notified to the comparison circuit 94.
The comparison circuit 94 compares the value received from the SA high-order 8-bit extraction unit 93 with the predicted value preset in the SA high-order 8-bit holding unit 92, and the comparison result (match / mismatch) is flip-flop 95. Input to the data terminal D of.

The timing controller 88 outputs a pulse when the INT-BOM is detected in the state where the cell enable signal CEN indicates a valid cell. Flip-flop 95
When the pulse from the timing control unit 88 is received at the clock terminal CP, the comparison circuit 94 at that timing
The result of comparison is fetched and output from the Q terminal. That is, the flip-flop 95 outputs the comparison result of the higher 8 bits of the source address SA extracted from the input INT-BOM and its predicted value in synchronization with the input timing of the INT-BOM. When the output of the flip-flop 95 (the output of the SA abnormality detection circuit 90) indicates "mismatch", the output is notified to the call control processor or the main processor as an SA abnormality notification (or CEN abnormality notification). Then, the processors recognize the failure state and execute the processing corresponding to the failure.

According to the above configuration, the cell enable signal CE
Even when a state indicating a valid cell as N is input to the charging unit 50, if the source address SA of the transfer data at that time does not match the predicted value, the charging process is not performed, so incorrect charging may be performed. Can be prevented and reliability is improved.

In the second embodiment, the normality of data transfer is judged based on the result of comparison between the upper 8 bits of the source address SA extracted from the input data and its predicted value, and the charging process is performed. However, the present invention is not limited to this, and any predictable bit can be used. For example, upper 4 bits or lower 16 bits of the source address SA may be used. Further, the destination address DA may be used instead of the source address SA. SM
The destination address DA of the DS has the configuration shown in FIG. 8 (b),
Even in this address, the predetermined bits are fixed,
It is predictable on the receiving side.

Next, a method of notifying at the time of failure common to the first and second embodiments will be described. FIG. 14 is a diagram for explaining a failure notification method. When the charging unit 50 detects a failure as described above in the first or second embodiment,
The billing unit 50 notifies the management unit 42 of that fact. Alternatively, the charging unit 50 may be provided with a state management memory,
When the above failure occurs, the failure content may be written in the state management memory and the management section 42 may read the failure information.

When the management unit 42 recognizes the failure, it notifies the call processor 16 of the fact, and the call processor 16 further notifies the main processor 15 of the information as necessary. The main processor 15 determines whether or not the charging process needs to be stopped according to the content of the notified failure. Further, when the SMDS processing device has a duplex configuration, the main processor 15 determines whether or not it is necessary to switch the system, and if necessary, switches the operating system and continues the charging process.

The SMDS has been described above as an embodiment of the present invention, but the present invention is not limited to this data transmission service, and a data unit is transferred at a predetermined interval to each data unit. It can be applied to a data transmission method in which a timing signal is generated. Also,
The present invention includes all methods of controlling the charging process based on the normality of a predetermined bit in the transfer data.

[0089]

EFFECT OF THE INVENTION In a billing system in which a data unit is transferred at predetermined intervals and a billing process is performed using a timing signal generated for each data unit, means for monitoring the cycle of the timing signal is provided. Since the billing process is performed while confirming the normality of the cycle, the reliability of the billing process is improved.

In the charging system for executing the charging process when the transfer data includes valid data, a means for confirming the normality of the transfer data is provided, and even when it is determined that the transfer data includes the valid data, When the normality of the transfer data cannot be confirmed, it is considered that a failure has occurred and a notification is sent to control the billing process, so if an error occurs in the information indicating whether or not the transfer data contains valid data. Also in, it is possible to prevent incorrect billing.

[Brief description of drawings]

FIG. 1 (a) and (b) are diagrams for explaining the principle of the first aspect and the second aspect of the present invention, respectively.

FIG. 2 is an overall schematic configuration diagram of an SMDS system.

FIG. 3 is a configuration diagram of a data transfer method between SMDS subscribers.

FIG. 4 is a configuration diagram of a common unit mainly showing a charging unit.

FIG. 5 is a timing chart of signals and clocks input to a common unit.

FIG. 6 is a configuration diagram of a first embodiment of the present invention.

FIG. 7 is a configuration diagram of a second embodiment of the present invention.

8A is a diagram showing a format of a source address SA, and FIG. 8B is a diagram showing a format of a destination address DA.

9 is a circuit diagram of a main part of an abnormality determination unit in FIG.

FIG. 10 is a diagram for explaining disassembly / assembly between connectionless data and a cell.

FIG. 11 is a diagram showing a format when connectionless data is decomposed into cells.

FIG. 12 is a diagram showing another configuration of the second exemplary embodiment.

FIG. 13 is a diagram illustrating cells processed in the configuration of FIG.

FIG. 14 is a diagram illustrating a method of notifying an abnormal state.

FIG. 15 is a diagram showing conversion between variable-length data and fixed-length cells in SMDS.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Cycle detection means 2 Notification means 3 Charging processing means 6 Extraction means 7 Notification means 8 Charging processing means 11 Line interface device 12 ATM switch 13, 14 Signal device 15 Main processor 16-18 Call processing processor 20 SMDS processing device 21 Transmission side line Section SMLP 22 reception side line section RMLP 23 common section COM 41 traffic monitoring section 42 management section 50 billing section 51 CF disconnection detection circuit 52 data extraction section 53 DA compression section 54 SA compression section 55 SA, carrier compression section 56 clock generation section 57 Billing RAM 58 MID holding unit 60 CF Period abnormality detection circuit 61 Period storage memory 62, 63 Counter 64 Comparison circuit 65 Flip-flop 66 OR circuit 70 SA abnormality detection circuit 71 SA setting unit 72 Extracted SA holding unit 73 Comparison circuit 74 Abnormal judgment Part 75 Exclusive OR circuit 76, 77 Free Flop 81 Cell classification extraction unit 82 Billing data collection unit 83 DA compression unit 84 SA compression unit 85 SA, carrier compression unit 86 Billing processing unit 87 MID holding unit 88 Timing control unit 90 SA abnormality detection circuit 91 Temporary storage memory 92 SA upper 8 Bit holding unit 93 SA Upper 8 bits extraction unit 94 Comparison circuit 95 Flip-flop

Claims (8)

[Claims] 1. A charging method for data transmission, wherein a data unit is transferred at a predetermined interval, and a charging process is performed using a timing signal generated for the data unit, in a cycle for detecting a cycle of the timing signal. Detecting means, notifying means for comparing the cycle detected by the cycle detecting means with the cycle of the timing signal in the normal state, and notifying the comparison result, and charging processing means for controlling the charging processing according to the notification by the notifying means. A charging method for data transmission, comprising: 2. The data transmission according to claim 1, wherein the period detecting means has a counter that counts up with a clock signal of a predetermined frequency and resets the count value each time the timing signal is received. Billing method. 3. The notifying means comprises a memory for storing a cycle of a timing signal in a normal state, a comparator circuit for comparing a cycle detected by the cycle detecting means with a cycle stored in the memory, The accounting system for data transmission according to claim 1, further comprising: a notification output circuit that outputs the comparison result of the comparison circuit as the notification when a timing signal is input. 4. A billing system for data transmission, wherein billing processing is executed for a data unit to be transferred when the data unit to be transferred contains valid data, and extracting means for extracting predetermined information from the data unit, A notification unit that compares the predetermined information extracted by the unit with a predicted value of the predetermined information and notifies the comparison result; and a charging processing unit that controls the charging process according to the notification from the notification unit. Data transmission billing method. 5. The extracting means extracts a predetermined bit in a transmission source address of the data unit, and the notifying means extracts the predetermined bit in the extracted transmission source address and a predetermined bit in the transmission source address. The charging method for data transmission according to claim 4, wherein the charging method is compared with a predicted value. 6. The extracting means extracts a predetermined bit in a transmission destination address of the data unit, and the notifying means extracts the predetermined bit in the extracted transmission destination address and the predetermined bit in the transmission destination address. The charging method for data transmission according to claim 4, wherein the charging method is compared with a predicted value. 7. The billing processing means performs billing processing when the transferred data unit includes valid data and the comparison results match.
Billing method for data transmission described in. 8. The billing processing means, even when the transferred data unit includes valid data, performs processing corresponding to the occurrence of a failure if the comparison results do not match. The charging method for data transmission according to claim 4.