JPH08265292A - Ofdm receiver - Google Patents

Abstract

PURPOSE: To pull in the frequency and phase of regenerative clocks in a wide range and to perform accurate clock regeneration without being influenced by the envelope change of reception signals. CONSTITUTION: This receiver is provided with quadrature detector 104 for quadrature detecting OFDM modulation wave input including a null symbol and a reference symbol for synchronization, correlation detection parts 110 and 111 for detecting the correlation of the reference symbol included in orthogonal detection output, a maximum value detector 113 for detecting the maximum value of correlation detection output, a phase error detection part 112 for detecting the phase error of clocks by obtaining the difference in front and behind a correlation detection maximum value based on maximum value detection output and a frequency error detector 114 for detecting the frequency error of the clocks by obtaining the deviation from a reference value of a timing when the correlation detection output becomes maximum based on the maximum value detection output. The clocks are regenerated by using the output of the phase error detection part 112 and the frequency error detector 114.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OFDM receiver, and more particularly to a clock recovery circuit for recovering a clock from a reference signal included in an OFDM modulated wave.

[0002]

2. Description of the Related Art In recent years, in the transmission of a video signal or an audio signal, a digital modulation method having high quality and high frequency utilization efficiency has been developed. Especially in mobile reception, orthogonal frequency division multiplexing (hereinafter referred to as OFDM
The adoption of a modulation method (called Orthogonal Frequency Division Multiplex) is under consideration.

The OFDM system is a system for modulating transmission digital data by dispersing it into a large number of carriers (hereinafter referred to as subcarriers) which are orthogonal to each other, and besides being characterized by being less susceptible to multipath interference, it has a frequency utilization efficiency. And has the advantage of being less likely to interfere with others.
For details of this OFDM system, refer to the document "Mobile Digital Audio Broadcasting Using OFDM" (NHK issue, VI
EW, May 1993) and the like, and only conventional techniques related to the present invention will be described here.

In OFDM transmission, data is assigned to a plurality of carriers which are orthogonal to each other to perform modulation and demodulation. This is the I
This can be realized by performing FFT processing and transmitting, and conversely performing FFT processing on the reception data on the receiving side.

Therefore, in the OFDM receiver, the FF
It is necessary to recover the clock from the OFDM-modulated signal input to perform T demodulation. Therefore, in general, OF
In DM transmission, reference symbols for clock recovery are periodically transmitted.

FIG. 8 shows an O using a conventional clock recovery circuit.
The configuration of an FDM receiver is shown, and FIG. 9 shows an example of an OFDM modulation method when transmitting reference symbols. For the reference symbol shown in FIG. 9, a sine sweep having a high autocorrelation as shown in FIG. 10 is generally used. Incidentally, FIG.
In (a), I-axis data is shown, and (b) shows Q-axis data.

In FIG. 8, an OFDM modulated wave shown in FIG. 9 is supplied to an input terminal 801, converted to a predetermined frequency by a frequency converter 802, and digitally converted by an A / D converter 803 based on a reproduction clock described later. After being converted into a signal, it is supplied to the quadrature detector 804.

The quadrature detector 804 quadrature-detects an input signal with a reproduction carrier and outputs a baseband OFDM-modulated wave. Its in-phase detection axis output (I signal) and quadrature detection axis output (Q signal). Are respectively the real part and the imaginary part of the OFDM modulated wave, and both are supplied to the FFT circuit 805.

The FFT circuit 805 performs FFT processing on the effective symbols of the input I signal and Q signal excluding the guard period, and its output is complex data representing the amplitude and phase of each carrier. Both are supplied to the equalizer 806.

The equalizer 806 corrects the amplitude / phase shift due to multipath for the input complex data, and its output is a demultiplexer 807.
The null symbol and the reference symbol are separated by, the demodulated I data output is output from the output terminal 808, and the demodulated Q data output is output terminal 80 with only the information symbol as received data.
It is output from 9.

On the other hand, I output from the quadrature detector 804
The signal and the Q signal are both branched and supplied to the null detector 810, envelope detection is performed during the null period, and the null detection timing is output to the counter 811. The counter 811 counts for a fixed period by the null detection timing signal, and the count value is the error detector 81.
2 is supplied.

The error detector 812 compares the input counter value for a certain period with the reference value. The comparison result is supplied to the loop filter 813 as an error detection signal and converted into a clock reproduction control signal. D / A81
4 is supplied. The D / A converter 814 converts the clock reproduction control signal into an analog signal, and the voltage controlled oscillator 8
Output as control voltage of 15.

The clock oscillated under the control of the control voltage is divided by the frequency divider 816 into the converted clock of the A / D converter 803, whereby clock recovery can be achieved.

The output of the null detector 810 is also supplied to the timing reproduction circuit 817. The timing reproduction circuit 817 is for generating various timing pulses according to the detection timing signal from the null detector 810.

[0015]

However, in the above-described conventional OFDM receiver, the null symbol period is detected by comparing the envelope level with a predetermined reference level, and clock recovery is performed. However, there is a problem in that the pull-in range is narrow, the C / N of the received signal is deteriorated, the multi-path is affected, etc., and the accurate clock reproduction cannot be performed.

The present invention has been made to solve the above-mentioned problems, and it is possible to pull in a wide range of the clock recovery of the receiving device, the deterioration of the C / N of the received signal and the influence of multipath. It is an object of the present invention to provide an OFDM receiver capable of accurately performing clock recovery without being affected even when the envelope changes due to.

[0017]

Means for Solving the Problems O according to the first invention of the present application
The FDM receiver receives an OFDM modulated wave including a null symbol and a reference symbol for timing synchronization, and detects a correlation between a quadrature detection means for quadrature detection of the input and the reference symbol included in the quadrature detection output of this means. Correlation detection means, maximum value detection means for detecting the maximum value of the correlation detection output of this means, and by calculating the difference before and after the maximum value of the correlation detection output based on the maximum value detection output of this means Phase error detecting means for detecting a phase error, and frequency error detecting means for detecting a frequency error of the clock by obtaining a deviation from a reference value of a timing at which the correlation detection output becomes maximum based on the maximum value detection output. And reproducing the clock using the outputs of the phase error detecting means and the frequency error detecting means.

In the OFDM receiving apparatus according to the second invention of the present application, the correlation detecting means has an I of the reference symbol.
Reference symbol generating means for generating axis data and Q axis data; first correlation calculating means for obtaining a correlation between the I-axis data output of the quadrature detecting means and the I-axis data output of the reference symbol generating means; Second correlation calculation means for obtaining the correlation between the Q-axis data output of the detection means and the Q-axis data output of the reference symbol generation means, and the outputs of the first and second correlation calculation means are each squared and added. And an amplitude detecting means for controlling the amplitude.

An OFDM receiver according to the third invention of the present application is provided with offset means for adding a predetermined value to the maximum value detected previously in the maximum value detecting means, and the input data and the output of the offset means are provided. It is characterized in that the maximum value of the input data series is detected by comparison.

In the OFDM receiving apparatus according to the fourth invention of the present application, the frequency error detecting means outputs a switching signal for selecting one of frequency control and phase control in clock recovery control according to the presence or absence of a frequency error. Frequency / phase control switching means for
One of the frequency control and the phase control in the clock reproduction control is selected.

An OFDM receiving apparatus according to a fifth aspect of the present invention is provided with a comparing means for outputting a maximum value detection flag indicating that the detected maximum value is equal to or higher than a predetermined level in the maximum value detecting means, Based on the maximum value detection flag, the clock regeneration control is performed when the maximum value detection flag is detected, and the clock regeneration control is not performed when the maximum value detection flag is not detected. To do.

[0022]

In the OFDM receiving apparatus according to the first invention of the present application,
Null symbol created by orthogonal frequency division multiplexing using a plurality of subcarriers, quadrature detection by inputting a received signal composed of a reference symbol and a large number of effective symbols, the correlation of the reference symbol contained in this signal The maximum value is obtained and detected, and the phase error of the clock is detected by obtaining the difference value before and after the correlation detection output based on the result of the maximum value detection output, and at the timing when the correlation detection output becomes maximum. The frequency error of the clock is detected by obtaining the deviation from the reference value, and the clock is reproduced based on the phase error detection result and the frequency error detection result.

That is, since the reference symbols have high autocorrelation, the reference calculation symbol position can be accurately detected by using the correlation calculation amplitude output. Based on the correlation calculation result, the maximum value detector can be used. By detecting the maximum value and performing phase control and frequency control based on the result, it is possible to accurately perform clock recovery in a wide range of pull-in without being affected by reception deterioration.

In the second invention of the present application, the correlation detecting means performs the correlation calculation of the I-axis data and Q-axis data of the reference symbol of the quadrature-detected signal and the signal from the generation of the reference symbol, and outputs the correlation calculation result. The outputs are squared and added, and the amplitude is calculated.

That is, the signal generated from the I-axis or Q-axis data of the reference symbol and the I of the quadrature detection output.
The results of the correlation calculation of the signals of the axis data and the Q-axis data are each squared and added to obtain the amplitude, so that the correlation can be reliably detected even when the input signal has a phase shift.

In the third invention of the present application, the maximum value detector adds a predetermined value to the previously detected maximum value, and compares this value with the input value to obtain the maximum value of the input data series. To detect.

That is, in the maximum value detector, a predetermined value is added to the maximum value of the correlation output previously detected, and this value is compared with the input value, so that the equalization by the multipath signal other than the desired wave is obtained. Even when the correlation output of the level (D / U = 0 dB) is detected, the desired wave can be detected as the maximum value.

In the fourth invention of the present application, the frequency error detecting means generates a switching signal for selecting frequency error control or phase control based on the frequency error result,
Clock switching is performed by selecting one of these switching signals. If there is a frequency error, only frequency control is performed and phase control is not performed. If there is no frequency error, frequency control is not performed and only phase control is performed. .

That is, the frequency error detector outputs a switching signal for switching between frequency control and phase control on the basis of the frequency error detection result, so that the phase error signal is detected when there is a clock frequency error. Acts not to use.

In the fifth invention of the present application, the maximum value detecting means determines and outputs a signal for determining whether or not the maximum value is detected, based on whether or not the maximum value is equal to or higher than a predetermined level. Clock control is performed only when detected, and clock control is not performed when not detected. That is, the clock control is not performed when the maximum value of the correlation detection output is not detected to prevent an adverse effect when the reference signal is disturbed.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block circuit diagram showing the configuration of an OFDM receiving apparatus according to the present invention. Input OF
As shown in FIG. 2, the DM modulated wave is assumed to be frame-configured with null symbols, reference symbols, and a large number of effective symbols. In the following embodiment, an example in which a sine sweep is used as the reference symbol will be shown.

An OFDM modulated wave received by a tuner (not shown) and converted into an intermediate frequency band signal (hereinafter referred to as an IF signal) is input to the input terminal 101. The OFDM-modulated wave given to the input terminal 101 is, for example, a QAM signal that has been OFDM-modulated on the transmitting side and then orthogonally modulated by a predetermined carrier and transmitted. Note that QAM is I corresponding to the real part of the complex representation.
A symbol can be represented by data and Q data corresponding to the imaginary part.

The OFDM modulated wave supplied to the input terminal 101 is converted into a predetermined frequency by the frequency converter 102, converted into a digital signal by the A / D converter 103, and then supplied to the quadrature detector 104. . Quadrature detector 1
In 04, the input signal is quadrature-detected by the reproduction carrier and a baseband OFDM modulated wave is output.

The in-phase detection axis output (I signal) and the quadrature detection axis output (Q signal) of the quadrature detector 104 are respectively OFDM.
The real part and the imaginary part of the modulated wave. The A / D converter 103 is A / D-converted by a clock recovered clock described later. The FFT circuit 105 performs an FFT process on the effective symbols of the input I signal and Q signal excluding the guard period.

The output of the FFT circuit 105 is complex data representing the amplitude / phase of each carrier. The equalizer 106 corrects the amplitude / phase shift due to multipath and the like, and the demultiplexer 107 performs null correction. The symbol and the reference symbol are separated, only the information symbol is received data, and the demodulated I data output is output from the output terminal 108.
The demodulated Q data output is output from the output terminal 109.

On the other hand, the I and Q outputs of the quadrature detector 104 are both branched and supplied to the correlation calculator 110. The correlation calculator 110 performs the correlation calculation between the reference symbol of the input signal and the internal reference symbol and outputs the correlation calculation output SI.
And SQ.

Here, the correlation calculator 110 fetches the effective symbol portion (N samples) of the reference symbol shown in FIG. 2 and the signals (M samples) of several tens of samples before and after it into the RAM, and then reads the read position of the RAM. Correlation calculation is performed between the signal shifted by one sample and the read output of the internal reference signal stored in the ROM. The calculation period control of the correlation calculation unit 110 is controlled by the address value from the address generation circuit 122.

The correlation calculation output SI and the correlation calculation output SQ are
The amplitude detector 111 takes absolute values, synthesizes (adds) them, and outputs them as an amplitude detection signal SI ² + SQ ² . The amplitude detection signal SI ² + SQ ² is supplied to the phase error detection unit 112. The phase error detector 112 outputs a difference value before and after the correlation peak value as a phase error detection signal, and the output is supplied to the frequency / phase switch 115.

On the other hand, the correlation peak value output from the phase error detector 112 is also supplied to the maximum value detector 113,
Here, the maximum value is detected, and the detection timing signal and the maximum value detection flag indicating that the detected maximum value is equal to or higher than a predetermined level are supplied to the frequency error detector 114.

The frequency error detector 114 fetches the address value output from the address generation circuit 122 at the maximum value detection timing and compares it with the reference value to detect the frequency error during the period when the detection flag is detected. The frequency error detection signal is the frequency / phase switch 1
15 are supplied. That is, the frequency error detector 114
The frequency / phase switch 115 outputs a control signal for switching the frequency / phase depending on whether or not a frequency error is detected.
Output to.

The frequency / phase switching unit 115 selectively outputs either the frequency error detection signal or the phase error detection signal based on the switching signal from the frequency error detector 114, and its output is The D / A converter 1 is supplied to the loop filter 116 and used as a clock reproduction control signal.
17 is supplied.

This D / A converter 117 converts the clock reproduction control signal into an analog signal, and the voltage controlled oscillator 118
Output as control voltage to. The clock oscillated under the control of the control voltage is divided by the frequency divider 119 into the conversion clock of the A / D converter 103. This allows clock recovery to be achieved.

The output of the maximum value detector 113 is also supplied to the timing reproduction circuit 120. The timing reproduction circuit 120 generates various timing pulses according to the detection timing signal from the maximum value detector 113.

FIG. 3 is a block circuit diagram showing a specific configuration of the correlation calculation unit 110 of FIG. In FIG. 3, RA
M301 inputs the in-phase detection output (I signal) and the quadrature detection output (Q signal) from the quadrature detector 104, and based on the RAM-W (write) address from the address generation circuit 122, the effective symbol portion of the reference symbol and Signals of several tens of samples before and after that are acquired. Also, the address generation circuit 1
Based on the RAM-R (read) address from 22,
The read signals are sequentially read out and output while shifting the reading position by one sample within the width of the effective period.

The in-phase I output signal and the quadrature Q output signal of the RAM 301 are supplied to multipliers 302 and 303, respectively.
Internal reference signal (S) read and output from ROM 304
Is calculated. The ROM 304 is read based on the ROM-R address from the address generation circuit 122.

SI output from the multipliers 302 and 303
The signals SQ and SQ are integrated into the values of N samples by the adders 305 and 306 and the latch circuits 307 and 308, respectively, and then taken into the latch circuits 309 and 310 to become correlation operation outputs SI and SQ. A clear signal is supplied to the latch circuits 307 and 308 at the start of the correlation calculation,
The previous calculation result is set to 0.
When the integration of N samples is completed, a clock signal is supplied to the latch circuits 309 and 310 to take in data.

FIG. 4 is a block circuit diagram showing a specific structure of the maximum value detector 113 of FIG. In FIG.
The correlation amplitude output supplied from the amplitude detector 111 is input to the terminal A of the comparator 401 and the latch circuit 402. The latch circuit 402 holds the maximum value of the correlation output, and when the reference signal is written in the RAM 301 of the correlation calculation unit 110, the output is cleared to 0 by the reset signal.

The output of the latch circuit 402 is input to the terminal B of the comparator 401 through the adder 403. Comparator 40
The output of 1 becomes H when A> B, and this is supplied to the clock terminal of the latch circuit 402, and the input signal is held as a new maximum value. The output of the comparator 401 is output as the maximum detection timing.

The adder 403 is an offset circuit 404.
A predetermined value output from is input and added to the output of the latch circuit 402. This is for stably detecting the maximum value of the correlation output even when the received signal includes a multipath signal having a large level.

In particular, when a multipath signal of D / U = 0 dB is present, the levels of the correlation peak due to the desired wave detected first and the correlation peak due to the multipath wave detected later become substantially equal. Even in such a case, as shown in FIG. 4, by offsetting the previously detected maximum value by a predetermined level, it is possible to stably determine the first correlation peak as the maximum value.

On the other hand, the correlation amplitude output from the amplitude detector 111 is also supplied to the comparator 405. The comparator 405 determines that the detected maximum value is equal to or higher than a predetermined level, and the determination result is output to the frequency error detector 114 as a maximum value detection flag.

FIG. 5 is a block circuit diagram showing a specific configuration of the phase error detector 112 of FIG. In FIG.
Correlation amplitude output SI ² + SQ ² from the amplitude detector 111
Is supplied to the adder 503 via the latch circuits 501 and 502. The adder 503 directly inputs the correlation amplitude output and performs a difference calculation with respect to the signals that have passed through the latch circuits 501 and 502. By this processing, the latch circuit 50
The correlation peak value is obtained from 1 (outputted to the maximum value detector 113), and the difference value before and after the peak is obtained from the adder 503.

The output of the adder 503 is supplied to the latch circuit 504. The latch circuit 504 takes in the difference signal of the output of the adder 503 at the maximum value detection timing from the maximum value detector 113, and the latch output thereof is output to the frequency / phase switch 115 as a phase error detection signal.

FIG. 6 is a block circuit diagram showing a specific configuration of the frequency error detector 114 of FIG. In FIG. 6, the latch circuit 601 is supplied with data indicating the offset amount at the read start point of the RAM 301 from the address generation circuit 122. The output of the maximum value detector 113 is supplied to the clock terminal of the latch circuit 601.
That is, the latch circuit 601 is configured to sequentially take in the address offset amount when the correlation output becomes maximum.

When the correlation detection is completed, the latch circuit 6
02, the timing signal is supplied to the latch circuit 601.
Data is captured. As a result, the shift of the read start point of the RAM 301 when the correlation output becomes maximum can be obtained. The output of the latch circuit 602 is the error signal detector 60.
3 is supplied.

This error signal detector 603 outputs the comparison result as a frequency error detection signal by comparing the output of the latch circuit 602 with a predetermined value. Further, it outputs a signal for performing frequency / phase switching control depending on whether or not the frequency error signal is detected.

Specifically, when there is a frequency error, only the frequency control is performed without performing the phase control, and when there is no frequency error, the frequency control is not performed and only the phase control is performed. It is controlled by the detection flag of the reference symbol supplied from the value detector 113, and when not detected, the frequency / phase control switching signal is set to the frequency side and the output is set to 0.

7 (a) to 7 (d) show the influence of the clock error due to the reference symbol correlation detection. FIG. 7 (a)
When the phase error of the clock is 0 degree, FIG. 7 (b) is 90 degrees, FIG. 7 (c) is 180 degrees, and FIG. 7 (d) is 360 degrees.
It shows the time of degree.

In this way, by using the difference value before and after the correlation peak as the error signal, the clock error of ± 180 degrees can be controlled. Further, a clock error in sample units can be detected from the timing shift of the correlation peak.

Therefore, the OFDM receiving apparatus having the above configuration controls the amplitude levels before and after the correlation peak value obtained by the amplitude detection processing of the correlation calculation result to be equal to each other, so that the reference symbol of the OFDM modulated signal Since the frequency error and the phase error are detected from the signal in which the correlation is detected and the clock is reproduced, the clock can be pulled in a wide range, and the C / N of the received signal is deteriorated and the influence of the multipath is exerted. Accurate clock reproduction can be performed without receiving such as.

[0061]

As described above, according to the present invention,
The clock recovery can be performed in a wide range, and even if the envelope is changed due to the deterioration of C / N of the received signal and the influence of multipath, the clock can be accurately reproduced without being affected.
An FDM receiver can be provided.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing the configuration of an embodiment of an OFDM receiving apparatus according to the present invention.

FIG. 2 is a diagram showing a frame structure of an OFDM modulated wave input of the embodiment shown in FIG.

FIG. 3 is a block circuit diagram showing a specific configuration of a correlation calculator of the embodiment shown in FIG.

FIG. 4 is a block circuit diagram showing a specific configuration of a maximum value detector of the embodiment shown in FIG.

5 is a block circuit diagram showing a specific configuration of the phase error detector of the embodiment shown in FIG.

FIG. 6 is a block circuit diagram showing a specific configuration of the frequency error detector of the embodiment shown in FIG.

FIG. 7 is a diagram showing the influence of a clock error in reference symbol correlation detection of the embodiment shown in FIG.
(D) shows clock phase errors of 0 degree, 90 degree, and 1
It is a figure which shows the time of 80 degrees and 360 degrees.

FIG. 8 is a block circuit diagram showing a configuration of a conventional OFDM receiver.

FIG. 9 is a diagram showing a frame structure of an OFDM modulated wave including a reference symbol in the conventional OFDM transmission system.

FIG. 10 is a diagram showing an example of a sine sweep waveform used as the reference symbol.

[Explanation of symbols]

101 ... OFDM modulated wave input terminal 102 ... Frequency converter 103 ... A / D converter 104 ... Quadrature detector 105 ... FFT circuit 106 ... Equalizer 107 ... Demultiplexer 108 ... Demodulation I data output terminal 109 ... Demodulation Q data output Terminal 110 ... Correlation calculation unit 111 ... Amplitude detector 112 ... Phase error detection unit 113 ... Maximum value detector 114 ... Frequency error detector 115 ... Frequency / phase switcher 116 ... Loop filter 117 ... D / A converter 118 ... Voltage Controlled oscillator 119 ... Frequency divider 120 ... Timing recovery circuit 122 ... Address generation circuit 301 ... RAM 302, 303 ... Multiplier 304 ... ROM 305, 306 ... Adder 307, 308, 309, 310 ... Latch circuit 401 ... Comparator 402 ... Latch circuit 403 ... Adder 404 ... Offset generation circuit 40 Comparator 501, 502 ... Latch circuit 503 ... Adder 504 ... Latch circuit 601, 602 ... Latch circuit 603 ... Error signal detector 801 ... OFDM modulated wave input terminal 802 ... Frequency converter 803 ... A / D converter 804 ... Quadrature detector 805 ... FFT circuit 806 ... Equalizer 807 ... Demultiplexer 808 ... Demodulation I data output terminal 809 ... Demodulation Q data output terminal 810 ... Null detector 811 ... Counter 812 ... Error detector 813 ... Loop filter 814 ... D / A converter 815 ... Voltage controlled oscillator 816 ... Divider 817 ... Timing recovery circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noboru Noboru 3-9 Shinbashi, Minato-ku, Tokyo 3-9 Toshiba Toshiba Abu E Co., Ltd.

Claims (5)

[Claims] 1. A quadrature detection means for inputting an OFDM modulated wave containing a null symbol and a reference symbol for timing synchronization and quadrature detecting the input, and detecting the correlation between the reference symbols included in the quadrature detection output of this means. Correlation detection means, maximum value detection means for detecting the maximum value of the correlation detection output of this means, and by calculating the difference before and after the maximum value of the correlation detection output based on the maximum value detection output of this means A phase error detecting means for detecting a phase error; and a frequency error detecting means for detecting a frequency error of the clock by obtaining a deviation from a reference value of a timing at which the correlation detection output becomes maximum based on the maximum value detection output. Of the phase error detecting means and the frequency error detecting means, and performing clock reproduction by using the outputs of the phase error detecting means and the frequency error detecting means.
M receiver. 2. The correlation detecting means, reference symbol generating means for generating I-axis data and Q-axis data of the reference symbol, I-axis data output of the quadrature detecting means and I-axis data of the reference symbol generating means. A first correlation calculating means for obtaining a correlation with an output; a second correlation calculating means for obtaining a correlation between the Q-axis data output of the quadrature detecting means and the Q-axis data output of the reference symbol generating means; 2. An OFDM receiving apparatus according to claim 1, further comprising: an amplitude detecting unit that squares and adds outputs of the second correlation calculating unit. 3. The maximum value detecting means includes an offset means for adding a predetermined value to the maximum value detected previously, and compares the input data with the output of the offset means to obtain the maximum value of the input data series. The OFDM receiving apparatus according to claim 1, wherein a value is detected. 4. The frequency error detecting means controls the frequency in clock recovery control according to the presence / absence of a frequency error.
A frequency / phase control switching means for outputting a switching signal for selecting either one of phase control is provided, and one of frequency control / phase control in clock recovery control is selected by the switching signal. Item 2. The OFDM receiver according to Item 1. 5. The maximum value detection means comprises a comparison means for outputting a maximum value detection flag indicating that the detected maximum value is equal to or higher than a predetermined level, and the maximum value detection flag is based on the maximum value detection flag. 2. The OFDM receiver according to claim 1, wherein when the detection flag is detected, clock reproduction control is performed, and when the maximum value detection flag is not detected, clock reproduction control is not performed.