JPH08255704A - Chip thermistor and its manufacturing method - Google Patents
Chip thermistor and its manufacturing methodInfo
- Publication number
- JPH08255704A JPH08255704A JP5880695A JP5880695A JPH08255704A JP H08255704 A JPH08255704 A JP H08255704A JP 5880695 A JP5880695 A JP 5880695A JP 5880695 A JP5880695 A JP 5880695A JP H08255704 A JPH08255704 A JP H08255704A
- Authority
- JP
- Japan
- Prior art keywords
- thermistor
- forming
- chip
- sintered body
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Details Of Resistors (AREA)
- Thermistors And Varistors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、プリント回路基板など
に表面実装されるチップサーミスタ及びその製造方法に
係り、特に、温度の上昇により抵抗値が減少する負特性
サーミスタであって、抵抗値や寸法精度のばらつきが少
なく、しかも、機械的強度にも優れたチップサーミスタ
及びこのようなチップサーミスタを歩留り良く製造する
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip thermistor surface-mounted on a printed circuit board or the like and a method for manufacturing the same, and more particularly to a negative characteristic thermistor whose resistance value decreases as temperature rises. The present invention relates to a chip thermistor having little variation in dimensional accuracy and excellent mechanical strength, and a method for manufacturing such a chip thermistor with high yield.
【0002】[0002]
【従来の技術】従来、チップサーミスタは、遷移金属酸
化物よりなるセラミックス焼結体の両端に外部電極を形
成する、或いは、絶縁性セラミックス基板の上にセラミ
ックスの厚膜ペーストを印刷法により塗布して焼成し、
得られた焼結体の両端に外部電極を形成することにより
作製されている。2. Description of the Related Art Conventionally, a chip thermistor has formed external electrodes on both ends of a ceramic sintered body made of a transition metal oxide, or coated a thick film paste of ceramics on an insulating ceramics substrate by a printing method. And burn,
It is produced by forming external electrodes on both ends of the obtained sintered body.
【0003】[0003]
【発明が解決しようとする課題】遷移金属酸化物のセラ
ミックス焼結体は、アルミナ、シリカなどの絶縁性セラ
ミックス材料に比べ機械的強度が弱く、特に多用される
低抵抗材料を用いたものは、低温で焼結されるため、そ
の傾向がとりわけ著しい。このため、プリント基板実装
時の機械的強度、或いは、実装後の温度サイクルにおい
て強度が十分でないため信頼性に欠けるという難点があ
る。A ceramic sintered body of a transition metal oxide has a lower mechanical strength than an insulating ceramic material such as alumina or silica. This tendency is particularly remarkable because it is sintered at a low temperature. Therefore, the mechanical strength at the time of mounting the printed circuit board, or the strength in the temperature cycle after the mounting is not sufficient, resulting in a lack of reliability.
【0004】この問題に対処するために、焼結体表面に
ガラスコートなどを施して強度向上を図るなどの工夫が
なされている(特開平3−250603号公報,特開平
3−250604号公報)が、表面実装部品に求められ
ている小型、薄型化の要求に対応するためには、未だ十
分な強度向上効果は得られていない。In order to deal with this problem, the surface of the sintered body is coated with glass or the like to improve the strength, etc. (JP-A-3-250603 and JP-A-3-250604). However, sufficient strength improving effect has not yet been obtained in order to meet the demand for smaller and thinner surface mount components.
【0005】一方、アルミナやマグネシア、或いはシリ
カなど高温で焼結される絶縁性セラミックス材料は、機
械的強度が高いため、絶縁性セラミックス基板上にサー
ミスタセラミックス厚膜ペーストを印刷してチップサー
ミスタを製造する手法では、上記のような欠点がない。
しかし、印刷法では、印刷された膜厚のばらつき、即
ち、寸法精度のばらつきや基板との反応によって、得ら
れるサーミスタの抵抗値又は温度係数のばらつきが大き
く、高特性化には向いていない。On the other hand, an insulating ceramic material such as alumina, magnesia, or silica that is sintered at high temperature has high mechanical strength, and therefore a thermistor ceramic thick film paste is printed on an insulating ceramic substrate to manufacture a chip thermistor. The method does not have the above-mentioned drawbacks.
However, in the printing method, variations in the printed film thickness, that is, variations in dimensional accuracy and reaction with the substrate cause a large variation in the resistance value or temperature coefficient of the thermistor to be obtained, and are not suitable for high performance.
【0006】本発明は上記従来の問題点を解決し、抵抗
値や温度係数等のサーミスタ特性のばらつきや寸法精度
のばらつきが少なく、しかも、機械的強度にも優れたチ
ップサーミスタ及びその製造方法を提供することを目的
とする。The present invention solves the above-mentioned problems of the prior art, and provides a chip thermistor having a small variation in thermistor characteristics such as a resistance value and a temperature coefficient and a variation in dimensional accuracy, and a method of manufacturing the same which is excellent in mechanical strength. The purpose is to provide.
【0007】[0007]
【課題を解決するための手段】請求項1のチップサーミ
スタは、サーミスタ素体の両端面に外部電極が形成され
たチップサーミスタにおいて、該サーミスタ素体は、絶
縁性セラミックスの焼結体と、サーミスタ形成用セラミ
ックスのグリーンシートとを積層した積層体を焼結一体
化してなることを特徴とする。A chip thermistor according to claim 1 is a chip thermistor in which external electrodes are formed on both end surfaces of a thermistor body, wherein the thermistor body is a sintered body of an insulating ceramic and a thermistor. It is characterized in that a laminated body in which a green sheet of forming ceramics is laminated is sintered and integrated.
【0008】請求項2のチップサーミスタは、請求項1
のサーミスタにおいて、前記焼結体とグリーンシートと
の間に内部電極を有することを特徴とする。The chip thermistor of claim 2 is the same as claim 1.
In the thermistor, the internal electrode is provided between the sintered body and the green sheet.
【0009】請求項3のチップサーミスタは、請求項1
又は2のサーミスタにおいて、前記外部電極形成端面を
除くサーミスタ素体の表面は厚さ50μm以下の無機物
層で被覆されていることを特徴とする。The chip thermistor of claim 3 is the same as claim 1.
Alternatively, the thermistor of No. 2 is characterized in that the surface of the thermistor element body excluding the external electrode forming end surface is covered with an inorganic layer having a thickness of 50 μm or less.
【0010】請求項4のチップサーミスタの製造方法
は、請求項2に記載のチップサーミスタを製造する方法
であって、絶縁性セラミックス焼結体よりなる薄板の少
なくとも一方の板面に電極パターンを形成する工程と、
該電極を形成したセラミックス焼結体の少なくとも電極
形成面にサーミスタ形成用セラミックスのグリーンシー
トを積層する工程と、得られた積層体を焼結一体化する
工程と、得られた焼結体をチップ状に切断する工程と、
切断されたチップの両端面に外部電極を形成する工程と
を含むことを特徴とする。A method for manufacturing the chip thermistor according to claim 4 is the method for manufacturing the chip thermistor according to claim 2, wherein an electrode pattern is formed on at least one plate surface of a thin plate made of an insulating ceramics sintered body. And the process of
A step of laminating a green sheet of ceramics for forming a thermistor on at least an electrode forming surface of a ceramics sintered body on which the electrode is formed, a step of sintering and integrating the obtained laminated body, and a chip of the obtained sintered body. A step of cutting into a shape,
And a step of forming external electrodes on both end surfaces of the cut chip.
【0011】請求項5のチップサーミスタの製造方法
は、請求項3に記載のチップサーミスタを製造する方法
であって、絶縁性セラミックス焼結体よりなる薄板の少
なくとも一方の板面に電極パターンを形成する工程と、
該電極を形成したセラミックス焼結体の少なくとも電極
形成面にサーミスタ形成用セラミックスのグリーンシー
トを積層する工程と、得られた積層体を焼結一体化する
工程と、得られた焼結体の板面に無機物層を形成した後
チップ状に切断する工程と、切断されたチップの両端面
に外部電極を形成する工程とを含むことを特徴とする。A method for manufacturing a chip thermistor according to claim 5 is the method for manufacturing a chip thermistor according to claim 3, wherein an electrode pattern is formed on at least one plate surface of a thin plate made of an insulating ceramics sintered body. And the process of
A step of laminating a green sheet of ceramics for forming a thermistor on at least an electrode forming surface of a ceramics sintered body on which the electrode is formed, a step of sintering and integrating the obtained laminated body, and a plate of the obtained sintered body. The method is characterized by including a step of forming an inorganic layer on the surface and then cutting it into chips, and a step of forming external electrodes on both end surfaces of the cut chips.
【0012】なお、本発明で使用するサーミスタ材料
は、正特性、負特性のいずれであっても良いが、表面実
装部品として数多く使用される移動体通信分野の温度補
償用には高精度の負特性サーミスタが求められることか
ら、本発明は特に負特性サーミスタに好適である。The thermistor material used in the present invention may have either a positive characteristic or a negative characteristic, but a highly accurate negative characteristic is used for temperature compensation in the field of mobile communication, which is often used as a surface mount component. The present invention is particularly suitable for a negative characteristic thermistor because a characteristic thermistor is required.
【0013】[0013]
【作用】本発明においては、絶縁性セラミックスの焼結
体を用いるため、機械的強度に優れたチップサーミスタ
とすることができる。しかも、この絶縁性セラミックス
の焼結体にサーミスタ形成用セラミックスのグリーンシ
ートを積層して焼結一体化するため、寸法精度や抵抗値
等の特性のばらつきの少ないチップサーミスタとするこ
とができる。In the present invention, since a sintered body of insulating ceramics is used, a chip thermistor having excellent mechanical strength can be obtained. Moreover, since a green sheet of the thermistor-forming ceramics is laminated on the sintered body of the insulating ceramics so as to be sintered and integrated, a chip thermistor with less variation in characteristics such as dimensional accuracy and resistance value can be obtained.
【0014】即ち、例えば、絶縁性セラミックス焼結体
の表面に内部電極を形成した後、サーミスタ形成用セラ
ミックスのグリーンシートを積層して焼結一体化した場
合、焼成時において絶縁性セラミックス焼結体自体の再
収縮は殆ど生じないため、この表面に形成された電極の
面積、及び焼結体の反対側の面に形成された対向電極と
の距離、或いは同一表面上に形成された他の電極との距
離などは殆ど変わらない。一方、サーミスタ形成用セラ
ミックスのグリーンシートは、焼結時に収縮するが、こ
の収縮が抵抗値に及ぼす影響は殆どなく、抵抗値のばら
つきを防止することができる。寸法についても、焼成時
の収縮はグリーンシートのみで起こり、焼結体について
は収縮が殆どないため、全体としての収縮量が小さく、
従って、寸法のばらつきが殆どなく、寸法精度の高いも
のとなる。That is, for example, when the internal electrodes are formed on the surface of the insulating ceramics sintered body and the green sheets of the thermistor forming ceramics are laminated and integrated by sintering, the insulating ceramics sintered body is sintered. Since almost no recontraction of itself occurs, the area of the electrode formed on this surface and the distance from the counter electrode formed on the opposite surface of the sintered body, or another electrode formed on the same surface The distance between and is almost unchanged. On the other hand, the green sheet of the thermistor-forming ceramic shrinks during sintering, but this shrinkage has almost no effect on the resistance value, and it is possible to prevent variations in the resistance value. Regarding the size, shrinkage during firing occurs only in the green sheet, and there is almost no shrinkage in the sintered body, so the overall shrinkage amount is small,
Therefore, there is almost no dimensional variation and the dimensional accuracy is high.
【0015】請求項2のチップサーミスタによれば、内
部電極を形成することにより、より低抵抗なチップサー
ミスタを得ることができる。According to the chip thermistor of the second aspect, the chip thermistor having a lower resistance can be obtained by forming the internal electrodes.
【0016】請求項3のチップサーミスタによれば、表
面の無機物層よりなる保護層によりサーミスタの信頼
性、耐久性、耐候性がより一層高められる。According to the chip thermistor of the third aspect, the reliability, durability and weather resistance of the thermistor are further enhanced by the protective layer made of the inorganic layer on the surface.
【0017】請求項4,5の方法によれば、このような
本発明のチップサーミスタを容易かつ効率的に製造する
ことが可能とされる。According to the methods of claims 4 and 5, such a chip thermistor of the present invention can be manufactured easily and efficiently.
【0018】特に、絶縁性セラミックス焼結体の薄板と
サーミスタ形成用セラミックスのグリーンシートの積層
体を焼結一体化したものをチップ状に切断加工するた
め、小型のチップサーミスタであっても高い寸法精度の
もとに、容易に大量生産することが可能である。In particular, since a laminated body of a thin plate of an insulating ceramics sintered body and a laminated body of a green sheet of ceramics for forming a thermistor is cut and processed into a chip shape, even a small chip thermistor has high dimensions. It is possible to mass-produce easily with accuracy.
【0019】また、請求項5の方法に従って、無機物層
形成後に切断加工することにより、個々のチップに無機
物層を形成する場合に比べて、無機物層の形成効率が飛
躍的に向上し、製造コストをより一層低減することが可
能となる。Further, according to the method of claim 5, by performing the cutting process after the formation of the inorganic layer, the forming efficiency of the inorganic layer is dramatically improved as compared with the case where the inorganic layer is formed on each chip, and the manufacturing cost is improved. Can be further reduced.
【0020】[0020]
【実施例】以下、図面を参照して本発明の実施例につい
て詳細に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【0021】図1(a)〜(h)は本発明のチップサー
ミスタの製造方法の一実施例を示す斜視図であり、図2
は図1(a)〜(h)の方法に従って製造されたチップ
サーミスタの断面図である。図3は本発明のチップサー
ミスタの他の実施例を示す断面図、図4は電極パターン
の実施例を示す模式図であり、図2に示す部材と同一機
能を奏する部材には同一符号を付してある。FIGS. 1 (a) to 1 (h) are perspective views showing an embodiment of the method of manufacturing the chip thermistor of the present invention.
FIG. 3 is a cross-sectional view of a chip thermistor manufactured according to the method of FIGS. FIG. 3 is a cross-sectional view showing another embodiment of the chip thermistor of the present invention, and FIG. 4 is a schematic view showing an embodiment of the electrode pattern. Members having the same functions as those shown in FIG. I am doing it.
【0022】図1に示す方法では、まず、絶縁性セラミ
ックス焼結体の薄板1を準備し(図1(a))、この薄
板1の一方の板面1Aに内部電極2の電極パターンを一
定間隔を置いて一定の幅で平行な列状に印刷し、乾燥す
る(図1(b))。必要あれば、次に、この薄板1を裏
返し、他方の板面1Bにも、同様の電極パターンを一定
間隔を置いて一定の幅で平行な列状に印刷し、乾燥す
る。その後、必要に応じて焼成して電極パターンの焼き
付けを行う。In the method shown in FIG. 1, first, a thin plate 1 of an insulating ceramics sintered body is prepared (FIG. 1A), and the electrode pattern of the internal electrodes 2 is fixed on one plate surface 1A of the thin plate 1. Printing is performed in parallel rows with a constant width at intervals and drying (FIG. 1 (b)). If necessary, the thin plate 1 is turned upside down, and the same electrode pattern is printed on the other plate surface 1B at regular intervals with a constant width in parallel rows and dried. After that, the electrode pattern is baked by firing if necessary.
【0023】次に、サーミスタセラミックス粉末と結合
材とを含む成形材料を成形し、これを薄板1と面寸法が
ほぼ同じ大きさとなるように切断してサーミスタ形成用
のグリーンシートを作成する。このグリーンシート3
A,3Bを、電極を焼き付けた焼結体の薄板1の両板面
に積層してプレス機により熱圧着させる(図1
(c))。その後、焼成して薄板1とグリーンシート3
A,3Bとを一体化させる。この焼成は、通常の場合、
1000〜1200℃で1〜5時間程度行う。Next, a molding material containing the thermistor ceramic powder and a binder is molded and cut so that the surface dimensions thereof are substantially the same as those of the thin plate 1 to form a thermistor forming green sheet. This green sheet 3
A and 3B are laminated on both plate surfaces of the thin plate 1 of the sintered body on which the electrodes are baked and thermocompression-bonded by a press machine (Fig. 1).
(C)). After that, it is baked and the thin plate 1 and the green sheet 3 are used.
Integrate A and 3B. This firing is usually
It is carried out at 1000 to 1200 ° C. for about 1 to 5 hours.
【0024】得られた焼結一体品4の一方の板面にガラ
スペーストを全面印刷した後乾燥する。乾燥後、焼結一
体品4を裏返して他方の板面にも同様にガラスペースト
を印刷した後乾燥し、その後ガラスペーストの焼き付け
を行って、焼結一体品4の両板面に無機物層5A,5B
を形成する(図1(d))。The glass paste is entirely printed on one plate surface of the obtained integrated sintered product 4 and then dried. After drying, the sintered integrated product 4 is turned over, the glass paste is printed on the other plate surface in the same manner, and then dried, and then the glass paste is baked, and the inorganic layer 5A is formed on both plate surfaces of the sintered integrated product 4. , 5B
Are formed (FIG. 1D).
【0025】無機物層5A,5Bを形成した後、焼結一
体品4を一定の間隔で細長い短冊状に切断して短冊状部
材6を得る(図1(e))。この短冊状部材6は、対向
する一対の側面にのみ無機物層5A,5Bが形成された
ものであるが、残る一対の側面にも前記と同様にして無
機物層5C,5Dを形成する。即ち、この短冊状部材6
を複数個短冊状部材整列用の治具に並べてガラスペース
トを印刷し、乾燥する。次に、この短冊状部材を反転さ
せて同様にガラスペーストを印刷して乾燥し、その後、
焼き付けを行う(図1(f))。After forming the inorganic layers 5A and 5B, the sintered integrated product 4 is cut into elongated strips at regular intervals to obtain strip-shaped members 6 (FIG. 1 (e)). The strip-shaped member 6 has the inorganic material layers 5A and 5B formed only on the pair of opposed side surfaces, but the inorganic material layers 5C and 5D are also formed on the remaining pair of side surfaces in the same manner as described above. That is, this strip-shaped member 6
Are arranged on a jig for aligning strip-shaped members, the glass paste is printed, and dried. Next, the strip-shaped member is turned over and the glass paste is printed and dried in the same manner, and thereafter,
Baking is performed (FIG. 1 (f)).
【0026】このようにして4側面を無機物層5A〜5
Dで被覆した短冊状部材6を端面に平行な方向に切断し
てチップ7を得る(図1(g))。このチップ7の無機
物層5が形成されていない両端面7A,7B及びこの両
端面7A,7B近傍の4側面にAg等の電極ペーストを
塗布して乾燥、焼き付けを行って外部電極8A,8Bを
形成し(図1(h))、更に、この外部電極の表面にN
iめっきを施し、更に、このNiめっき上に半田めっき
処理を行うことにより、めっき層9A,9Bを形成し
て、製品のチップサーミスタ10を得る。In this way, the four side surfaces are covered with the inorganic layers 5A to 5A.
The strip-shaped member 6 coated with D is cut in a direction parallel to the end face to obtain a chip 7 (FIG. 1 (g)). The external electrodes 8A, 8B are formed by applying an electrode paste such as Ag on both end faces 7A, 7B where the inorganic layer 5 of the chip 7 is not formed and the four side faces near the both end faces 7A, 7B, and drying and baking. (Fig. 1 (h)), and then N is formed on the surface of the external electrode.
By performing i-plating and further performing solder plating treatment on this Ni-plating, the plating layers 9A and 9B are formed, and the chip thermistor 10 of the product is obtained.
【0027】なお、本発明において、絶縁性セラミック
ス焼結体には、その熱膨張係数がサーミスタを構成する
セラミックス材料の熱膨張係数に近似している材料を選
択するのが好ましく、例えば、熱膨張係数が90〜12
0×10-7/℃のフォルステライト(2MgO・SiO
2 )を用いるのが好適である。この材料は熱膨張係数が
高いため内部電極との接合にも適している。In the present invention, it is preferable to select, as the insulating ceramics sintered body, a material whose thermal expansion coefficient is close to that of the ceramic material forming the thermistor. Coefficient is 90-12
0x10 -7 / ° C forsterite (2MgO ・ SiO
2 ) is preferably used. Since this material has a high coefficient of thermal expansion, it is also suitable for bonding to internal electrodes.
【0028】また、サーミスタ形成用セラミックスグリ
ーンシートの厚さが厚過ぎ、絶縁性セラミックス焼結体
薄板が薄過ぎると、絶縁性セラミックス焼結体を用いる
ことによる本発明の効果を十分に得ることができない。
逆に、サーミスタセラミックスグリーンシートの厚さが
薄過ぎるとサーミスタ特性が十分に得られない。従っ
て、サーミスタセラミックスグリーンシートの厚さは1
0〜100μmとするのが好ましく、このようなセラミ
ックスグリーンシートに対して、厚さ0.3〜1.0m
m程度の絶縁性セラミックス焼結体の薄板を用いるのが
好ましい。If the ceramic green sheet for forming the thermistor is too thick and the insulating ceramics sintered body thin plate is too thin, the effect of the present invention can be sufficiently obtained by using the insulating ceramics sintered body. Can not.
On the contrary, if the thermistor ceramic green sheet is too thin, the thermistor characteristics cannot be sufficiently obtained. Therefore, the thickness of the thermistor ceramics green sheet is 1
The thickness is preferably 0 to 100 μm, and the thickness of the ceramic green sheet is 0.3 to 1.0 m.
It is preferable to use a thin plate of an insulating ceramics sintered body of about m.
【0029】図1(a)〜(h)では、1枚の絶縁性セ
ラミックス焼結体の薄板の両板面に電極を形成して各々
グリーンシート3A,3Bを積層し、図2,図4(a)
に示す如く、内部電極2A,2Bが対向配置されたサー
ミスタを製造する方法を示したが、用いる絶縁性セラミ
ックス焼結体やグリーンシートの数やその積層配置、内
部電極配置等に特に制限はなく、例えば、内部電極2
A,2Bは、図4(b)に示すようなパターンのもの
が、図3に示す如く、ずれて形成されたサーミスタ10
Aであっても良い。また、図4(c)に示す如く、櫛型
の電極パターン2Cを採用することもできる。グリーン
シートを焼結体薄板の両板面に2枚ずつ積層し、積層し
たグリーンシート間に内部電極を形成して内部電極数を
増やすことにより、抵抗値の低減効果をより一層高める
こともできる。In FIGS. 1 (a) to 1 (h), electrodes are formed on both plate surfaces of a single thin plate of an insulating ceramics sintered body, and green sheets 3A and 3B are laminated on each other. (A)
As described above, the method of manufacturing the thermistor in which the internal electrodes 2A and 2B are arranged opposite to each other has been described, but there is no particular limitation on the number of insulating ceramics sintered bodies or green sheets to be used, their laminated arrangement, internal electrode arrangement, etc. , For example, the internal electrode 2
As for A and 2B, the thermistor 10 having the pattern as shown in FIG. 4B is formed by being shifted as shown in FIG.
It may be A. Further, as shown in FIG. 4C, a comb-shaped electrode pattern 2C can be adopted. The effect of reducing the resistance value can be further enhanced by stacking two green sheets on each plate surface of the sintered thin plate and forming internal electrodes between the stacked green sheets to increase the number of internal electrodes. .
【0030】[0030]
【発明の効果】以上詳述した通り、本発明のチップサー
ミスタ及びその製造方法によれば、抵抗値や温度係数の
ばらつきが小さくなると共に、実装や温度サイクル試験
に十分な機械的強度を備え、また、小型化において重要
な寸法精度にも優れ、かつ、高信頼性で、コスト的にも
安価なチップサーミスタが提供される。As described in detail above, according to the chip thermistor and the method for manufacturing the same of the present invention, variations in resistance value and temperature coefficient are reduced, and mechanical strength sufficient for mounting and temperature cycle tests is provided. Further, a chip thermistor which is excellent in dimensional accuracy, which is important in miniaturization, has high reliability, and is inexpensive in cost, is also provided.
【図1】本発明のチップサーミスタの製造方法の一実施
例を示す斜視図である。FIG. 1 is a perspective view showing an embodiment of a method for manufacturing a chip thermistor of the present invention.
【図2】本発明のチップサーミスタの一実施例を示す断
面図である。FIG. 2 is a sectional view showing an embodiment of the chip thermistor of the present invention.
【図3】本発明のチップサーミスタの他の実施例を示す
断面図である。FIG. 3 is a sectional view showing another embodiment of the chip thermistor of the present invention.
【図4】電極パターンの実施例を示す模式図である。FIG. 4 is a schematic view showing an example of an electrode pattern.
1 絶縁性セラミックス焼結体の薄板 2 内部電極(電極パターン) 2A,2B,2C,2D 内部電極 3A,3B グリーンシート 5 無機物層 7 チップ 8A,8B 外部電極 9A,9B めっき層 10,10A,10B チップサーミスタ 1 Thin Plate of Insulating Ceramics Sintered Body 2 Internal Electrode (Electrode Pattern) 2A, 2B, 2C, 2D Internal Electrode 3A, 3B Green Sheet 5 Inorganic Layer 7 Chip 8A, 8B External Electrode 9A, 9B Plating Layer 10, 10A, 10B Chip thermistor
Claims (5)
成されたチップサーミスタにおいて、該サーミスタ素体
は、絶縁性セラミックスの焼結体と、サーミスタ形成用
セラミックスのグリーンシートとを積層した積層体を焼
結一体化してなることを特徴とするチップサーミスタ。1. A chip thermistor in which external electrodes are formed on both end faces of a thermistor element body, wherein the thermistor element body is a laminated body obtained by laminating a sintered body of insulating ceramics and a green sheet of thermistor forming ceramics. A chip thermistor that is obtained by sintering and integrating.
結体とグリーンシートとの間に内部電極を有することを
特徴とするチップサーミスタ。2. The chip thermistor according to claim 1, further comprising an internal electrode between the sintered body and the green sheet.
前記外部電極形成端面を除くサーミスタ素体の表面は厚
さ50μm以下の無機物層で被覆されていることを特徴
とするチップサーミスタ。3. The thermistor according to claim 1 or 2,
A chip thermistor characterized in that the surface of the thermistor element body excluding the end face on which the external electrode is formed is covered with an inorganic layer having a thickness of 50 μm or less.
造する方法であって、 絶縁性セラミックス焼結体よりなる薄板の少なくとも一
方の板面に電極パターンを形成する工程と、 該電極を形成したセラミックス焼結体の少なくとも電極
形成面にサーミスタ形成用セラミックスのグリーンシー
トを積層する工程と、 得られた積層体を焼結一体化する工程と、 得られた焼結体をチップ状に切断する工程と、 切断されたチップの両端面に外部電極を形成する工程と
を含むチップサーミスタの製造方法。4. The method of manufacturing a chip thermistor according to claim 2, wherein a step of forming an electrode pattern on at least one plate surface of a thin plate made of an insulating ceramics sintered body, and the step of forming the electrode A step of laminating a green sheet of thermistor forming ceramics on at least the electrode forming surface of the ceramics sintered body, a step of sintering and integrating the obtained laminated body, and a step of cutting the obtained sintered body into a chip shape. And a step of forming external electrodes on both end surfaces of the cut chip, the method for manufacturing a chip thermistor.
造する方法であって、 絶縁性セラミックス焼結体よりなる薄板の少なくとも一
方の板面に電極パターンを形成する工程と、 該電極を形成したセラミックス焼結体の少なくとも電極
形成面にサーミスタ形成用セラミックスのグリーンシー
トを積層する工程と、 得られた積層体を焼結一体化する工程と、 得られた焼結体の板面に無機物層を形成した後チップ状
に切断する工程と、 切断されたチップの両端面に外部電極を形成する工程と
を含むチップサーミスタの製造方法。5. The method for manufacturing a chip thermistor according to claim 3, wherein a step of forming an electrode pattern on at least one plate surface of a thin plate made of an insulating ceramics sintered body, and the step of forming the electrode A step of laminating a green sheet of the thermistor forming ceramics on at least the electrode forming surface of the ceramics sintered body, a step of sintering and integrating the obtained laminated body, and an inorganic layer on the plate surface of the obtained sintered body. A method of manufacturing a chip thermistor, which includes a step of cutting the chip thermistor after forming, and a step of forming external electrodes on both end surfaces of the cut chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05880695A JP3246258B2 (en) | 1995-03-17 | 1995-03-17 | Manufacturing method of chip thermistor and chip thermistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05880695A JP3246258B2 (en) | 1995-03-17 | 1995-03-17 | Manufacturing method of chip thermistor and chip thermistor |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001244370A Division JP2002118003A (en) | 2001-08-10 | 2001-08-10 | Chip thermistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08255704A true JPH08255704A (en) | 1996-10-01 |
JP3246258B2 JP3246258B2 (en) | 2002-01-15 |
Family
ID=13094850
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP05880695A Expired - Fee Related JP3246258B2 (en) | 1995-03-17 | 1995-03-17 | Manufacturing method of chip thermistor and chip thermistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3246258B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10116708A (en) * | 1996-10-14 | 1998-05-06 | Mitsubishi Materials Corp | Chip-type thermistor and manufacture thereof |
JPH10144504A (en) * | 1996-11-06 | 1998-05-29 | Mitsubishi Materials Corp | Chip-type thermistor and its manufacture |
US6236668B1 (en) | 1998-06-29 | 2001-05-22 | Murata Manufacturing Co., Ltd. | Semiconductor laser apparatus and pumping circuit therefor |
CN105185490A (en) * | 2015-08-11 | 2015-12-23 | 太仓市高泰机械有限公司 | Negative temperature coefficient (NTC) thermistor element sintering and loading laminating technology |
-
1995
- 1995-03-17 JP JP05880695A patent/JP3246258B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10116708A (en) * | 1996-10-14 | 1998-05-06 | Mitsubishi Materials Corp | Chip-type thermistor and manufacture thereof |
JPH10144504A (en) * | 1996-11-06 | 1998-05-29 | Mitsubishi Materials Corp | Chip-type thermistor and its manufacture |
US6236668B1 (en) | 1998-06-29 | 2001-05-22 | Murata Manufacturing Co., Ltd. | Semiconductor laser apparatus and pumping circuit therefor |
CN105185490A (en) * | 2015-08-11 | 2015-12-23 | 太仓市高泰机械有限公司 | Negative temperature coefficient (NTC) thermistor element sintering and loading laminating technology |
CN105185490B (en) * | 2015-08-11 | 2018-04-17 | 太仓市高泰机械有限公司 | A kind of NTC thermistor element burns till dress alms bowl stacking technique |
Also Published As
Publication number | Publication date |
---|---|
JP3246258B2 (en) | 2002-01-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6311390B1 (en) | Method of producing thermistor chips | |
CN102971808A (en) | Chip thermistor and method for manufacturing the same | |
JP3246258B2 (en) | Manufacturing method of chip thermistor and chip thermistor | |
JPH10144504A (en) | Chip-type thermistor and its manufacture | |
JPH10116707A (en) | Chip type thermistor and its manufacturing method | |
JP3331807B2 (en) | Manufacturing method of multilayer chip thermistor | |
JPH1092606A (en) | Chip thermistor and its manufacture | |
JP3254970B2 (en) | Manufacturing method of multilayer composite element and multilayer composite element | |
JPS6339958Y2 (en) | ||
JPH09260105A (en) | Chip type thermistor and manufacturing method thereof | |
JP2002118003A (en) | Chip thermistor | |
JP2000124008A (en) | Composite chip thermistor electronic component and its manufacture | |
JP3248294B2 (en) | Chip inductor and manufacturing method thereof | |
JPH11195554A (en) | Multilayered ceramic electronic device and production of the same | |
JPH06251993A (en) | Chip type electronic part assembly | |
JPH08250307A (en) | Chip thermistor | |
JP3226013B2 (en) | Manufacturing method of thermistor | |
JP2755212B2 (en) | Manufacturing method of negative characteristic thermistor | |
JP2000082606A (en) | Chip-type thermistor and its manufacture | |
JP3269404B2 (en) | Chip type thermistor and manufacturing method thereof | |
JPS62169301A (en) | Temperature coefficient regulation of thick film resistance element | |
JP3245933B2 (en) | Resistor | |
JPH0555045A (en) | Chip inductor and its manufacture | |
JPH10241908A (en) | Composite element and its manufacturing method | |
JP2000082607A (en) | Chip-type thermistor and its manufacture |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20011002 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071102 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081102 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081102 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091102 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091102 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101102 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101102 Year of fee payment: 9 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101102 Year of fee payment: 9 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111102 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121102 Year of fee payment: 11 |
|
LAPS | Cancellation because of no payment of annual fees |